JPH11341600A - Fetching method of audio signal data and interface circuit for audio signal data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interface circuit for audio signal data capable of surely fetching the audio signal data. SOLUTION: An externally synchronized latch timing signal (CKPI 1) is generated and outputted by an externally synchronized latch timing signal generating circuit 4. An internally synchronized latch timing signals (CKP1 2-1, 2-2) which are not timewisely overlapped are generated by an internally synchronized latch timing signal generating circuit 5. When one of the signal (CKPI 2-1) and the signal (CKPI 2-2) is timewisely overlapped with the signal (CKPI 1), the other signal which is not overlapped with the signal (CKPI 1) is selected and outputted by a switching circuit 6. Thus, the data are exactly fetched by a latch 3A, etc., since the signal (CKPI 1) is not timewisely overlapped with the signal (CKPI 2) even when jitter exists in a channel signal (LRCK), etc., supplied from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio signal data fetching method and an audio signal data interface circuit which can reliably fetch audio signal data when the audio signal data is fetched from an external circuit to an internal circuit. About.

[0002]

2. Description of the Related Art Conventionally, in audio circuits and the like, L
When the audio signal data (SDATA) in which the channel signal and the R channel signal are alternately arranged are taken in from the outside, as shown in FIG.
K) and a channel signal (LRCK) indicating the timing of channel switching of the two-channel audio signal.

In general, the timing of the three signals from the external circuit is not specified with respect to the master clock generated by the internal circuit. However, for example, the frequency of the master clock is the channel signal (L
RCK) is 256 times the frequency. Therefore, it is necessary to synchronize between the above three signals and the signal of the internal circuit.

As shown in FIG. 5, an external serial audio signal data (SDATA) is supplied from an external synchronization signal (BI).
CK) and the transfer signal generated by the AND circuit based on the channel signal (LRCK), the L channel signal is sequentially transferred to the left shift register 1 and converted into parallel data, and then the R channel signal is converted to the right shift register (FIG. (Not shown), and is converted into parallel data.

When the transfer of the L-channel signal to the left shift register 1 is completed, the converted parallel data, as shown in FIG. Parallel data is first
It is taken in and held by the latch 2 (latched).
Note that the external serial pulse first generates signals LR1 and LR2 as shown in FIGS. 3B and 3C from the rise of the channel signal (LRCK) and the external synchronization signal (BICK), and further generates the signals LR1 and LR2. LR1 and signal LR2
Generated from the deviation.

Next, as shown in FIG. 1G, at the rise of the internal synchronization pulse independently generated by the internal circuit, the L channel signal stored in the first latch 2 is changed to the second signal.
The data is latched by the latch 3 and is terminated and held at the falling edge of the internal synchronization pulse.

By such an operation, the L-channel signal serially input to the left shift register 1 is subjected to serial-parallel conversion by the left shift register 1, and then is taken into the first latch 2 and further to the second latch. It is taken in by 3.

In the above description, only the L channel signal of the audio signal data (SDATA) has been described for the sake of simplicity, but the R channel signal is processed in the same manner as the L channel signal. .

[0009]

However, the phase of the above-mentioned channel signal (LRCK) may greatly change as in the case of BS channel switching, in which case the following inconvenience occurs. I do.

That is, when the two are separated from each other as in the external serial pulse shown in FIG. 6E and the internal synchronization pulse shown in FIG. 6G, no inconvenience occurs in operation. However, when the change point of the data at which the external serial pulse latches the data and the time at which the internal synchronization pulse determines the data overlap, the second latch 3 takes the change point of the data and takes in the correct data. You will not be able to do it.

In order to avoid such inconvenience, it is considered that the external serial pulse and the internal synchronization pulse should be synchronized with the rising and falling of the master clock of the internal circuit, respectively.

However, when jitter exists in the external synchronization signal (BICK) or the master clock, the internal synchronization pulse latches the pre-change data held in the first latch 2 or generates the data. Since the data after the change is latched, the second latch 3 has the inconvenience that the same data is fetched twice or data is skipped one by one.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for capturing audio signal data and an interface circuit for audio signal data, which can eliminate the above-mentioned problems caused by the jitter and can reliably capture the audio signal data. It is in.

[0014]

In order to solve the above-mentioned problems and to achieve the object of the present invention, the present invention according to the first aspect is directed to an audio signal data receiving audio signal data comprising a two-channel audio signal. The method of capturing, wherein the audio signal data input serially is sequentially captured and converted into parallel data, and the converted parallel data is converted into an external synchronization signal and a channel signal indicating a channel switching timing of the audio signal data. The first and second internal synchronization latch timing signals that do not overlap with each other in time are generated based on the internal synchronization signal and are temporarily captured and held by the external synchronization latch timing signal generated based on the external synchronization latch timing signal. One of the first and second internal synchronization latch timing signals is the external synchronization latch timing signal. When the overlap in time is switched to the other internal synchronization latch timing signal that does not overlap,
In accordance with the switched internal synchronization latch timing signal, the previously held parallel data is further fetched and held secondarily.

According to a second aspect of the present invention, there is provided an audio signal data interface circuit for receiving audio signal data composed of two-channel audio signals, wherein the serially input audio signal data is sequentially received for parallel data. Serial-parallel conversion means for converting the audio signal data into parallel data, first latch means for taking in and holding the audio signal data converted in parallel by the serial-parallel conversion means by an external synchronization latch timing signal, and holding the first latch means Second latch means for capturing and holding audio signal data by an internal synchronization latch timing signal, and generating the external synchronization latch timing signal based on the external synchronization signal and a channel signal indicating a channel switching timing of the audio signal data. External synchronous latch timing signal generating means And an internal sync latch timing signal generating means for temporally to generate first and second internal synchronous latch timing signal do not overlap each other on the basis of the signal,
One of the external synchronous latch timing signal generated by the external synchronous latch timing signal generating means and the first and second internal synchronous latch timing signals generated by the internal synchronous latch timing signal generating means is And selecting means for selectively supplying the other internal synchronizing latch timing signal which does not overlap with the second latch means when the timing overlaps.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating an example of an interface circuit according to an embodiment of the present invention.

As shown in FIG. 1, the interface circuit of this embodiment includes a left shift register 1A, a right shift register 1B, a first left latch 2A, a first right latch 2B, and a second left latch 3A. Right second latch 3B, external synchronous latch timing signal generating circuit 4, internal synchronous latch timing signal generating circuit 5, switching circuit 6, frequency dividing circuit 7, changeover switch 8, LR separating circuit 50,
LR separation circuit 60, AND circuit 9A, and AND circuit 9
B and an inverter 10.

The left shift register 1A sequentially takes in the L channel signals in the audio signal data (SDATA) in which the L channel signals and the R channel signals are alternately arranged in series in synchronization with the shift pulse, and converts them into parallel data. It is configured to convert. The shift pulse is composed of the external synchronization signal (BICK) and the L of audio signal data (SDATA).
On the basis of a channel signal (LRCK) indicating the timing of switching between the channel signal and the R channel signal,
It is generated by an AND circuit 9A.

The right shift register 1B is configured to sequentially fetch the R channel signal in the audio signal data (SDATA) in synchronization with the shift pulse and convert it into parallel data. The shift pulse is supplied to an external synchronization signal (B
ICK) and a channel signal (LRCK) based on the inverter 10 and the AND circuit 9B.

The left first latch 2A is connected to the LR separation circuit 50 based on the external synchronization latch timing signal (CKPI1) generated by the external synchronization latch timing signal generation circuit 4.
Is configured to capture and hold the parallel data stored in the left shift register 1A using the signal (CKPIL1) generated in (1). Similarly, the first right latch 2B captures and holds the parallel data stored in the right shift register 1B using the signal (CKPIR1) generated by the LR separation circuit 50 based on the external synchronization latch timing signal (CKPI1). It is configured to

The second left latch 3A is a signal (CKPIL) generated by the LR separation circuit 60 based on the internal synchronization latch timing signal (CKPI2) generated by the internal synchronization latch timing signal generation circuit 5 and selected by the switching circuit 6.
It is configured to take in and hold the data held in the left first latch 2A using 2). Similarly, the second right latch 3B outputs its internal synchronization latch timing signal (CK).
Using the signal (CKPIR2) generated by the LR separation circuit 60 based on PI2), the parallel data held in the right first latch 2B is fetched and held.

External synchronization latch timing signal generation circuit 4
Indicates an external synchronization signal (BICK) and a channel signal (LR)
CK) and its channel signal (LRCK) 25
It is configured to generate an external synchronization latch timing signal (CKPI1) based on a master clock (FS256) generated by an internal circuit (not shown) having a frequency six times as high.

Internal synchronous latch timing signal generation circuit 5
Is temporally based on a master clock (FS256), a clock (FS1) obtained by dividing the master clock (FS256) by the frequency divider 7, and a clock (FS8) obtained by the same frequency division. Internal synchronization latch timing signals (CKPI2-1) that do not overlap each other
And an internal latch timing signal (CKPI2-2).

The switching circuit 6 outputs one of the generated internal synchronization latch timing signal (CKPI2-1) and the internal synchronization latch timing signal (CKPI2-2) to the external synchronization latch timing signal generation circuit 4.
External synchronous latch timing signal (CKPI
When the signal overlaps with 1), the changeover switch 8 is configured to selectively output one non-overlapping internal synchronization latch timing signal.

The frequency dividing circuit 7 generates a clock (FS8) in which the frequency of the internal master clock (FS256) is reduced to 1/32, and further reduces the frequency of the frequency-divided clock (FS8) to 1/8. To generate a clock (FS1), and generate the generated clock (FS1).
8) and the clock (FS1) are output to the internal synchronous latch timing signal generation circuit 5.

Next, the detailed configuration of the external synchronization latch timing signal generation circuit 4, the internal synchronization latch timing signal generation circuit 5, and the switching circuit 6 of the circuit shown in FIG. 1 will be described with reference to FIG. .

External synchronization latch timing signal generation circuit 4
Are inverters 11 and 1 as shown in FIG.
2, a D flip-flop (DFF) 13, a D flip-flop 14, an exclusive OR circuit 15, a D flip-flop 16, a D flip-flop 17, and an AND circuit 18.

More specifically, as shown in FIG. 2, an external synchronizing signal (BICK) is input to the inverter 11, and the input external synchronizing signal (BICK) is inverted by the inverter 11 to be a D flip-flop. The clock is supplied to one of the clock input terminals of one of the loops 13 and 14, respectively.
The external synchronization signal (BI) inverted by the inverter 11
CK) is further inverted by the inverter 12 and supplied to the other clock input terminals of the D flip-flops 13 and 14, respectively.

A channel signal (LRCK) is input to the D input terminal of the D flip-flop 13, and the Q output terminal of the D flip-flop 13 is connected to the D output terminal of the D flip-flop 14.
Connected to input terminal. The Q output terminal of the D flip-flop 14 is connected to one input terminal of the exclusive OR circuit 15, and the exclusive OR circuit 15
The channel signal (LRCK) is input to the other input terminal of the.

The output terminal of the exclusive OR circuit 15 is connected to the D input terminal of the D flip-flop 16,
The Q output terminal of the D flip-flop 16 is connected to the D input terminal of the D flip-flop 17. A master clock (FS256) is supplied to one of the clock input terminals of the D flip-flops 16 and 17 after being inverted by the inverter 21. The other clock input terminals of the D flip-flops 16 and 17 are connected to a master clock (FS).
256) is supplied via the inverter 21 and the inverter 22.

The / Q (cuber) output terminal of the D flip-flop 17 is connected to one input terminal of the AND circuit 18, and the other input terminal of the AND circuit 18 is connected to the Q output terminal of the D flip-flop 16. . An external latch timing signal (CK) from the output terminal of the AND circuit 18
PI1) is an AND circuit 5 constituting the LR separation circuit 50
1 and 52 are input to one of the input terminals. Also,
The other input terminal of the AND circuit 51 has a channel signal (L
RCK) is input, and the other terminal of the AND circuit 52 is supplied with the channel signal (LRCK) via the inverter 53.
Is entered. Then, the output signal (CKPIL1) of the AND circuit 51 and the output signal (CKPIL) of the AND circuit 52 are output.
IR1) is output to the first left latch 2A and the first right latch 2B in FIG.

Next, the detailed configuration of the internal synchronization latch timing signal generation circuit 5 will be described. This internal synchronization latch timing signal generation circuit 5 includes, as shown in FIG.
Inverter 21, inverter 22, D flip-flop 23, D flip-flop 24, exclusive OR circuit 25, inverter 26, inverter 27, D flip-flop 28, D flip-flop 29, D flip-flop 30, and exclusive OR circuit 3
1 is comprised.

More specifically, as shown in FIG. 2, a master clock (FS256) is input to the inverter 21, and the input master clock (FS25) is input to the inverter 21.
6) is inverted by an inverter 21 and supplied to one clock input terminal of one of D flip-flops 23, 24, 29, 30. Further, the master clock (FS256) inverted by the inverter 21 is further inverted by the inverter 22 to generate the D flip-flops 23, 2
4, 29, and 30 are supplied to the other clock input terminals, respectively.

The output pulse (FS1) from the frequency divider 7 is input to the D input terminal of the D flip-flop 23. The Q output terminal of the D flip-flop 23 is connected to the D input terminal of the D flip-flop 24. The Q output terminal of the D flip-flop 24 is connected to one input terminal of the exclusive OR circuit 25, and the other input terminal of the exclusive OR circuit 25 is connected to the Q output terminal of the D flip-flop 23. An output terminal of the exclusive OR circuit 25 outputs an internal latch timing signal (CKPI2-1).

The output pulse (FS1) from the frequency divider 7 is input to the D input terminal of the D flip-flop 28. An output pulse (FS) from the frequency divider 7 is applied to one clock input terminal of the D flip-flop 28.
8) is inverted and supplied by the inverter 26, and the pulse (FS8) is supplied to the other clock input terminal of the D flip-flop 28 by the inverter 26 and the inverter 27.
Is supplied via Q of D flip-flop 28
The output terminal is connected to the D input terminal of the D flip-flop 29.

The Q output terminal of the D flip-flop 29 is D
The D input terminal of the flip-flop 30 is connected, the Q output terminal of the D flip-flop 30 is connected to one input terminal of the exclusive OR circuit 31, and the other input terminal of the exclusive OR circuit 31 is connected to the D flip-flop 29. Connected to Q output terminal. An output terminal of the exclusive OR circuit 31 outputs an internal latch timing signal (CKPI2-2).

Next, a detailed configuration of the switching circuit 6 will be described. As shown in FIG. 2, the switching circuit 6 includes an AND circuit 32, an AND circuit 33, and an SR flip-flop 3.
4 and a D flip-flop 35.

One input terminal of the AND circuit 32 is connected to the output terminal of the AND circuit 18, and the other output terminal is connected to the output terminal of the exclusive OR circuit 25. The output terminal of the exclusive OR circuit 25 is connected to one terminal 81 of the changeover switch 8.

One input terminal of the AND circuit 33 is connected to the output terminal of the AND circuit 18, and the other output terminal is connected to the output terminal of the exclusive OR circuit 31. The output terminal of the exclusive OR circuit 31 is connected to the other terminal 82 of the changeover switch 8.

The output terminal of the AND circuit 32 is connected to the S input terminal of the SR flip-flop 34,
Is connected to the R input terminal of the SR flip-flop. The Q output terminal of the SR flip-flop 34 is connected to the D input terminal of the D flip-flop 35,
The changeover contact 83 of the changeover switch 8 switches according to the output signal from the Q output terminal of the D flip-flop 35.

A master clock (FS256) inverted by the inverter 21 is supplied to one clock input terminal of the D flip-flop 35. The master clock (FS256) is supplied to the other clock input terminal of the D flip-flop 35 by the inverter 21 and the inverter 2.
2 are provided.

The internal synchronization latch timing signal (CKPI2) output from the changeover switch 8 is input to one input terminal of each of AND circuits 61 and 62 constituting the LR separation circuit 60. The output clock (FS1) of the frequency divider 7 is input to the other input terminal of the AND circuit 61, and the inverter 6 is input to the other input terminal of the AND circuit 62.
3, the output clock (FS1) is input. Then, the output signal of the AND circuit 61 (CKPIL
2) and the output signal (CKPIR2) of the AND circuit 62 are output to the left second latch 3A and the right second latch 3B in FIG. 1, respectively.

Next, the operation of the interface circuit configured as described above will be described with reference to FIGS. First, as shown in FIG.
When audio signal data (SDATA) composed of serial data in which channel signals are alternately arranged is input, the L channel signal in the audio signal data (SDATA) is shifted by the shift pulse output from the AND circuit 9A to the left shift register 1A. , And are converted into parallel data.

On the other hand, the R channel signal in the audio signal data (SDATA) is sequentially transferred to the left shift register 1B by the shift pulse output from the AND circuit 9B, and is converted into parallel data.

Next, the data stored in the left shift register 1A is output to the external synchronization latch timing signal generation circuit 4A.
External synchronous latch timing signal (CKPI
1), the signal (CK) generated by the LR separation circuit 50.
PIL1), it is captured and held by the first left latch 2A. Similarly, the data stored in the right shift register 1B is the external synchronization latch timing signal (CK)
In synchronization with the signal (CKPIR1) generated by the LR separation circuit 50 based on PI1), the signal is taken in and held by the right first latch 2B.

Further, the data stored in the left first latch 2A is generated by the internal synchronization latch timing signal generation circuit 5 and is subjected to LR separation based on the internal synchronization latch timing signal (CKPI2) selected by the selection circuit 6. Circuit 6
In response to the signal (CKPIL2) generated at 0, the signal is captured and held by the second left latch 3A. Similarly, data stored in the right first latch 2B is captured and held in the right second latch 3B by a signal (CKPIR2) generated by the LR separation circuit 60 based on the internal latch timing signal (CKPI2). You.

Next, specific generation of the above-described external synchronization latch timing signal (CKPI1) and internal latch timing signal (CKPI2) will be described with reference to FIGS.

The channel signal (L) input to the D flip-flop 13 and the exclusive OR circuit 15
RCK) changes from the “L” level to the “H” level as shown in FIG. 3A, and at this time, when the output of the D flip-flop 14 is at the “L” level, the exclusive OR circuit 15 (CKPI) is shown in FIG.
Changes from the “L” level to the “H” level.

At the next rise of the external synchronization signal (BICK), the D flip-flop 13 causes the channel signal (LR)
CK) at the “H” level, and the output of the D flip-flop 13 goes to the “H” level. Next, at the next fall of the external synchronization signal (BICK), the D flip-flop 14 captures the “H” level state of the D flip-flop 13, and the output of the D flip-flop 14 changes from “L” level to “H”. Change to a level. . As a result, the output signal (CK) of the exclusive OR circuit 15 is output.
PI) changes from “H” level to “L” as shown in FIG.
Change to a level.

As described above, the output signal (CKPI) of the exclusive OR circuit 15 is the channel signal (LR)
During the period from the rising edge of the external synchronization signal (BICK) to the rising edge of the external synchronizing signal (BICK), as shown in FIG.
Level.

Next, the output signal (CKPI) of the exclusive OR circuit 15 is the master clock (FS25).
At the rise of 6), the data is taken into the D flip-flop 16, and the output of the D flip-flop 16 changes from "L" level to "H" level as shown in FIG. At this time, the output of the / Q output terminal of the D flip-flop 17 is
It is at the “H” level as shown in FIG. Therefore, the external synchronization latch timing signal (CKPI1), which is the output of the AND circuit 18, is at the “H” level as shown in FIG. 2F, and the state of the “H” level is after the master clock (FS256). Continue until the rise.

The master clock (FS25)
The frequency of 6) is 256 times the frequency of the channel signal (LRCK). On the other hand, the clock (FS1) generated by the frequency dividing circuit 7 is the master clock (FS1).
256) is reduced to 1/256. The clock (FS8) generated by the frequency divider 7
Sets the frequency of its master clock (FS256) to 1
/ 32. Therefore, the channel signal (LRCK) and the clock (FS1) have the same frequency but different phases and are asynchronous (see FIGS. 3A and 3H).

The output clock (FS1) of the frequency dividing circuit 7 is
At the fall of the master clock (FS256), the level changes from "H" level to "L" level as shown in FIG. For this reason, the clock (FS1) is taken into the D flip-flop 23 at the fall of the master clock (FS256) after its fall, and the output (S3) of the D flip-flop 23 becomes as shown in FIG. As shown, the level changes from the “H” level to the “L” level. At this time, D
The output (S4) of flip-flop 24 is at "H" level. Therefore, the output signal (CKPI2-1) of the exclusive OR circuit 25 becomes "H" level. The “H” level of the output signal (CKPI2-1) continues until the next fall of the master clock (FS256).

As described above, the output signal (CKPI2-1) of the exclusive OR circuit 25 is obtained after the output clock (FS1) of the frequency divider 7 changes from the "H" level to the "L" level. Master clock (FS25
It goes to the “H” level during the period from the falling edge of 6) to the next falling edge (see FIG. 3L).

On the other hand, the output clock (FS) of the frequency divider 7
1) is taken into the D flip-flop 28 at the rise of the output clock (FS8) of the frequency dividing circuit 7, and the output signal (S5) of the D flip-flop 28 changes from "H" level to "H" as shown in FIG. L ”level.

The output signal of the D flip-flop 28 (S
5) is taken into the D flip-flop 29 at the falling edge of the master clock (FS256), and the output (S6) of the D flip-flop 29 changes from “H” level to “L” level as shown in FIG. Change. At this time,
The output (S7) of D flip-flop 30 is at "H" level. Therefore, the output signal (CKPI2-2) of the exclusive OR circuit 31 becomes "H" level. The “H” level of the output signal (CKPI2-2) continues until the next fall of the master clock (FS256).

As described above, the output signal (CKPI2-2) of the exclusive OR circuit 31 is obtained after the output clock (FS1) of the frequency divider 7 changes from the "H" level to the "L" level. The output clock (FS) of the circuit 7
8) changes from the “L” level to the “H” level, and then changes to the “H” level during the period from the fall of the master clock (FS256) to the next fall (see FIG. 10 (P)).

Therefore, the exclusive OR circuit 25
Output signal (CKPI2-1) and the exclusive
The output signal (CKPI2-2) of the OR circuit 31 has an interval of a half cycle of the output clock (FS8) of the frequency divider 7, that is, 16 cycles of the master clock (FS256).

The output signal (CKPI2-1) of the exclusive OR circuit 25 and the external synchronization latch timing signal (CKPI1) output from the AND circuit 18 are:
The AND operation is performed by the AND circuit 32, and the operation result is input to the S input terminal of the SR flip-flop circuit 34.

As shown in FIGS. 3F and 3L, the external latch timing signal (C
KPI1) and the output signal (CKPI2-1) of the exclusive OR circuit 25 temporally overlap,
Since the output (S8) of the AND circuit 32 changes from “L” level to “H” level as shown in FIG.
SR flip-flop 34 is set and its output attains "H" level.

The "H" level is taken into the D flip-flop 35 at the falling edge of the master clock (FS256), and its output (S9) is output as shown in FIG.
As shown in FIG. The "H" level causes the changeover contact 83 of the changeover switch 8 to assume the position shown in FIG. 2, so that the output (CKPI2-2) of the exclusive OR circuit 31 is output as the internal synchronization latch timing signal (CKPI2).

On the other hand, the external synchronization latch timing signal (CKPI1) output from the AND circuit 18 and the output signal (CKPI2-1) of the exclusive OR circuit 31
In the case of the overlap, the output of the AND circuit 33 changes to "H" level, the SR flip-flop 34 is reset, and the output of the Q output terminal thereof changes to "L" level. The “L” level is at the falling edge of the master clock (FS256) at the D flip-flop 35.
And its output (S9) becomes "L" level. By this "L" level, the changeover contact 83 of the changeover switch 8 switches from the position shown in FIG. 2 to the opposite position, so that the output of the exclusive OR circuit 25 (C
KPI2-1) is the internal synchronization latch timing signal (CK)
PI2). Such a state is continued until the external synchronization latch timing signal (CKPI1) output from the AND circuit 18 and the output signal (CKPI2-1) of the exclusive OR circuit 25 temporally overlap.

As described above, in the embodiment of the present invention, as described above, the internal synchronization latch timing signal (CKPI2-1) and the internal synchronization latch timing signal (CKPI2-2) which do not overlap in time are used. , One of which generates an external synchronization latch timing signal (CKP).
When the timing overlaps with I1) in time, the other internal synchronization latch timing signal which does not overlap is selected and output, and this state is continued.

Therefore, in the interface circuit of this embodiment, the channel signal (L
RCK) or external synchronization signal (BICK), even if jitter exists, the external synchronization latch timing signal (CKPI)
1) and the internal synchronization latch timing signal (CKPI2) do not overlap in time, so that the left second latch 3A and the right second latch 3B can accurately capture data, and capture the same data twice. Such inconvenience can be solved.

In the embodiment of the present invention, once the internal synchronization latch timing signal is determined, the internal latch timing signal is not switched unless the phase of the external clock changes significantly thereafter.
There is also obtained an effect that the operation of taking data into the latch 3A and the right second latch 3B can be performed stably.

In the interface circuit of this embodiment, the external synchronization latch timing signal (CKPI
It is preferable that the time interval between 1) and the internal synchronization latch timing signal (CKPI2) be sufficiently larger than the maximum jitter swing in order to stabilize the operation.

In the interface circuit according to the embodiment of the present invention, not only can each of the constituent elements be implemented as an LSI, but all of them can be realized by hardware, and a part of the interface circuit is implemented by a CPU (central processing unit). Can execute the processing according to a program stored in a storage medium such as a ROM.

[0068]

As described above, according to the first and second aspects of the present invention, audio signal data input in series is sequentially taken and converted into parallel data, and this parallel data is converted into an external synchronization signal and audio signal data. First and second internal synchronization latches which are temporarily captured and held by an external synchronization latch timing signal generated based on a channel signal indicating a channel switching timing of the above and which do not temporally overlap with each other based on an internal synchronization signal A timing signal is generated, and when one of the first and second internal synchronization latch timing signals temporally overlaps with the external synchronization latch timing signal, the other first internal synchronization latch timing signal does not overlap with the other. Since the retained parallel data is taken in secondarily and retained, external Be present such as jitter, etc. on a signal al supplied, without the external synchronizing latch timing signal and an internal synchronizing latch timing signal overlap in time,
Data can be imported accurately, and the same
Inconvenience such as taking in can be solved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a detailed configuration of an external synchronization latch timing signal generation circuit, an internal synchronization latch timing signal generation circuit, and a switching circuit.

FIG. 3 is a time chart illustrating an example of an operation of the circuit illustrated in FIG. 2;

FIG. 4 is a time chart for explaining a conventional technique.

FIG. 5 is an explanatory diagram of a conventional device.

FIG. 6 is a time chart for explaining a problem of the related art.

[Explanation of symbols]

 1A Left shift register 1B Right shift register 2A Left first latch 2B Right first latch 3A Left second latch 3B Right second latch 4 External synchronization latch timing signal generation circuit 5 Internal synchronization latch timing signal generation circuit 6 Switching circuit 7 Frequency division Circuit 8 Changeover switch 9A, 9B AND circuit 10 Inverter 50, 60 LR separation circuit

Claims (2)

[Claims] 1. A method for capturing audio signal data which captures audio signal data composed of two-channel audio signals, wherein the serially input audio signal data is sequentially captured and converted into parallel data. Data is temporarily captured and held by an external synchronization latch timing signal generated based on an external synchronization signal and a channel signal indicating a channel switching timing of the audio signal data, and does not overlap with each other in time based on the internal synchronization signal. First
And generating a second internal synchronous latch timing signal;
When one of the generated first and second internal synchronization latch timing signals temporally overlaps with the external synchronization latch timing signal, the signal is switched to the other non-overlapping internal synchronization latch timing signal. A method for capturing audio signal data, wherein the parallel data held previously is further secondarily captured and held by the switched internal synchronization latch timing signal. 2. An audio signal data interface circuit for receiving audio signal data composed of two-channel audio signals, comprising: serial / parallel conversion means for sequentially receiving the serially input audio signal data and converting it into parallel data. A first latch unit that captures and holds the audio signal data converted in parallel by the serial / parallel conversion unit using an external synchronization latch timing signal; and converts the audio signal data held in the first latch unit into an internal synchronization latch. A second latch unit that captures and holds the external synchronization signal based on a timing signal; an external synchronization latch timing signal generation unit that generates the external synchronization latch timing signal based on a channel signal indicating a channel switching timing of the external synchronization signal and the audio signal data; Time based on the internal synchronization signal. The do not overlap in 1
And an internal synchronization latch timing signal generating means for generating the second internal synchronization latch timing signal; an external synchronization latch timing signal generated by the external synchronization latch timing signal generating means; Selecting means for selectively supplying the non-overlapping internal synchronous latch timing signal to the second latch means when one of the first and second internal synchronous latch timing signals overlaps in time; An interface circuit for audio signal data, comprising: