JPH02130041A - Multiplexing device - Google Patents

Abstract

PURPOSE:To multiplex data as preventing the data from striking each other on an input/output bus even if two high speed lines exist by dividing a high speed line side quad into two parts, and providing the high speed line side quad of one side with a shift register, and delaying the synchronizing clock of the high speed line side quad of one side by this shift register. CONSTITUTION:A first high speed line side quad 5a sends input data to an input bus 3 as adapting it to the synchronizing clock 14 to be sent from a timing control circuit 7. Since it is determined beforehand to what terminal all the bits of the data to be sent from a first high speed line 6a are assigned, the data length of the total sum of them is known beforehand, and therefore, the value of a selector 11 in a second high speed line side quad 5b is set manually so as to be delayed by this data length portion. The second high speed line side quad 5b sends the input data to the input bus 3 as synchronizing with the synchronizing clock 15 after shift. Thus, the data from the first high speed line 6a and the data from the second high speed line 6b can be multiplexed without striking each other on the input bus 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field J] This invention converts a plurality of input data (digital signals) of, for example, 400 to 9600 B P 8 into a plurality of 1.544
The present invention relates to a multiplexing device that multiplexes MBFB data.

[Prior Art] FIGS. 4 and 5 are time charts showing an overall view of a conventional multiplexing device disclosed in Japanese Patent Application Laid-Open No. 61-163741 and a time chart C frame configuration 1) for explaining its operation. In the figure, (1) is a multiplexing device.

FIG. 6 is a block diagram showing the internal configuration of a conventional multiplexing device. In the figure, (1a) to (In) are low-speed lines connected to terminal cards (2a) to (2!ll), respectively. ing. The input bus (3) and output bus (4) are connected to the terminal card (
2a) to (2n) in common. (5) is a high-speed line side card, (input is a timing control circuit, both of which are connected to the input bus (3) and output bus (4).

(6) is a high-speed line, and is connected to the high-speed line side card (5) Ic.

In addition, the timing control circuit (7) also connects the address bus (
8), the synchronous clock (9) is output, and the address bus (
8) is connected to the terminal cards (2a) to (2n), and the synchronous clock (9) is connected to the high-speed line side card (5).

Next, the operation will be explained. The time chart in FIG. 5 shows a standard configuration of the PCM signal. As for the bit configuration, one frame consists of one synchronization bit and 192 data bits. Here there are 192 more
One of the bits is used to set the synchronization bit to 2.

If a code that has one period in 20 frames is used for the synchronization bit, it becomes possible to detect the period every 20 frames. Since one frame A is 125 μsec, one multiframe is 2.5 m5ec. Therefore, since 1 bit in 1 multiframe is 1 bit in 2.5 m5ec, 40
0 BPS information can be transmitted. Therefore, 400
For transmission of x rlB P
By allocating bits, it is possible to directly multiplex data from low speed to high speed. 19 during multiframe
There is 3 x 20 = 3860 bits of data.

Next, in Fig. 6, the timing control circuit (7) has a counter that operates cyclically at a cycle of 3860, and the counter that operates cyclically at a cycle of 3860 is connected to the high-speed line side card (5) once every 3860 times. The period clock (9) is being sent.

In addition, the timing control circuit (7) has a memory in which the addresses of the terminal cards (2a) to (2 and +) are associated with each of these 3860 counter values, and the address value output from this memory is It is sent to each terminal card (2a) to (2r+) via the address bus (8). This address value is compared with the address value of each card by the address decoder in the terminal cards (2a) to (2n), and the terminal cards (2a) to (2n) are input only when they are selected. Bus (3) and output bus (4) can be used.

The high-speed line side card (5) detects the synchronization bit from the data input from the high-speed line #1l (6), takes in the input data, and transfers the input data to the input bus (3) in accordance with the synchronization clock (9).
Send input data to. Also, the output is a synchronous clock (9
), and sends the data on the output bus (4) to the high speed circuit #1l (6).

[Problem to be solved by the invention 1 Since the conventional multiplexing device was configured as described above,
When there were two high-speed lines, there was a problem that data would collide on the bus.

This invention was made to solve the above-mentioned problems, and its purpose is to prevent data from colliding on the bus even if there are two high-speed lines.

[Means for Solving the Problems 1] A multiplexing device according to the present invention divides a high-speed line side card into two, provides a shift register on one of the high-speed line side cards, and provides a shift register on one side of the high-speed line side card. This allows the card's synchronization clock to be delayed.

[Operation 1] The shift register in this invention delays one synchronous clock until data transfer for the other high-speed line is completed, and controls timing to prevent data collision on the bus.

[Example 1 An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, (5a) is the first high-speed @J line side card, (5b) is the second high-speed line side card, and (6a) is the first
(6b) is a second high-speed line, and the second high-speed line side card (5b) includes a shift register (10
) and a selector (11) are provided, and a shift register (1
0) is connected to a synchronous clock (9) and a selector (11).

FIG. 2 is a time chart for explaining the operation in FIG.
16) is data on the first high-speed line, and (17) is data on the second high-speed line.

Next, the operation will be explained.

First and second high speed @JA1! Side card (5a), (5
In b), a synchronization bit is first detected from the bits input from the first and second high-speed circuits M (6a) and (6b), and input data is taken in. The first high-speed line side card (5a) sends input data to the input bus (3) in accordance with the synchronization clock (14) sent from the timing control circuit (7). For the data sent from the WCL high-speed line (6a), it is determined in advance which terminal all bits are assigned to, so the data length, which is the sum of the bits, is known in advance. Line side card (5b)
Manually set the value of the selector (11) in the data so that it is delayed by this data length. Second high-speed line side card (5
b) sends the input data to the input bus (3) in synchronization with the shifted synchronous clock (15), so that the input bus (3) as shown by the data (13) on the input or output bus The data from the first high-speed line (6a) above and '
There is no collision with the data from the high-speed line (6b) of $,2.

On the output side, as shown in the data (16) on the first high-speed line, the first high-speed line side card (5a) inserts a synchronization bit in accordance with the synchronization clock (14), and outputs the output bus ( 4) to the high-speed line (6a), press the button as shown in the data (17) on the second high-speed line, and the second high-speed line side card (5b) outputs the shifted synchronous clock (
15), and insert a synchronization bit according to the output (4).
) data faster #! (6b).

FIG. 3 shows another embodiment of the present invention, and the first feature is that the timing control circuit (7) and the selector (11) are connected by the selector signal All (12). The one in FIG. 3 uses the selector control signal (12) from the timing control circuit (7) to
). Since the timing control circuit (7) manages 3860 bits,
It is easy to control the value of the selector (11), and in this way the equivalent transmission speed of the high-speed line can be changed, so that the bus can be used effectively.

Note that the above embodiment describes the case where there are two high-speed lines, but fc may be three or more. In this case, the shift register (10) is similarly used to shift three or more synchronized clocks, By preventing the respective data from overlapping, the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, by using a shift register, even when there are two 1m high-speed circuits, data can be multiplexed without colliding on the input/output bus, and the values of the selectors can be changed freely. It has the effect of being extremely efficient because it can be set to .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiplexer showing one embodiment of the invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a multiplexer showing another embodiment of the invention. 4 is an overall diagram of a conventional multiplexing device, FIG. 5 is a time chart for explaining the operation of the conventional multiplexing device, and FIG. 6 is a block diagram of the conventional multiplexing device. It is. In the figure, (1) is a multiplexing device, (la) to (1n)
is a low-speed line, (2a) to (2rl) are terminal cards, (3
) is the input bus, (4) is the output bus, (5) is the high-speed line side card, (6) is the high-speed line, (7) is the timing control circuit, (8) is the address no? (9) is a synchronization clock, (10) is a shift register, (11) is a selector, and (12) is a selector control signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Fig. 1 Iα, ~/71 ft (far E1 green 3, input bus + engineering j) guku 6L0L-1b: 1yirajL S, atto input bar matade synchronous 70 ft

Claims (1)

[Claims] In a multiplexing device that converts multiple low-speed data into multiple high-speed data and multiplexes the data, it has a bus that supplies a synchronized clock that is commonly used by each high-speed data card, and each high-speed data In the card, a shift register is connected to the synchronization signal input from the bus, a selector is connected to this shift register, and the output of this selector is used as a synchronization clock for each high-speed data card, and the value of the selector is manually set. A multiplexing device that is characterized by being able to