JPH0461528A - Time division multiplexer/demultiplexer - Google Patents

Abstract

PURPOSE:To decrease a circuit scale when multiplexing/demultiplexing and multiplexed relay are required after transmission line maintenance information is terminated/generated and when a head of actual information and an overhead can take a variable position with respect to a basic frame by processing the transmission line maintenance information inserted to each channel after multiplexing/demultiplexing without serial/parallel conversion. CONSTITUTION:The output of a low-order group address counter 25 provided on every multiplex channel separately and operated separately synchronously with the phase of an input data signal is inputted to a decoder 26 with output enable terminal, which generates a signal to terminate/generate transmission line maintenance information and it is sent to additional information termination/generating circuits 27a-27n. A data resulting from processing the additional information of all channels is outputted from a line X as it is in the case of multiplex relaying and inputted to buffers 28a-28n with a pulse from the decoder 26 at every channel, in which processing such as speed conversion to low-order group and replacement into in-station clock is implemented and the result is outputted to lines A, B-N.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a time division multiplexing/demultiplexing device, and in particular, the present invention relates to a time division multiplexing/demultiplexing device, and in particular, the present invention relates to a time division multiplexing/demultiplexing device, and in particular, after transmission line maintenance information is terminated and generated, it is necessary not only to demultiplex it but also to repeat multiplexing and relaying. , or a frame structure in which the beginning of the information string and overhead has a variable position with respect to the basic frame.

(Conventional technology) Conventionally, there has been a device of this type as shown in FIG.

This figure is shown in the conventional example of Japanese Patent Application Laid-Open No. 63-10833. In the figure, (1) and (2) are respectively time division multiplexing and demultiplexing devices (hereinafter abbreviated as TDM), and (3)
and (4) are data line P and end device (hereinafter referred to as DC), respectively.
(abbreviated as E), (5a) to (5b) are buffers, respectively, and (6) and (7) are shift registers (SR
), (8) is the synchronization signal generation circuit (SYN), (9)
(10) and (11) are shift registers (SR), (12a) to (12d) are ant circuits, (13a) to (13d) are buffers, and (14) is a synchronization signal check circuit. (DET),
(15) is a control section.

Next, the operation will be explained.

As an example of conventional general TDM, here we will use the diagram shown in Fig. 2 (a).
), (b), for example, consider the case where 4-bit multiplexing is performed and the -me synchronization pulse is multiplexed with 1 bit every 4 bits. The transmitted signal has a multiplexing rate of 5
T
In DM (1,), the switch mechanism allows the synchronization signal F, channel A, channel B, channel C,
Channel Df! - They are arranged as shown in FIG. 2(b) and sent out in serial format, and the TDM (2) on the receiving side converts and outputs each channel data into parallel signals using a similar switch mechanism.

An example of the conventional TDM circuit configuration is shown in Figure 2(c).
As shown in FIG. 2, on the transmitting side, the data of each channel A to D is inputted to buffers (5a) to (5d), respectively, and further inputted in parallel to (a) to (d) of a shift register (6).

The synchronizing signal F output from the synchronizing signal generating circuit (8) is added to the output signal and sent to the line.

On the receiving side, the received serial format signal is input to the shift register (10), and is sequentially shifted as (d) - (a) by the output clock of the control section (15), so that each channel's glue data is converted into a regular one. When shifted to the position, AND circuits (12a) to (12d) are opened and input to buffers (13a) to (+3d).

Further, the received signal is sent to the synchronization signal check circuit (14) via the shift register (11), where the synchronization signal F is detected and the clock CLK synchronized with this synchronization signal F is detected.
is output from the control section (15).

Therefore, in conventional time division multiplexing and demultiplexing processing, processing of additional information for transmission line maintenance and the like is performed by a low-order group frame counter using a low-order group clock.

[Problem to be solved by the invention] Since the conventional time division multiplexing m processing method is configured as described above, after transmission line maintenance information is terminated and generated, it is not only demultiplexed but also remultiplexed. In the case of relaying, the multiplexing circuit shown in the conventional example is required, which leads to an increase in the circuit scale, and CCITT Recommendations G707 and 708
, 709
(e Interface) When processing a g-level frame, if the actual information and the beginning of the overhead are at variable positions with respect to the basic frame, the conventional method has the problem of increasing and complicating the circuitry.

This invention was made to solve the above-mentioned problems, and it is necessary not only to terminate and demultiplex transmission line maintenance information but also to multiplex and relay it after it is generated, and when it is necessary to multiplex and relay the information at the beginning of the actual information and overhead. An object of the present invention is to obtain a time division multiplexing/demultiplexing device that can reduce the circuit scale even when variable positions can be taken with respect to a basic frame.

[Means to solve the problem]

The time division multiplexing and demultiplexing device according to the present invention provides a head position pulse of information of each multiplexed channel generated by a means for decoding a frame counter output after establishing frame synchronization or other means such as pointer processing, and a head position pulse of information for each multiplexed channel. The counter phase is controlled by the valid position pulse of the information, and the low-order group address counter operates with the clock before demultiplexing, and the output of this low-order group address counter is input, and the output is enabled by the pulse decoded from the above frame counter. It is equipped with a decoder circuit that performs control, and a circuit that processes control information such as transmission line maintenance that is allocated to each multiplexed channel of input data before multiplexing by the ratio cabling of this decoder circuit.

[Effect]

In this invention, in order to process the transmission line maintenance information inserted into each channel after demultiplexing without serial/parallel conversion, a low-order group address counter with count enable and count reset is provided for each channel. This counter operates with a high-order group clock, advances the count when valid data for each channel arrives, and makes the decoder output valid.

[Example] Hereinafter, an example of the present invention will be described based on FIG. 1. FIG. 1 is a block diagram of time-division multiplexing and demultiplexing snowmaking according to this embodiment. In the figure, (21) is a frame counter; (21) is a frame counter;
22 is a decoder that decodes the output of the frame counter (2]), (23) is a pointer processing circuit, and (24a)
, (24b) is a selection switch, (25) is a low-order group address counter with a reset and count enable terminal that recognizes the frame phase after demultiplexing, (26) is a decoder that decodes the output of this counter (25), (
27a), (27b), . . . (27n) are additional information termination/generation circuits that process transmission line maintenance information determined for each of the n channels using the decoder output of each channel; (28a), (28b), -, (28
n) is a buffer circuit that performs conversion to a low-order group speed, transfer to the local clock, etc.

Next, the operation will be explained. The received signal is first sent to the synchronization signal check circuit (14), where the synchronization signal is detected, and by synchronizing the phase with this synchronization signal, the frame counter (21) performs a counting operation in synchronization with the received signal. The decoder (22) uses this frame counter (21
) is decoded to generate a frame synchronization position verification pulse and sent to the synchronization signal check circuit (14) to maintain frame synchronization.

This decoder (22) also generates pulses that control the lower order group atrescara (25) and the decoder (26). In addition, if the basic frame structure can have a variable position with respect to the start of actual information and overhead using a pointer, etc., with respect to the basic frame, a pulse is generated to notify the position of the pointer indicating this variable position, and the pointer is processed. It is passed to the circuit (23).

The selection switches (24a) and (24b) are used to control the output pulse of the pointer processing circuit (23) when the actual information and the beginning of the overhead can take variable positions with respect to the basic frame due to a pointer or the like in the basic frame structure. Next group address counter (25) and decoder (26)
), and if not, selects control by the output pulse of the decoder (22).

The low-order group address counter (25) corresponds to the multiplexed channel number according to a predetermined basic frame structure,
For example, in the case of #1 channel, a control signal is output from the decoder (22) or from the pointer processing circuit (23) to advance the counter when the #1 data is valid and reset the count at the beginning position of the #1 data. It is output and input to the count enable terminal and reset terminal of the low-order group address counter (25) to perform a counting operation. This low-order group address counter (25) and decoder (26)
are provided separately for each multiplexed channel and operated separately in synchronization with the phase of the input data signal of each multiplexed channel. The output of the low-order group address counter (25) is input to a decoder (26) with an output enable terminal, which generates a signal for terminating and generating the transmission line maintenance information provided for each multiplexed channel, and outputting the additional information terminating/generating signal. Generation circuit (27a)
, (27b) s..., (27n).

The additional information termination/generation circuit (27a) processes the maintenance information corresponding to the #1 multiplexed channel of the input received data based on the output pulses of the low-order group address counter (25) and the decoder (26). Additional information termination/generation circuit (
27b) outputs the maintenance information corresponding to the multiplexed channel #2 from the output data of the additional information termination/generation circuit (27a) to the low-order group address counter #2 (not shown in Figure 1) and the decoder #2 (not shown in Figure 1). Processing is performed based on the output pulses (omitted in Figure 1). Processing is performed in the same manner up to the n-th channel.

When the data processed with the additional information of all channels is multiplexed and relayed, it is output as is from X, and when demultiplexed output is required, a decoder (26 ) along with pulses from the buffers (27a), (27b),...
(27n), and undergoes processing such as speed conversion to a lower order group and transfer to the internal clock, A, B...,
Output to N.

Therefore, in this embodiment, a low-order group address counter with count enable and count reset and a decoder with output disable are used for each multiplexed channel. Since the count is advanced when data arrives and the decoder output is enabled, it is possible to process the transmission line maintenance information inserted into each channel after demultiplexing without serial conversion.

In the above embodiment, the additional information termination/generation circuit (27
a) , (27b) s= , (27n) may be connected in cascade or in parallel. In this case, the multiplexed relay output X is output from each additional information termination/generation circuit (27a)
, (27b).

. . , (27n) may be selected and generated.

(Effects of the Invention) As described above, according to the present invention, when not only demultiplexing but also multiplexing and relaying is required after transmission line maintenance information is terminated and generated, and when the beginning of the actual information and overhead is This has the effect that the circuit scale can be reduced even when a variable position is obtained.

[Brief explanation of drawings]

Figure 1 shows an embodiment of the present invention. FIG. 2 is a block diagram showing a conventional multiplex processing method. In the figure, (21) is a frame counter, (22) is a decoder that decodes the output of the frame counter (21), (23) is a pointer processing circuit, (24a), (
24b) is a selection switch, (25) is a low order group address counter, (26) is a decoder, (27a), (27
b) , .=-, (27n) is an additional information termination/generation circuit, and (28) is a buffer circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] After frame synchronization is established, the counter phase is controlled by the head position pulse of the information of each multiplexed channel and the effective position pulse of the information of each multiplexed channel, which are generated by means such as decoding the frame counter output or other means such as pointer processing. and a low-order group address counter that operates with a clock before demultiplexing, a decoder circuit that receives the output of this low-order group address counter and performs output enable control using pulses decoded from the frame counter, and this decoder circuit. 1. A time division multiplexing/demultiplexing device comprising: a circuit for processing control information such as transmission path maintenance assigned to each multiplexed channel of input data before demultiplexing using output pulses.