JPS6360637A - Synchronizing multiplex system - Google Patents

Abstract

PURPOSE:To correspond a CH number at multiplexing to that after multiplexing/ demultiplexing by using a difference between a specific channel CH number connected to a control latch means and a specific CH number on a basic signal frame so as to control a multiplexing/demultiplexing latch circuit. CONSTITUTION:A serial/parallel conversion means 11 applies serial/parallel conversion to an input multiplexing signal to output a parallel signal having a multiplexed CH number having different timings TM and input them to a multiplex/demaltiplex latch means 16. A control latch means 12 latches a signal of a specific CH of the output of the means 11 at a fixed timing and sends it to a control signal identification means 14. The means 14 identifies the multiplexed CH number of the specific CH latched by the means 12 and detects the difference with the multiplexed CH number connected to the means 12. A TM control means 15 generates a TM signal having a TM difference corresponding to the difference of the CH number detected by the means 14 to the latched timing TM in the means 12. The means 16 uses the TM signal of the means 15 to latch the output of the means 11 thereby making the CH number of the basic signal of the multiplexed CH number at multiplexing coincident with the CH number after multiplexing/demultiplexing and outputting the result.

Description

[Detailed description of the invention] [Summary] A basic signal is created by inserting a control signal necessary for multiplexing into a frame structure of a basic signal rate, and this basic signal is multiplexed to produce a high-order multiplexed signal. In the receiving section of the synchronous multiplexing method that forms This allows for stable correspondence between the channel at the time of demultiplexing and the channel after demultiplexing on the receiving side.

[Industrial application field]

The present invention relates to a PCM signal multiplexing system, and particularly to a synchronous multiplexing system in which basic signals are multiplexed in an integral multiple.

In order to transmit and exchange wideband signals such as video signals,
In the conventional multiplexing system based on PCM hierarchy, the time slot of each signal in the group signal is not fixed.
It was extremely difficult to directly extract and output the desired signal from the group signal. Additionally, as services become wider in bandwidth, construction of synchronous networks using higher-order groups is being considered to reduce the effects of jitter and the like. In this situation, broadband l5DN
A synchronous multiplexing method is being considered in which a number + M b ps is selected as the basic signal rate of , and an integer multiple thereof is allowed as the multiplexed PCM hierarchy.

In this synchronous multiplexing method, the multiplexing hierarchy is an integer multiple of the basic signal rate, so auxiliary signals (frame synchronization signals, control signals, etc.) are not inserted in each multiplexing unit, and the control signals necessary during multiplexing are etc. are prepared in advance on the basic signal frame, and multiplexing is performed using this control signal area. This greatly simplifies the configuration of the multiplexing section, which requires high speed (just a P/S
(conversion, S/P conversion), frame synchronization processing, and control processing of the channel switching unit that supports multiplexed channels can be performed at the basic signal speed, so it is necessary to adopt a configuration suitable for high speed. is possible. Note that channel switching here is based on the function of the high-speed multiplexer being simple P/S conversion.
Since only S/P conversion is performed, the channel number during multiplexing and the channel number after demultiplexing do not necessarily match, so it is necessary to take channel correspondence by channel switching, which is why it is provided.

However, such a configuration is not a problem when the service is provided below the basic signal rate, i.e. when it is used as a pipe, but for broadband services where it is necessary to combine and use multiple basic signal frames. Therefore, there is a possibility that a phase difference may occur on the basic signal frame after demultiplexing, and a synchronous multiplexing method that does not cause such a phase difference is desired.

[Conventional technology]

In the conventional synchronous multiplexing method, the multiplexing control signal written on the basic signal frame after demultiplexing is identified, and the channel switching section placed immediately after the demultiplexing latch circuit is selected based on the identification result. I was trying to control it and take action on the channel.

FIG. 5 shows the frame structure of the basic signal.

As shown in the figure, the frame structure consists of a control signal and an information signal (D), and the control signal is a frame synchronization signal (D).
F), a multiplex control signal (ID), a maintenance monitoring signal, etc.

FIG. 6 shows an example of the configuration of a conventional synchronous multiplexing device. On the transmitting side, the multiplexing section includes an identification signal writing section 11 for each channel. 12. −.

1n, each channel CHI, ,CH2+
---Write a specific multiplexing channel number into the multiplexing control signal ID for each basic signal FB of CHn. In the P/S converter 2, the basic signal of each channel in which the multiplex channel number is written is subjected to parallel-to-serial conversion to create a multiplex signal nFB.

The control unit (CONT) 3 controls the operation timing of each unit at this time. The multiplexed signal nFB at the output of the P/S converter 2 is sent to the receiving side via the transmission path 4.

On the receiving side, the demultiplexer converts the input multiplexed signal into S
/P converter 5 performs serial-to-parallel conversion, and sequentially separates the signals into signals SRI, SR2, . Basic signal CHI'
, CH2', -.

produces CHn'. At this point, the multiplexed channel number of the basic signal of each channel does not necessarily correspond to that on the transmitting side.

Frame synchronization, multiplex channel number identification section (FSYNC)
, ID DET) 8 establishes frame synchronization for the basic signal of a specific channel, for example CHn', and identifies its multiplexed channel number. Then, the switch unit 9 is controlled to sequentially change the order of the basic signals of each channel so that the identified multiplexing channel number matches the original multiplexing channel number of that channel. As a result, output signals having channel numbers CH1, CH2, -CHn that correspond to the channel numbers at the time of multiplexing on the transmitting side are obtained.

[Problem that the invention seeks to solve]

The configuration of the synchronous multiplexer shown in FIG. 6 is intended to use the basic signal as a pipe, so when combining multiple basic signal frames, the phase relationship of each channel is Since the phase relationship does not necessarily match the phase relationship before multiplexing, it is necessary to perform phase adjustment between multiple channels.

That is, for example, by combining and using three basic signals with a basic signal speed of 5 Q Mbps, 150 Mbps
When transmitting the s signal, the following cases may occur depending on the network configuration.

1. The three combined basic signals are each transmitted through separate routes, and a frame phase difference occurs between the three basic signals due to the path delay time difference.

2. Even if three basic signals are sent through the same multiplexed transmission path, a frame phase difference may occur between the combined basic signals depending on the demultiplexing method.

Problem 1 above can be solved by controlling the networks so that they pass through the same transmission path. However, regarding problem 2, problems arise with conventional demultiplexing methods.

FIG. 7 shows a time chart of demultiplexing in a conventional synchronous multiplexer. In FIG. 7, the multiplexed input data is the output SRI, S
In R2, . . . , SRn, outputs are sequentially delayed by one bit. The latch section 6 latches and converts the speed according to the fixed timing signal PH1 of the counter 7, and outputs basic signals CHI', CH2', ---, CHn'.
Separate into

Since the channel number arrangement of this basic signal output does not correspond to that on the transmitting side, the multiplexed channel number is identified and the channel is replaced in the switch section 9, and the channel number correspondence is re-established. As shown in Figure 2, there is a possibility that a 1-bit phase difference will occur in each channel output.

Therefore, it is necessary to insert a function that can insert a 1-bit delay into the output of the switch section and perform phase control between the combined channels. Otherwise, for example, if the transmission signal is an image signal, the MSB and LSB in one byte of the output signal may be swapped due to a one-bit difference, but in such a case, the reproduced image will be completely meaningless. There was a problem that it became.

[Means for solving problems,]

The present invention is an attempt to solve the problems of the prior art, and as shown in the basic structure of FIG. , a demultiplexing device using a synchronous multiplexing method that multiplexes a synchronized basic signal at a signal speed that is an integral multiple of the speed thereof, comprising a serial-to-parallel conversion means 11, a control latch means 12, a control signal identification means 14, , timing control means 15, and demultiplexing/demultiplexing latch means 16.

The serial/parallel converter 11 converts the input multiplexed signal into serial/parallel converters to generate parallel signal outputs of the number of multiplexed channels having sequentially different timings.

The control latch means 12 latches the signal of a specific channel in the output of the serial/parallel converter 11 at a fixed timing.

The control signal identification means 14 identifies the multiplexed channel number of the signal of the specific channel latched by the control latch means 12, and detects the difference from the number of the multiplexed channel to which the control latch means 12 is connected. do.

The timing control means 15 generates a timing signal having a timing difference corresponding to the above-mentioned difference in multiplexed channel numbers with respect to the latch timing in the control latch means 12.

The demultiplex/latch means 16 latches the output of the serial/parallel converter 11 in accordance with the timing signal of the timing control means 15, thereby generating basic signal outputs corresponding to the number of multiplexed channels.

[For production]

In the demultiplexing method of the present invention, the control latch means connects the control latch means by identifying the channel number on the basic signal frame of the particular channel by the output obtained by latching the specific channel at a fixed timing. By comparing the specified channel number with the specified channel number and controlling the demultiplexing latch circuit according to the difference, the channel number at the time of multiplexing corresponds to the channel number after demultiplexing.

〔Example〕

FIG. 2 shows an embodiment of the present invention, illustrating the configuration of a demultiplexing section. In the figure, 21 is a shift 5 register;
22 is a control latch section, 23 is a counter circuit, 24 is a frame synchronization and multiplexing channel number identification section, 25 is a timing control section, and 26 is a demultiplexing latch section.

Further, FIG. 3 shows a time chart of demultiplexing in the embodiment of FIG. 2.

The multiplexed input data is read into the shift register 21 in accordance with the clock, and outputs SRI, SR2, -, SRn sequentially shifted by one bit are generated in parallel. The control latch unit 22 outputs the output of a specific channel, for example, SRn,
The clock is latched in accordance with the fixed timing signal PH1 of the counter circuit 23 that counts the clock, and an output is generated. The frame synchronization and multiplexing channel number identifying section 24 performs frame synchronization on the output of the control latch section 22 and identifies the multiplexing channel number.

If the identification result is a multiplexed channel number, it is shifted by -n bits from the multiplexed channel number n on the transmitting side, so the timing control unit 25 shifts -n bits from the write clock in the shift register 21. A shifted demultiplexing timing signal PHC is generated and applied to the demultiplexing latch section 26. The demultiplexing latch unit 26 latches the output of the shift register 21 at this timing and converts the speed, thereby output basic signals CH1, CH2, −・.

Produces CHn.

FIG. 4 shows an example of the configuration of the timing control section 25, in which the decoder 25. decodes the counter value from the counter circuit 23, and the selector 252 determines the demultiplexing timing by selecting the output of the decoder 251 according to the frame synchronization and multiplexing channel number identified in the multiplexing channel number identifying section 24. Generates signal PHC.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to always correctly demultiplex the output basic signal without a phase shift from the basic signal of each channel multiplexed on the transmitting side. Even for broadband services that are used in combination, demultiplexing can be performed stably, and the device configuration in this case is simple and can be downsized.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of principle 9 of the present invention, Fig. 2 is a diagram showing the configuration of the synchronization separation section of an embodiment of the invention, and Fig. 3 is a diagram showing the demultiplexing time in the embodiment of Fig. 2. 4 is a diagram showing a configuration example of a timing control section; FIG. 5 is a diagram illustrating a frame configuration of a basic signal; FIG. 6 is a diagram illustrating a configuration example of a conventional synchronous multiplexing device; FIG. 7 is a diagram showing a time chart of synchronous separation in a conventional synchronous multiplexing device. 21-Shift register 22-Control latch section 23--Counter circuit 24--Frame synchronization, multiplexed channel number identification section 25--Timing control section 25,--Decoder 252--Selector 26---Demultiplexing latch part

Claims (1)

[Claims] Demultiplexing using a synchronous multiplexing method that has a control signal including a multiplexing channel number on a basic signal frame and multiplexes the synchronized basic signal at a signal speed that is an integral multiple of the basic signal speed. In the apparatus, a serial-to-parallel conversion means (
11), a control latch means (12) for latching a signal of a specific channel of the serial-to-parallel converter (11) at a fixed timing, and identifying a multiplexed channel number in the output of the control latch means (12). control signal identification means (14) for detecting the difference between the number of the multiplexed channel to which the control latch means (12) is connected;
a timing control means (15) for generating a timing signal having a timing difference corresponding to the difference between the fixed timing of 2) and the multiplexed channel number; 11) A synchronous multiplexing system comprising: demultiplexing/latch means (16) for latching the output of 11) and generating basic signal outputs for the number of multiplexed channels.