JPH06252870A - Data multiplexing transmission system - Google Patents

Abstract

PURPOSE:To obtain a data multiplexing transmission system by which a transmission line is effectively utilized and realized without complicated circuit configuration even when a data speed is other than a multiple of 1/N of 48kbps. CONSTITUTION:Data signals from plural data terminal equipments are stored respectively in FIFO memories 12, 18, in which speed conversion is executed and data for the plural data terminal equipments are collected and a resulting DSOB signal is sent. The system is provided with a frame generating circuit 14 controlling read and distribution of plural data from the FIFO memories 12, 18, a read timing circuit 13, a frame detection circuit 16 and a distribution circuit 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data multiplex transmission system, and more particularly to a data multiplex transmission system in which an interface multiplex system between a data terminal device and a PCM multiplex communication device is improved.

[0002]

2. Description of the Related Art Generally, a plurality of data terminal devices are input,
For example, when data is multiplexed by a 24-channel PCM multiplexing communication device, each frame is inserted at the time slot TS1 to TS24 for 24 channels and the end of each frame as shown in the signal format of FIG. It is composed of frame synchronization bits (not shown) and is multiplexed. Each time slot has an 8-bit structure, and is composed of a head frame bit F, a 6-bit data bit D inserted by speed conversion of terminal data, and a control bit C at the end. Normally, the signal of one channel corresponding to the 0th-order group of the multiplexing hierarchy (hierarchy) is 64
It is kbps, and the speed is converted to 1.544 Mbps when the hierarchy is increased to 24 channels.

Conventionally, an interface for converting a data signal of this type of data terminal device into a 0th order data signal of a PCM multiplexer will be described. As described above, in the PCM multiplex communication device, information is transmitted and received with an 8-bit signal (64 kbps) per one time slot, but when transmitting a data signal, 2 bits out of 8 bits are a frame bit and a control bit. Since the control bits of the bits are allocated and the remaining 6 bits are allocated to the data bits, data of 64 kbps × 6/8 bits = 48 kbps can be transmitted. For example, when a data signal from a data terminal device is multiplexed with a signal of 9.6 kbps, data is sent at a rate of 48 kbps / 9.6 kbps = 5, that is, once every 5 times (5 frames),
The other four times I'm doing byte stuffing. It is also necessary to send information on whether the byte sent the data or the byte stuffing. It should be noted that frame bits are used for each frame to form a frame and hold the synchronization state to send information.

Now, the data signal from the data terminal device is 1
9.2 kbps and 48 kbps / 19.2 kbp
A case where a fractional number occurs in the number of frames such as s = 2.5 will be described. In this case, as shown in FIG. 4, the data is sent once every 2.5 times, the remaining one time is byte stuffing, and the remaining 0.5 time is stuffing bit by bit. It will be a shift-like repetition such as performing. To realize this, the circuit becomes very complicated. Further, even in the case of 9.6 kbps, it becomes difficult to send information as to whether the data is stuffed only by the frame bit, and the data bit is used, so that the circuit becomes complicated here.

[0005]

In this conventional data multiplex transmission system, when a plurality of data signals are multiplexed in the 0th order hierarchy, the data signal from the data terminal device is 9.
In the case of 6 kbps, the information frame is 1/5, and in the case of 19.2 kbps, the information frame is 2.5.
It has the drawback of using only one-third. In particular, when the data signal is not 1 / N times 48 kbps (N = integer) like the case where the data signal is 19.2 kbps, there is a drawback that the circuit becomes very complicated due to the stuffing.

[0006]

The data multiplex transmission system of the present invention is a data multiplex transmission system having an interface circuit for transmitting a data signal from a data terminal device using a PCM multiplex communication device. , When converting a data signal from the data terminal device into a zero-order group signal DSO (64 kbps) which is the minimum basic unit of PCM multiplex communication, the data signals from several data terminal devices are combined into one. It is characterized in that it is a DSOB signal.

[0007]

According to the present invention, the data signal from the data terminal device is transmitted to the P
The minimum basic unit of CM multiplexed communication is DSO (64 kb
ps), the data signals from several data terminal devices are combined into one DSOB signal. Further, two or more time slots are assigned to one channel, and these two features can be realized.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 shows a signal format according to an embodiment of the present invention, and FIG.
FIG. 3 is an interface circuit configuration diagram for realizing the signal format of this embodiment. The signals handled in this embodiment show the case where the input / output signal from the data terminal device is 19.2 kbps and is converted into a 0th-order group multiplexed signal.

Next, the operation of this embodiment will be described. As shown in FIG. 1, when two time slots of each frame are assigned to one channel, data of (64 kbps × 6/8 bits) × 2 = 96 kbps (1) can be transmitted. Therefore, if the method of allocating these two time slots to one channel is used, 19.2 kbps × 5 = 96 kbps ... (2) As shown in equations (1) and (2), 19.2 kbps 5
Since the data from the individual data terminal devices a, b, c, d, and e are received by the PCM communication device, it is possible to convert the data into a 64 kbps signal and to carry the signal.

The operation of this embodiment will be described below with reference to FIG. The operation on the transmitting side will be described. The data terminal output signal 21 output from the data terminal device is converted to a logic level by the line driver / receiver 11 and then sent to the transmission side FIFO memory 12. Sending FI
The data stored in the FO memory 12 is read by the timing signal 23 generated by the read timing circuit 13. In this embodiment, five sets of the above line driver / receiver and the transmission side FIFO memory are provided, each of which is controlled by the timing signal 23 and read. This timing signal sequentially reads data from the five transmitting FIFO memories 12. The frame generation circuit 14 also generates a frame signal 24 in phase with the timing signal 23. The frame signal 24 is used by the receiving circuit to recognize which data terminal a, b, c, d, or e is the data terminal. The channel interface circuit 15 adds the frame signal 24 to the data read from the five FIFO memories and sends it as transmission data 25 to the multiplexing circuit.

Next, the operation on the receiving side will be described. The channel interface circuit 15 receives the reception data 27 separated by the channel from the multiplexing circuit, and the distribution circuit 1
Type in 7. The distribution circuit 17 distributes the respective data of a, b, c, d, and e to the five reception side FIFO memories 18, and the information on where to distribute the data is determined by the frame detection circuit 1.
6 can detect. The data stored in the five FIFO memories are continuously read by the clock of the data terminal device, level-converted by each line driver / receiver 11, and the data terminal input signal 22
Is sent as.

In this embodiment, the data signal is 48 kbps 1
Although an example in which the data rate is 19.2 kpbs has been described as an example in the case of not becoming / N times (N = integer), it can be similarly applied to the case of data of 38.4 kpbs. Also, the data rates are 2.4 kpbs and 4.8 kpb.
s, 9.6 kpbs, etc., 1 / N of 48 kpbs
Although it can be applied to the case of double (N = integer), the frame structure in this case is a structure in which one channel is allocated to one time slot.

[0013]

As described above, according to the present invention, since the data signals from several data terminal devices are put together into one 0th-order group channel signal, the transmission line can be used efficiently. Furthermore, when the data signal from the data terminal device does not become 1 / N times 48 kbps (N = integer), two or more time slots are assigned to one channel, so that the transmission path can be used more efficiently. You can Further, even when the data signal from the data terminal device is not 1 / N times 48 kbps (N = integer), the circuit scale is not increased.

[Brief description of drawings]

FIG. 1 is a signal format showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an embodiment of the present invention.

FIG. 3 is an explanatory diagram of signals during data transmission of a general PCM multiplex communication device.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 11 line driver / receiver 12 transmission side FIFO memory 13 read timing circuit 14 frame generation circuit 15 channel interface circuit 16 frame detection circuit 17 distribution circuit 18 reception side FIFO memory 21 data terminal output signal 22 data terminal input signal 23 timing signal 24 frames Signal 25 Transmission data 26 Clock signal 27 Reception data

Claims (3)

[Claims] 1. A data signal from a data terminal device is sent to a PC.
A data multiplex transmission method having an interface circuit for transmission using an M multiplex communication device, wherein a data signal from the data terminal device is a zero-order group signal DSO which is the minimum basic unit of PCM multiplex communication. (64 kbps)
A data multiplexing transmission method characterized in that, when converted into, the data signals from several data terminal devices are combined into one DSOB signal. 2. The data multiplexing transmission system according to claim 1, wherein two or more time slots in each frame of the PCM multiplexing communication device are assigned to one channel. 3. A transmission / reception FIFO memory in which the interface circuit performs data rate conversion, and a transmission FI.
A read timing circuit that controls the timing of reading data from the FO memory, and a frame that generates a frame signal that is used as information for identifying which terminal of several data terminal devices is used by the receiving circuit. A generation circuit, a frame detection circuit that receives a frame signal, detects which terminal the data is, and supplies the information to a distribution circuit, and performs level conversion between the signal of the data terminal device and the signal of the PCM multiplexing communication device. A line driver / receiver, a distribution circuit that allocates data to each data terminal device, and a channel that adds a frame signal to the data signal read from the transmission FIFO memory and inputs the received data to the frame detection circuit and the distribution circuit. The data multiplex transmission system according to claim 1, further comprising an interface circuit.