KR100295811B1 - Data frame converting circuit from E4 data to C4 data in AU4 data frame - Google Patents

Abstract

An object of the present invention is to provide a data transmission system by minimizing the amount of jitter generated in converting E4 data to C4 data in a North American European optical transmission system using the E4 interface and the AU4 interface as the basis for data transmission. An object of the present invention is to provide a circuit for converting E4 data into C4 data of an AU4 frame, which can prevent errors and thereby improve the quality of communication services.

According to an aspect of the present invention, there is provided a circuit for converting E4 data of an optical transmission system to C4 data of an AU4 frame, comprising: a frame counter 100 that receives a 19 Mbps clock signal and generates and outputs a signal for a C4 data frame position; A data converter 200 which receives E4 data according to a 17 Mbps clock signal and generates and outputs data driven according to a 19 Mbps clock signal within a range where underflow does not occur using a first-in first-out buffer; And a data arranging unit 300 which receives the data output from the data converter 200 and arranges and outputs the data in the form of C4 data according to the frame position signal output from the frame counter 100.

Description

Data frame converting circuit from E4 data to C4 data in AU4 data frame}

In the present invention, this 4 (E4, hereinafter referred to as 'E4') data (data) AY 4 (AU4, hereinafter referred to as 'AU4') Seed 4 (C4, 'C4') of the frame (frame) In more detail, in a North American European optical transmission system based on the E4 interface and the AU4 interface as data transmission, the jitter is minimized while minimizing the size of jitter. A circuit for converting E4 data into C4 data.

In general, optical transmission systems used in North America and Europe are used for transmitting data between each exchange and repeater, or for transmitting data from each exchange and repeater to a subscriber network.

The data processed by the transmitter is classified into E4 data and C4 data according to its characteristics. The C4 data has a transmission rate of 155.84 megabits (Mega bps), Mbps, and data of AU4 frame. It is part of the structure.

As shown in FIG. 1, the data structure of the AU4 frame has a V4 including the C4 data D10 and Pass OverHead (POH, hereinafter referred to as 'POH', D20) containing actual information. (VC4, hereinafter referred to as 'VC4') data and a pointer (pointer, POH, D30).

The C4 data is composed of nine subframes, and the structure of each subframe is as shown in FIG. 2, and the portion excluding the POH is one subframe of the C4 data.

That is, in FIG. 2, the portion denoted '96I' is 96 data bits I containing actual information, the portion denoted 'W' is eight information data bits I, and the portion denoted 'Y' is non- Eight fixed stuff bits (R) that are information.

The part labeled 'X' is composed of one adjustment control bit (C, hereinafter referred to as 'C bit'), five fixed element bits (R), and two overhead bits (O). The part marked 'Z' includes six data (I) bits, one justification opportunity bit (S, hereinafter referred to as 'S bit') and one fixed element bit (R), which are actual information. Is made of.

As can be seen in Figure 2, the C4 data consists of the parts containing the actual information (I) and other parts necessary for communication, and transmitted between the respective transmission devices in the form of the C4 data, but each In the step of transmitting to the subscriber network, the data is converted into E4 data by the data conversion circuit and transmitted.

On the contrary, when transmitted from each subscriber network to each transmitter and repeater, the data conversion circuit converts E4 data into C4 data and transmits the data.

Meanwhile, the E4 data has a frame structure as shown in FIG. 3, and all of the E4 data correspond to pure information of the C4 frame structure.

Unlike the C4 data, the E4 data contains only pure information, and is transmitted at a transmission rate of 139.264 Mbps by a clock of 17 Mbps.

However, the C4 data is data transmitted at a transmission rate of 155.84 Mbps by a clock of 19 Mbps, and as described above, various non-information parts are included in addition to the pure information, and the transmission speed of only the pure information part is In calculation, since there are 20 96 I bits in one subframe, one 'W' of 8 bits, and six I bits in 'Z', the following equation is calculated.

Information data in one subframe = 96 × 20 + 8 + 6 = 1,934

By the way, since one frame of C4 data consists of nine subframes, the information data in one frame becomes 17,406 bits.

Since each bit is transmitted at a rate of 8 Kbps, the transmission rate of one frame is calculated as shown in Equation 2 below, resulting in 139.248 Mbps.

Transmission rate of one frame information data = 17,406 × 8,000 = 139,248,000 bps

As described above, when E4 data is converted to the C4 data format, E4 data is input at a transmission rate of 139.264 Mbps, and C4 data is output at a transmission rate of 139.248 Mbps, so C4 data is higher than E4 data. 16,000bps is lacking.

On the other hand, there is an S bit in the portion indicated by the 'Z' in the frame structure of the C4 data, the S bit is an optional bit that may or may not contain information in some cases.

Therefore, 16,000 bits, which is the difference between the E4 data and the C4 data, can be solved by appropriately using the S bits.

That is, there are nine S bits in the frame, one for each subframe, of which two S bits contain information and the remaining seven S bits do not contain information. The number of C4 data can be the same.

As described above, when converting E4 data containing pure information into C4 data, a first-in-first-out (FIFO) type buffer is used. The difference between the rate at which data is written to the buffer and the rate at which C4 data is read from the buffer according to a clock of 19 Mbps is shown. Thus, there is an underflow that performs an operation of reading data even though no data is written to the buffer. There is a problem that overflow occurs, the opposite phenomenon occurs, and jitter occurs.

If a jitter phenomenon occurs due to the above causes, an error in data transmission may occur, thereby degrading the quality of the overall communication service.

Accordingly, an object of the present invention is to solve the above problems of the prior art, and in the North American European optical transmission system using the E4 interface and the AU4 interface as a basis for data transmission, the E4 data is converted into C4 data. By minimizing the amount of jitter incurred, it is possible to provide a circuit for converting E4 data into C4 data in an AU4 frame, which can prevent data transmission errors and thereby improve the quality of communication services.

1 is a block diagram showing a data structure of an AU4 frame;

FIG. 2 is a block diagram illustrating a subframe structure of one of C4 data in FIG. 1;

3 is a block diagram showing an E4 data frame structure;

4 is a block diagram to which a circuit for converting E4 data into C4 data of an AU4 frame according to an embodiment of the present invention is applied;

FIG. 5 is a block diagram to which the data converter of FIG. 4 is applied;

6 is a block diagram to which a data arranging unit is applied in FIG. 4;

7 is a block diagram in which the present conversion circuit is applied to four channels.

Explanation of symbols on the main parts of the drawings

100: frame counter 200: data converter

210: input control unit 220: input buffer

230: output control unit 240: output buffer

300: data placement unit 310: subframe arrangement unit

320: alignment control unit 330: parallel signal generation unit

340: selection bit control unit 350: alignment unit

360: clock control unit

The configuration of the present invention for achieving the above object is made as follows.

In a circuit for converting E4 data of an optical transmission system into C4 data of an AU4 frame,

A frame counter which receives a 19 Mbps clock signal and generates and outputs a signal for a C4 data frame position;

Data conversion means for receiving E4 data according to a 17 Mbps clock signal and generating and outputting data driven according to a 19 Mbps clock signal using a first-in first-out buffer;

And data arrangement means for receiving data output from the data conversion means and arranging and outputting the data in the form of C4 data according to a frame position signal output from the frame counter.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

As shown in Figs. 4 to 6, a circuit for converting E4 data into C4 data of an AU4 frame according to an embodiment of the present invention is configured as follows.

In a circuit for converting E4 data of an optical transmission system into C4 data of an AU4 frame,

A frame counter 100 which receives a 19 Mbps clock signal and generates and outputs a subframe number signal CNT9 and a subframe section signal CNT270 for a C4 data frame position;

A data converter 200 which receives E4 data according to a 17 Mbps clock signal and generates and outputs data driven according to a 19 Mbps clock signal within a range where underflow does not occur using a first-in first-out buffer;

And a data arranging unit 300 which receives the data output from the data converter 200 and arranges and outputs the data in the form of C4 data according to the frame position signal output from the frame counter 100.

As shown in FIG. 5, the configuration of the data converter 200 is

An input control unit 210 for generating and outputting an E4 data write control signal WE according to a 17 Mbps clock signal;

An input buffer 220 which operates according to the recording control signal WE output from the input control unit 210 and sequentially records and outputs E4 data;

An output control unit 230 operating according to a 19 Mbps clock signal to generate and output a read control signal RE by comparing the write address ADDWR and the read address ADDR;

An output which operates according to the read control signal RE output from the output control unit 230 and outputs the corresponding data to the data placing unit 300 according to a clock signal of 19 Mbps and outputs a buffer level control signal WREN Buffer 240 is included.

As shown in FIG. 6, the configuration of the data arranging unit 300 is

Subframe array unit 310 for receiving the sub-frame section signal (CNT270) indicating the size of the sub-frame output from the frame counter 100 to generate and output the C4 enable signal (C4EN) according to the position of the C4 data )Wow,

An alignment control unit 320 for generating and outputting an alignment control signal ADDCNT by operating according to the C4 enable signal C4EN and the S-bit processing signal SELSB output from the subframe array unit 310;

After receiving the alignment control signal ADDCNT and the buffer level signal BUFLV output from the alignment control unit 320, it is determined whether to process the S bits as data or non-data in the surf frame, and accordingly S A selection bit control unit 340 for generating a bit processing signal SSELB and outputting the generated bit processing signal to the alignment control unit 320;

A parallel signal generator 330 which receives the buffer level control signal WREN outputted from the data converter 200 and data having a transmission rate of 19 Mbps and generates and outputs a 256-bit parallel signal;

By receiving the 256-bit parallel signal output from the parallel signal generator 330 is aligned in the correct position in the payload (C4) data according to the alignment control signal (ADDCNT) output from the alignment control unit 320 An alignment unit 350 for outputting,

The second bit of the first clock reference signal CLKCT1, which is the second bit of the energetic control signal ADDCNT, output from the alignment control unit 320, and the second bit of the buffer level signal BUFLV, which is output from the parallel signal generation unit 330. And a clock control unit 360 for receiving the second clock reference signal CLKCT2 and generating and outputting a phase locked loop control signal.

Operation of the embodiment of the present invention made as described above is as follows.

First, the main operation of the present invention will be described. As shown in FIG. 4, the frame counter 100 receives a clock signal CK19M of 19 Mbps as a 2430 counter and receives the subframe number signal CNT9 for the C4 data frame position. By generating the sub-frame section signal CNT270, a signal indicating the size and position of the entire C4 data frame is output.

The data converter 200 receives the E4 data DAT17M according to the 17 Mbps clock signal CK17M, and uses a first-in-first-out buffer to provide a 19 Mbps clock signal CK19M within a range in which no underflow occurs. Generates and outputs data driven by

In addition, the data arranging unit 300 receives the data DAT19M output from the data converting unit 200 and outputs C4 data according to various frame position signals CNT9 and CNT270 output from the frame counter 100. Output in a form arranged.

Hereinafter, an operation of the data converter 200 will be described in detail with reference to FIG. 5.

The input controller 210 of the data converter 200 generates and outputs an E4 data write control signal WE according to a 17 Mbps clock signal CK17M, and the input buffer 220 is output from the input controller 210. The E4 data is sequentially recorded and output according to the recording control signal WE.

That is, the input controller 210 outputs a write control signal for each flip-flop so that only one flip-flop is sequentially driven among the eight flip-flops in the input buffer 220 by using a 17M counter. The flop flops are not driven.

In addition, the input buffer 220 drives the corresponding flip-flop according to the 8-bit recording control signal output from the input control unit 210 and receives and outputs 8 bits of E4 data input at a transmission rate of 17 Mbps.

The input controller 210 outputs a write address ADDWR indicating the address of the flip-flop in which the input buffer 220 is being input. The output controller 230 receives the signal and outputs the signal from the output buffer 240. The output read address ADDR is received, the two values are compared, and the read control signal RE is generated so that the value is within a certain range without underflow or overflow. The read control signal RE is output according to a clock signal of 19Mbps. .

That is, the output controller 230 outputs the read control signal RE to operate the output buffer 240 only when the difference between the write address ADDWR and the read address ADDR is 4 or more. Let the output go low once.

The output buffer 240 operates according to the output control signal RE output from the output control unit 230 to adjust the data output from the input buffer 220 according to a 19 Mbps clock signal. ), But the period of the output data is not constant.

By doing the above, the data converter 200 converts the E4 data (DAT17M) input at the transmission speed of 17 Mbps to the transmission speed of 19 Mbps, and outputs the data. The overflow occurs during data conversion by the operation of the output controller 230. Or underflow can be prevented.

Hereinafter, an operation of the data placement unit 300 will be described in detail with reference to FIG. 6.

The subframe arranging unit 310 of the data arranging unit 300 receives an interval signal CNT270 for each subframe indicating the size of the subframe output from the frame counter 100 and indicates the exact position of the C4 data therein. Generate and output the C4 enable signal C4EN.

The alignment control unit 320 operates according to the C4 enable signal C4EN output from the subframe arrangement unit 310 and the S-bit processing signal SELSB output from the selection bit control unit 340. Generate and output an alignment control signal ADDCNT that controls the operation of the < RTI ID = 0.0 >

On the other hand, the selection bit control unit 340 receives the alignment control signal ADDCNT output from the alignment control unit 320 and the buffer level signal BUFLV output from the parallel signal generation unit 330 to receive S bits in the surf frame. It is determined whether to process data or non-data, and generate an S bit processing signal SSELB according to the data and output the same to the alignment controller 320.

In addition, the parallel signal generator 330 receives the buffer level control signal WREN output from the data converter 200 and data having a transmission rate of 19 Mbps, generates and outputs a 256-bit parallel signal. A buffer level signal BUFLV is generated and output to the selection bit controller 340 and the clock controller 360.

The alignment unit 350 receives the 256-bit parallel signal output from the parallel signal generation unit 330 and precisely positions the payload of C4 data according to the alignment control signal ADDCNT output from the alignment control unit 320. Output to sort by.

The sorting unit 350 is designed to increase by 8 when data is input. When Z data is input, 7 increases when S bits are used as data, and 6 when S bits are non-data. Let this increase.

By doing the above, the E4 data can be accurately converted to the C4 data format in the AU4 frame, and the S bit of the Z data can also be properly processed, so that the number of the E4 data and the C4 data can be matched. By properly adjusting, the jitter phenomenon can be minimized.

On the other hand, the clock control unit 360 is the buffer level output from the first clock reference signal (CLKCT1) and the parallel signal generator 330, which is the second bit of the energetic control signal (ADDCNT) output from the alignment control unit 320 The second clock reference signal CLKCT2, which is the second bit of the signal BUFLV, is input to generate and output a phase locked loop control signal VCO19PLL.

By doing the above, the phase synchronization can be appropriately performed at the place of receiving the data output from the present converter.

On the other hand, if configured as shown in Figure 7, the data conversion circuit as described above can process four channels at once.

That is, each data conversion circuit 1000, 2000, 3000, 4000 for each channel receives the E4 data (DAT17M1, DAT17M2, DAT17M3, DAT17M4) according to the clock signals CK17M1, CK17M2, CK17M3, and CK17M4. In addition, each C4 data (DATOUT1, DATOUT2, DATOUT3, DATOUT4) is output in accordance with a clock signal having a single 19Mbps transmission rate. Thus, class 622 data transmission can be performed.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, conversions, and modifications are possible within the scope without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.

Accordingly, the present invention operates as described above in the North American European optical transmission system using the E4 interface and the AU4 interface as a basis for data transmission, by minimizing the amount of jitter generated when converting the E4 data to C4 data. Therefore, there is an effect that it is possible to prevent an error of data transmission and thereby improve the quality of communication service.

In addition, the E4 channel can be accommodated at the same time, thereby minimizing the size of the system and utilizing the free space, thereby inducing a drop in the product production price.

Claims (5)

In a circuit for converting E4 data of an optical transmission system into C4 data of an AU4 frame, A frame counter which receives a 19 Mbps clock signal and generates and outputs a signal for a C4 data frame position; Data conversion means for receiving E4 data according to a 17 Mbps clock signal and generating and outputting data driven according to a 19 Mbps clock signal using a first-in first-out buffer; And data arrangement means for receiving the data output from the data conversion means and arranging and outputting the data in the form of C4 data according to the frame position signal output from the frame counter. Circuit to convert seed 4 data of a frame. The method of claim 1, wherein the data conversion means, Input control means for generating and outputting an E4 data recording control signal in accordance with a clock signal of 17 Mbps; An input buffer for sequentially recording and outputting E4 data by operating in accordance with a recording control signal output from the input control means; Output control means for operating according to a clock signal of 19 Mbps to generate and output a read control signal by comparing a write address with a read address; And an output buffer operating according to a read control signal output from the output control means to output corresponding data to the data placement means in accordance with a clock signal of 19 Mbps and output a buffer level control signal. A circuit that converts data into seed 4 data in an A4 frame. The method of claim 2, wherein the output control means, A circuit for converting the 4 data into the seed 4 data of an A4 frame, characterized by driving the read control signal to a high signal only when the difference between the write address and the read address is 4 or more. The method of claim 1, wherein the data arrangement means, Subframe arrangement means for receiving an interval signal for each subframe indicating the size of the subframe output from the frame counter and generating and outputting a C4 enable signal according to the position of the C4 data; Alignment control means for generating and outputting an alignment control signal by operating according to the C4 enable signal and the S-bit processing signal outputted from the subframe arrangement means The alignment control signal and the buffer level signal outputted from the alignment control unit are input to determine whether to process the S bit as data or non-data in the subframe, and generate the S bit processing signal accordingly. Selection bit control means for outputting to the control means, Parallel signal generation means for receiving the buffer level control signal output from the data conversion means and data having a transmission rate of 19 Mbps and generating a 256-bit parallel signal and outputting the same; And an alignment means for receiving the 256-bit parallel signal output from the parallel signal generating means and aligning the same at a precise position in the payload of the C4 data according to the alignment control signal output from the alignment control means. The circuit converts the 4 data into seed 4 data of the A4 frame. The method of claim 4, wherein the data arrangement means, Generates a phase locked loop control signal by receiving a first clock reference signal, which is the second bit of the energetic control signal output from the alignment control means, and a second clock reference signal, which is the second bit of the buffer level signal output from the parallel signal generating means. And a clock control means for outputting the same. The circuit for converting the 4 data into the seed 4 data of the A4 frame.