KR20000026042A - Circuit for multiplexing/inverse multiplexing data using fifo memories in high-bit-rate digital subscriber line device - Google Patents

Abstract

PURPOSE: A circuit for multiplexing/inverse multiplexing data is provided to use FIFO(First In First Out) memories, which is possessed in an HDSL(High-bit-rate Digital Subscriber Line) device for stable data transmission. CONSTITUTION: A circuit for multiplexing/inverse multiplexing data comprises: an E1 mapping clock generator(300) for generating a clock to map E1 data; FIFO(First-In First-Out) memories(215) for storing the E1 data in a first, a second memory according to time slots in turn, by a write clock; an HDSL(High-bit-rate Digital Subscriber Line) frame controller(400) for making basic HDSL frames by receiving a signal generated from the E1 mapping clock generator(300), for adjusting synchronization between a data terminal and lines, and for supplying a clock to read the data from the FIFO memories(215); a FIFO data input/output confirmer(500) for latching data recorded in the FIFO memories(215) by the control clock, for comparing two values, and for resetting the FIFO memories(215), if the two values are not the same; and an HDSL framer mapper(600) for transmitting E1/2 data outputted from the first, the second memory of the FIFO memories(215) to the lines, by mapping the E1/2 data in the frames made in an HDSL frame(420).

Description

A data multiplexing / demultiplexing circuit using a line input line output memory provided in a high speed data transmission device.

The present invention relates to a data multiplexing / demultiplexing circuit using a line input line output (FIFO) memory provided in a high speed data transmission device (HDSL). In detail, the present invention relates to two data in real time using a serial FIFO memory. Data using a line input line output (FIFO) memory provided in a high speed data transmission device (HDSL) which is suitable for demultiplexing into signals and transmitting to two pairs of lines or multiplexing two high speed data received from two pairs of lines. The present invention relates to a multiplexing / demultiplexing circuit.

High-bit-rate Digital Subscriber Line (HDSL) is a device that transmits DS1 (1,544Mbps) or DS1E (2,048Mbps) level data without a separate relay device by using existing telephone subscriber line.

1 is a block diagram of a conventional high speed data transmission apparatus. As shown, the configuration of the transmitting end block 110 for transmitting data and the receiving end block 120 are almost the same. Looking at the structure of the transmitting end block, the line interface IC 111 which functions to code / decode or clock the data of DS1 (T1) / DS1E (E1) and the framer IC which examines the frame of the data of DS1 / DS1E class 112, a V.35 driver / receiver IC 113 for converting V.35 data into a transmit / receive signal, and transfer the selected data to one of DS1 / DS1E and V.35 data, and convert the data into a DSP IC 115; PGA ICs 114 and 116 which are sent to or received from the DSP IC 115, the DSP IC 115 which multiplexes one data into two signals or two signals into one data, and the DSP IC ROM 118 storing data for driving 115, and transceiver IC 117 having a function of modulating or demodulating two signals.

In operation, when a DS1 / DS1E or V.35 data is sent from a data terminal (DTE), the PGA IC is transmitted through the line interface IC 111 and the framer IC 112 in the case of the DS1 / DS1E class. 114 is received via the V.35 driver / receiver IC 113 in the case of V.35.

The received data causes the PGA IC 114 to generate signals necessary for data transmission according to the desired interface DS1 / DS1E, V.35, and some signals are sent to the DSP IC 115.

The DSP IC 115 downloads the information in the ROM 118 when power is supplied to an integrated circuit having a process function. The DSP IC 115 stores the data sent from the PGA IC 114 in a 16-bit unit in an internal buffer and demultiplexes the data into two signals having a frame structure, and then converts the two data by 8 bits into the PGA IC ( 116). The PGA IC 116 functions to make an HDSL frame structure, and the signal is modulated by the transceiver IC 117 and divided into two pairs of lines.

In case of reception, it is the opposite of transmission. That is, the two signals demodulated by the transceiver IC 127 are separated from the additional information except for the data by the PGA IC 126, and the data is sent to the DSP IC 125. The DSP IC 125 multiplexes two data and converts the data into one data, and the data is sent to the PGA IC 124.

The PGA IC 124 receives data according to a desired interface. When using the V.35 interface, the data rate is a multiple of 64 Kbps (N x 64 Kbps). N values range from 1 to 32, but only a few frequently used values are implemented.

However, the conventional technique of multiplexing and demultiplexing data using the DSP IC 105 does not perform real-time processing for data after being stored in an internal buffer, and an N value is odd in a V.35 interface using Nx64 Kbps. In that case it is difficult to implement. If the data of the ROM 108 is not properly downloaded, data transmission and reception are impossible.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above. The present invention can process high-speed data in real time by a write clock and a read clock, and is operated by a circuit designed without an external driving circuit such as a ROM. You can. In addition, when interworking with a data terminal device (DTE) having a transmission rate of Nx64 Kbps, even if the N value is an odd number, there is no malfunction such as a clock glitches. It is an object of the present invention to provide a data multiplexing / demultiplexing circuit using a FIFO) memory.

A feature of the present invention for achieving the above object is a high-speed data transmission device (HDSL: High-bit-rate Digital) for transmitting DS1 (1.544 Mbps) or DS1E (2.048 Mbps) data at high speed using a telephone subscriber line. In a data multiplexing / demultiplexing circuit of a high speed data transmission device (HDSL) configured to demultiplex into two signals in a subscriber line and transmit on two pairs of lines or multiplex two high-speed data received on two pairs of lines. An E1 mapping clock generator which receives the E1 signal input from an external data terminal device (DTE) and generates a clock for mapping E1 DATA; A pre-input line output (F) divided into a first memory unit and a second memory unit to alternately receive and store time slots based on a write clock generated from the generator. IFO) memory unit, and receives the signal generated from the E1 mapping clock generator to create a basic HDSL frame, and when the clock phase difference between the data terminal (DTE) and the line is synchronized and read data from the FIFO memory An HDSL frame control unit providing a clock and data written to the FIFO memory based on a write clock generated from the E1 mapping clock generator, and data output from the FIFO memory based on a control clock of the HDSL frame control unit. Read and latch the two values to compare the two values with each other, and reset the FIFO memory area if the two values are different; and if the FIFO data input / output based on the FIFO data input / output check unit is normal, remove the FIFO memory. E1 / 2 D respectively output from the 1st memory part and the 2nd memory part It is configured to include an HDSL framer mapper for mapping the ATA to the frame made by the HDSL framer to be transmitted to the line.

1 is a block diagram of a high speed data transmission device (HDSL) equipped with a conventional DSP chip and ROM to perform high speed data multiplexing and demultiplexing.

2 is a block diagram of a high speed data transfer device (HDSL) for performing multiplexing and demultiplexing of high-speed data using a line input line output (FIFO) memory according to an embodiment of the present invention;

3 and 4 are clock diagrams relating to a line input line output (FIFO) memory according to the present invention;

FIG. 5 is a detailed block diagram of a circuit for demultiplexing high-speed data among data multiplexing / demultiplexing circuits using a line input line output (FIFO) memory according to an embodiment of the present invention; FIG.

Explanation of symbols on the main parts of the drawings

10: Input data of FIFO 11: Write clock

12: magnitude clock enable signal 13: output data of FIFO

14: Read Clock 15: Read Clock Enable Signal

16: reset signal 110: transmit end block

120: receiving end block 111 (121): line interface

112: T1 / E1 Framer 113 (123) Driver / Receiver

114,116 (124,126): PGA 115 (125): DSP

117 (127): Transceiver 118 (128): Rom

130: CPU 210: transmitting end block

220: receiving end block 211 (221): line interface

212: T1 / E1 Framer 213 (223): Driver / Receiver

214,216 (224,226): PGA 215 (225): FIFO

217 (227): Transceiver 230: CPU

300: E1 mapping clock generator 400: HDSL frame control unit

410: STUFF 420: HDSL framer

500: FIFO data check unit 511: first write latch

512: second write latch 521: first read latch

522: second read latch 531: first comparator

532: second comparator 600: HDSL framer mapper

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a high speed data transmission apparatus according to an embodiment of the present invention. As shown, the difference from the conventional configuration is that a pre-input line output memory IC (hereinafter referred to as a FIFO memory) 215 and 225 is used instead of the DSP ICs 115 and 125 which function to multiplex and demultiplex data. There are no ROMs 118, 128 that drive conventional DSP ICs 115,125.

The FIFO 215 is a pre-input line output memory (First-In, First-Out Memories), and the signals inputted by the write clock and write clock enable signals are first input to the read clock and read clock enable signals. The memory output by

3 and 4 show signals associated with FIFO memories 215 and 225. As shown, the reset signal 16 resets the FIFO memories 215 and 225. For this signal to operate, there must be at least four write clocks and four read clocks. Write data 10 refers to input data. The write clock 11 represents a clock used for inputting data to the FIFO memories 215 and 225. The write data 10 is input in synchronization with the rising edge of the write clock 11.

The write enable signal 12 is a signal for validating the write clock 11 and must be + 5V to drive the clock. The read enable 15 is a signal that validates the read clock 14 and must be + 5V to drive the clock.

The read clock 14 is a clock used to read data from the FIFO memories 215 and 225. The read data 13 is output in synchronization with the rising edge of the read clock 14.

FIG. 5 is a detailed circuit diagram of a data multiplexing / demultiplexing circuit using a line input line output (FIFO) memory provided in a high speed data transfer device (HDSL) according to an embodiment of the present invention. The FIFO memory 215 and the FIFO memory are shown in FIG. A detailed circuit block diagram of PGA blocks 214 and 216 for operating 215 shows a case of transmission of DS1E (E1) that demultiplexes high speed data.

As shown, an E1 mapping clock generator 300 which receives an E1 signal input from an external data terminal device (DTE) and generates a clock for mapping E1 DATA, and an E1 DATA input from an external E1 mapping clock. On the basis of the write clock generated from the generator 300, the FIFO memory unit 215 divided into the A region and the B region so as to be alternately received and stored for each time slot, and the signal generated from the E1 mapping clock generator 310 When the clock phase between the data terminal device (DTE) and the line is different from the input, the stuffing (STUFF 410) is stuffed to synchronize and the input is synchronized by the stuff (STUFF 410) to create a basic HDSL frame. HDSL framer 420 for outputting a clock and read enable signal for reading data from FIFO memory 215, and the first 8 bits TS0 input to the FIFO memory unit 215. Write latches 511 and 512 comprising first and second write latches 511 and 512 for latching and storing the second 8 bits TS1 by the latch clock output from the E1 mapping clock generator 300 and the latch clock enable. And the first 8 bits TS0 and the second 8 bits of the data output from the FIFO memory unit 215 based on the read latch clock and the read latch clock enable signal output from the HDSL frame controller 400. Read latch sections 521 and 522 comprising first and second read latches 521 and 522 to read and latch the data, and whether the data of the first write latch 511 and the data of the first read latch 521 are the same. Compare the data of the second write latch 512 with the data of the second read latch 522 and compare the same with each other. When the data input / output to the FIFO memory unit 215 is not the same, the FIFO memory unit 215 Resetting the first and second comparators 531 and 532 and the first and second memory units of the FIFO memory 215 when the FIFO data input and output based on the FIFO data input and output confirmation unit 500 are normal. It is composed of the HDSL framer mapper 600 for mapping the output E1 / 2 DATA to the frame made by the HDSL framer 420 to be transmitted to the track.

E1 DATA is FIFO write data (10), CLOCK is a write clock (11) with 2.048 Mbps, CLKEN 1,2 inputs E1 DATA (10) to the FIFO A area and the next eight to FIFO B area. A write clock enable signal 12 that allows input.

RDCLK1,2 is a read clock 14 having 1,168 Kbps and RDCLKEN is a read clock enable signal 12. E1 / 2 DATA is FIFO read data 13.

First, E1 DATA refers to a data frame having 32 timeslots, and timeslot refers to 8 bits of data. The first timeslot (TS0) and the seventeenth timeslot (TS16) serve a specific purpose.

The E1 mapping clock generator 300 generates an E1 receiving clock, a signal indicating TS0, TS16, an E1 receiving clock 8-division clock by data received from an external data terminal (DTE), and enables a write clock. It also generates a signal. The stuff (STUFF 410) and the HDSL framer 420 is a block associated with the HDSL frame to create a basic HDSL frame and synchronizes when the clock phase between the data terminal (DTE) and the line is different. The HDSL framer mapper 600 inserts E1 / 2 DATA into a frame made by the HDSL framer 420 and transmits it on a line.

Looking at the operation, E1 DATA is input to the A, B areas of the FIFO (205). At that time, the write clock (CLOCK) is 2.048 Mbps. The write clock is operated by the clock enable signals CLKEN1 and 2, and TS0 is input to the FIFO 205 area A, and TS1 is input to the FIFO 205 B area, and the timeslot is alternately inputted to the FIFO 205. It is input in the A and B areas.

The first 8 bits TS0 input to the FIFO 205 are stored in the first write latch 511 which is the first 8 bit latch circuit to be written by the latch clock LAT_CLK_A and the latch clock enable LAT_EN1.

The second 8-bit TS1 is stored in the second write latch 512, which is the write second 8-bit latch circuit, by the latch clock LAT_CLK_A and the latch clock enable LAT_EN2. At this time, the clock enable signal and the latch clock enable signal of the FIFO are synchronized with the HDSL frame structure for reading data from the FIFO 205.

The HDSL frame has a total structure of 6ms. The first 14 bits are used for synchronization, and the FIFO write clock enable signal is also synchronized to it.

The read clock enable (RDCLKEN) signal can be operated at a desired time after a certain period of time after the 14-bit synchronization signal. The read clock (RDCLK1,2) is 1,168Kbps in the DS1E class, but if Nx64Kbps in V.35, the clock depends on the N value. For example, in the case of DS1E, a total of 16 bytes of clocks, but when N = 2, only one byte (8 bits) of clocks of the FIFO 205 A and B areas appears.

This read clock outputs read data (E1 / 2 DATA). The read data is placed in the payload position in the HDSL frame and goes to the line.

There is a need to check whether the input data and the output data are the same and whether the data is in place. Thus, the first 8 bits of the output data are stored in the first read latch 521 which is the first 8 bit latch circuit by the latch clock LAT_CLK_B and the latch clock enable LAT_ENB.

The second 8-bit data is also stored in the second read latch 522, which is the second 8-bit latch circuit, by the latch clock LAT_CLK_B and the latch clock enable LAT_ENB. The first and second 8 bit values previously stored in the write latch circuits 511 and 512 and the read latch circuits 521 and 522 stored in the write latch circuits 511 and 512 are compared at a predetermined time. This fixed time should not exceed 6ms after storage. If possible, store the second 8 bits of the read and compare them on the clock.

The comparison operation is performed every 6ms. If the comparison is incorrect, the FIFO A and B areas are reset. At this time, at least four write clocks and read clocks must be present.

This operation demultiplexes E1 DATA into two E1 / 2 DATAs, and conversely, two E1 / 2 DATAs coming from the track can be multiplexed into one E1 DATA.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common knowledge in the art that various substitutions, conversions, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those who have

According to the present invention, high-speed data can be processed in real time by a write clock and a read clock, and can be operated by a designed circuit even without an external driving circuit such as a ROM. In addition, when interworking with a data terminal device (DTE) having a transmission rate of Nx64 Kbps, even if the N value is an odd number, there is no malfunction such as a clock glich, so that a circuit for stable data transmission can be implemented. The pins associated with the FIFO are all external, making debugging and circuit design easier.

Claims (3)

In a data multiplexing / demultiplexing circuit of a high speed data transmission device (HDSL), The data demultiplexing circuit, An E1 mapping clock generator 300 which receives an E1 signal input from an external data terminal device (DTE) and generates a clock for mapping E1 DATA; A pre-input line output (FIFO) divided into a first memory unit and a second memory unit to alternately receive and store E1 DATA input from the outside based on the write clock generated from the E1 mapping clock generator 300. A memory unit 215; Receives the signal generated from the E1 mapping clock generator 300 to create a basic HDSL frame, and synchronizes when the clock phase between the data terminal device (DTE) and the line is synchronized and reads data from the FIFO memory 215. An HDSL frame control unit 400 for providing a clock; The data written to the FIFO memory 215 is latched on the basis of the write clock generated by the E1 mapping clock generator 300 and from the FIFO memory 215 on the basis of the control clock of the HDSL frame controller 400. A FIFO data input / output checker 500 for reading and latching the output data, comparing the two values with each other, and resetting the FIFO memory 215 when the two values are different; If the FIFO data input / output based on the FIFO data input / output confirmation unit 500 is normal, the HDSL framer 420 outputs E1 / 2 DATA output from the first and second memory units of the FIFO memory 215, respectively. Data multiplexing / demultiplexing using a pre-input line output (FIFO) memory provided in a high speed data transmission device (HDSL), characterized in that it comprises a HDSL framer mapper 600 for transmitting to the line by mapping to the frame made in Circuit. The method of claim 1, wherein the HDSL frame controller 400 receives a signal generated from the E1 mapping clock generator 310 and stuffs to synchronize when a clock phase between the data terminal device and the line is different from each other. With stuff (STUFF 410) to say, The HDSL framer 420 is configured to receive the input synchronized by the stuff (STUFF 410), to make a basic HDSL frame, and to output a clock and a read enable signal for reading data from the FIFO memory 215. A data multiplexing / demultiplexing circuit using a line input line output (FIFO) memory provided in a high speed data transmission device (HDSL). The method of claim 1, wherein the FIFO data input and output confirmation unit 500, The first 8 bits TS0 and the second 8 bits TS1 input to the pre-input line output memory FIFO 215 are latched by a latch clock and a latch clock enable output from the E1 mapping clock generator 300. Write latch units 511 and 512 each comprising first and second write latches 511 and 512 for storing; The first 8 bits TS0 and the second 8 bits of data output from the FIFO memory unit 215 are respectively read based on the read latch clock and the read latch clock enable signal output from the HDSL frame controller 400. Read latch sections (521, 522) comprising first and second read latches (521, 522) for latching; The data of the first write latch 511 and the data of the first read latch 521 are compared with each other to compare the data of the second write latch 512 with the data of the second read latch 522. The latch data comparison unit 531 or 532 includes first and second comparators 531 and 532 which reset the FIFO memory unit 215 when the data inputted and outputted to the FIFO memory unit 215 are not the same. A data multiplexing / demultiplexing circuit using a line input line output (FIFO) memory provided in a high speed data transmission device (HDSL).