KR100460514B1 - SDH transmission system - Google Patents

Abstract

The present invention provides a bit kneeling block unit comprising a plurality of blocks, a data extraction processor connected to the bit kneeling block unit and outputting a predetermined clock and parallel data among optical signals input from an external device, and outputting from the data extraction processor. STM-1 ReFraming, AU pointer analysis, and TU pointer analysis are sequentially processed using the clock signal and parallel data. Then, each of the 84 channel control clock signals (Rctrl [83: 0]) and data (Rd [7: 0]) is output to each LIU block, and the clock signal of the data extraction processing unit is divided into four to generate a 6M clock signal of a set phase and read mux address signal muxad to read data in different phases. Provided is an SDH transmission device comprising a mux address unit to generate.

The present invention as described above includes a mux and a clock means in the bit-knicking block section having a plurality of bit-knocking blocks, thereby multiplexing the signals of the bit-knicking blocks, thereby demultiplexing the PDH signal from each bit-knicking block section. As the number of line ports is significantly reduced, the space design of the transmission system can be maximized accordingly, and as the number of lines of PDH data is reduced in the demultiplexing direction, the number of pins of the system implemented as a chip is significantly reduced. It also significantly reduces costs.

Description

SDH transmission system {SDH transmission system}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SDH transmission apparatus, and more particularly, to an SDH transmission apparatus having a multiplexer and a clock means in a bit kneeling block including a plurality of bit kneeling blocks to demultiplex signals of a plurality of bit kneeling blocks.

In general, the transmission technology began with the spiral carrier in the 1910s, developed into the analog transmission technology, and in the form of a digital transmission technology. Later, in the 1960s, the digital transmission technology started to develop a T1 channel bank with a 1.544 Mbps transmission rate. It was. Moreover, the digital transmission method has been developed into an optical transmission method using an optical cable as a transmission medium. As the point-to-point type optical communication has evolved into an optical communication network, as a result of standardization of a broadband integrated information network (B-ISDN), It is called synchronous transmission.

Here, while making a synchronous optical network (SONET) connection standard to enable the construction of the network by the optical communication systems, this is also referred to as the network node interface (NNI) standard of B-ISDN. Synchronized digital hierarchy (SDH) has been generalized for use, and a synchronous transmission scheme is a transmission scheme based on this synchronous digital hierarchy. In particular, a new transmission method for configuring and transmitting the synchronous digital step signals is called a synchronous transmission method, compared to a conventional communication method for constructing similar synchronous digital step signals and transmitting them through a baseband.

Therefore, through the synchronous multiplexing process, the existing DS-1 to DS-4 level signals are multiplexed into STM-n signals, reconstructed through a digital access cross-connet system (DACS) device, and transmitted through a synchronous optical communication network. It can be called a synchronous transmission method through a series of synchronous processing to reproduce.

Then, referring to the SDH transmission apparatus as described above with reference to FIG. 1, a plurality of blocks, for example, 21 blocks multiplexing a PDH (Plesiochronous digital hierarchy) signal transmitted from a subscriber side to an STM-n signal or performing a reverse process thereof. STM-n data, for example, ck_155M and dt_155M serial data, input from an external device, for example, an exchange device 71, respectively, connected to the bit-knicking block section 70A-N and the bit-knicking block section 70A-N. For example, a 19M and 6M clock for extracting a constant clock and parallel data, a data extraction processor 72 for outputting 8-bit parallel data Rstm1 [7: 0], and 19m output from the data extraction processor 72. STM-1 ReFraming, AU pointer analysis, and TU pointer analysis are processed sequentially using the clock and 8-bit parallel data (Rstm1 [7: 0]), and then the control clock signal (Rctrl [83] : 0]) and data (Rd [7: 0]) for each LIU It comprises a (70A-N) SDH processor 73 for output.

In addition, each of the bit nicking block units 70A-N uses a control signal system clock independent of the data input signal for each channel to reproduce the actual T1 / E1 data rxdt and a clock rck. A plurality of bit-leaking blocks (74A-D) are provided.

Here, four bit kneeling blocks 74A-D are provided in one bit kneeling block unit 70A-N in the case of T1 and three in the case of E1. In this case, the total 21 bit kneeling blocks 70A are provided. -N) processes a total of 84 channels.

In addition, an 8-bit data (7: 0) and an individual channel control signal (RCTRL [83: 0]) are provided from the SDH processor 73 at the input terminal of each of the bit knee block 74A-D. 72, clock signals 19M and 6M are provided, respectively.

On the other hand, in the operation of the conventional SDH transmission apparatus 75 as described above, when the PDH signal is input from the lower subscriber side to the bit nicking block unit 70A-N, the bit nicking block unit 70A-N receives the input PDH. The signal is multiplexed and converted into an STM-1 format optical signal for transmission to an external device such as an exchange 71.

On the other hand, when the multiplexed STM-1 signal is input to the data extraction processing unit 72 of the SDH transmission unit 75, the data extraction processing unit 72 is an STM-n input from an external device, for example, the exchange 71. By extracting a constant clock and parallel data from the data, for example, ck_155M and dt_155M serial data, for example, 19M clock and 6M clock are provided in 21 bit-knicking block portions 70A-N, that is, 4 bits each for T1. The knee block 74A-D and the SDH processor 73 are inputted, and another 19M clock signal and 8-bit parallel data Rstm1 [7: 0] are outputted to the SDH processor 73.

Then, the SDH processor 73 uses the 19m clock outputted from the data extraction processor 72 and the 8-bit parallel data Rstm1 [7: 0] to determine the bit-bit of each bit-knicking block unit 70A-N. STM-1 ReFraming, AU pointer analysis, TU pointer analysis, etc., which control the nicking block 74A-D, are processed sequentially, followed by control clock signals (Rctrl [83: 0]) and data, which are control signals for each 84 channels. (Rd [7: 0]) is output to the bit-knitting blocks 74A-D of the corresponding LIU block 70A, respectively.

As a result, the SDH processor 73 displays the information bits of each of the T1 / E1 channels in the 84-channel VC11 or 63-channel VC12 signal, the pointer stuff decision signal for bit-kneading, and the VC11 / VC12 signal. The Rctrl signal and the data signal indicating the separate control signal for each of 84 channels such as the enable signal to be expressed are output to the corresponding bit-knicking block units 70A-N.

Then, the corresponding bit-knitting block 74A-D of the bit-knicking block unit 70A-N is provided from the data extraction processor 72 using a control signal system clock independent of the data input signal for each channel. Actual T1 / E1 data (rxdt) and clock based on the 19M and 6M clock signals and the control clock signals Rctrl [83: 0] and data Rd [7: 0] provided from the SDH processor 73 rck) will output it. At this time, the output of each of the bit-knitting blocks 74A-D independently outputs rpdt [83: 0], rndt [83: 0], and rck [83: 0].

However, the conventional SDH transmitter as described above requires 504 ports for the T1 / E1 channel data and the clock signal on the system based on the capacity of one STM-1, and only 504 ports are needed for such simple PDH line data. Therefore, there is a lot of difficulties in the design of the transmission system to implement it according to the complexity, and also, the implementation cost of the transmission system to implement the 504 photos as described above also has a significant increase.

In addition, the conventional SDH transmission device as described above is a separate control for controlling the phase between the T1 / E1 channel data signal and the channel clock signal in accordance with the characteristics of the demultiplexed T1 / E1 clock and data bit biting block There was a problem that a signal was needed.

Accordingly, the present invention has been invented to solve the above-mentioned general problems, and since the number of line ports of the PDH signal demultiplexed from each bit-knitting block unit is considerably reduced, SD can maximize the spatial design of the transmission system accordingly. The purpose is to provide a transmission apparatus.

Another object of the present invention is to provide an SD transmission apparatus in which the number of pins of a system implemented as a chip is significantly reduced as the number of lines of PDH data is reduced in a demultiplexing direction.

The present invention for achieving the above object is to demultiplex the optical PDH signal received from an external device and a bit kneeling block portion consisting of a plurality of blocks, and the optical input from an external device connected to the bit kneeling block portion, respectively The STM-1 ReFraming, AU pointer analysis, and TU pointer analysis are sequentially performed by using a data extraction processor for outputting a predetermined clock and parallel data among signal serial data, and a clock signal and parallel data output from the data extraction processor. An SDH processor for outputting the control clock signals Rctrl [83: 0] and data Rd [7: 0] for each of the 84 channels to the respective bit-needing block units; S which is composed of mux address unit which generates 6M clock signal of set phase and generates mux address signal muxad to read data in different phases. H. provides a transfer apparatus.

1 is an explanatory diagram illustrating a conventional SDH transmission apparatus.

2 is an explanatory diagram illustrating an SDH transmission apparatus of the present invention.

<Detailed Description of Codes>

1A-N: Bit Knicking Block Part 2: Data Extraction Processing Unit

3: SDH processor 4: mux address part

5A-D: Beat Kneading Block 6: Muxbu

7: latch 8: clock phase latch

9: mux address generator 10A-D: first to fourth latch portions

11A-D: 1-4 Forward Latch Section 12A-D: 1-4 Nest Latch Section

13: SDH transmitter

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The apparatus of the present invention demultiplexes the received PDH signal as shown in Fig. 2, and includes, for example, bit-knicking block portions 1A-N consisting of a plurality of blocks, for example, 21-bit blocks, and 1-N. For example, the 25M and 19M clock signals and 8-bit parallel data extracting a predetermined clock and parallel data from STM-n data, for example, ck_155M and dt_155M serial data, respectively, connected to an external device such as a switch (not shown). STM-1 using the data extraction processing section 2 which outputs Rstm1 [7: 0]) and the 19M clock signal output from the data extraction processing section 2 and 8-bit parallel data Rstm1 [7: 0]. ReFraming, AU pointer interpretation and TU pointer interpretation are processed sequentially, and then the bit clocking block is assigned to the control clock signal (Rctrl [83: 0]) and data (Rd [7: 0]), which are control signals for each 84 channel. The 25M clock signal of the SDH processor 3 and the data extraction processor 2 outputted to the units 1A-N. Is divided into four to generate a six-phase 6M clock signal, and the mux address unit 4 for generating a mux address signal muxad to read data in different phases.

Each LIU block 1A-N uses a control signal system clock independent of the data input signal for each channel to reproduce the actual T1 / E1 data rxdt and clock rck, for example, 4 (T1). ) Or 3 (E1) bit knocking blocks 5A-D and the data output terminals rxdt [0-3] of the four bit knocking blocks 5A-D, respectively. A mux section 6 for multiplexing and outputting the data of the bit-needing blocks 5A-D according to the mux address signal of the &quot; muxad &quot;, and a constant clock for stabilizing a data signal multiplexed by the mux section 6; For example, a plurality of latches 7 latched with a 25M clock signal and a plurality of clock stages of the bit knocking blocks 5A-D are connected to each other, and a clock signal of each channel is fixed to a predetermined clock, for example, a 25M clock signal. It consists of a plurality of clock phase latches 8 for latching at edges and falling edges, respectively. .

In addition, the mux address generator 9 outputs the system clock of the data extraction processing unit 2, for example, 25 M clock signal, to the mux address unit 4 in four divisions, and generates a mux address signal of the mux unit 6. And a 4-phase clock, for example, a 6-M clock signal, in which the bit divider blocks 5A-D have different timings by serially shifting the 6-M clock signals divided into four by the MUX address generator 9, respectively. The first to fourth latch units 10A-D are generated.

Here, the first latch portion 10A is connected to the input terminal of the bit nicking block 5A, and the second latch portion 10B is connected to the input terminal of the bit knitting block 5B. Is connected to the input terminal of the bit kneeling block 5C, and the fourth latch portion 10D is connected to the input terminal of the bit kneeling block 5D, respectively.

On the other hand, the clock phase latch unit 8 receives a clock signal of each of the bit knee block (5A-D) in order to have a system clock, that is, the width of the 25M clock signal to the clock edge in the center of the data 25M clock signal A first latching latch unit 11A-D latched at a positive edge of a low clock and outputting the bit clocking block 5A so that the width of the system clock, that is, the 25M clock signal, is at the center of the data so that the clock edge is at the center of the data. And a first to fourth latch portion 12A-D for receiving the clock output signals of -D) and latching them at the negative edges of the clocks as 25M clock signals.

Here, four bit nicking blocks 5A-D are provided in one LIU block 1A-N in case of T1 and three in case of E1.

In addition, an 8-bit data (7: 0) and an individual channel control signal (RCTRL [83: 0]) are provided from the SDH processor 3 to the input terminal of each of the bit-neaking blocks 5A-D. The clock signal 19M from 2) and the 6M clock signal are provided from the mux address section 4, respectively.

Next, the operation and effect of the apparatus of the present invention as described above will be described.

First, when a PDH signal is input to a LIU block (not shown) from a lower subscriber side, the LIU block multiplexes the input PDH signal and converts the PDH signal into an STM-1 format optical signal for transmission to an external device such as an exchange. .

On the other hand, when the multiplexed STM-1 signal is input to the data extraction processing section 2 of the SDH transmission apparatus 13, the data extraction processing section 2 is configured as STM-n data input from an external device, for example, a switch. By extracting a constant clock and parallel data from the ck_155M and dt_155M serial data, for example, a 19M clock signal is included in each of the 21 bit biting blocks 1A-N and 4 (T1) or 3 (E1) bit biting blocks 5A. -D) and the SDH processor 3, and another 19M clock signal and 8-bit parallel data Rstm1 [7: 0] are outputted to the SDH processor 3. The 25 M clock signal of the data extraction processing section 2 is also input to the mux address generator 9 of the mux address section 4.

Then, the SDH processor 3 uses the 19m clock outputted from the data extraction processing unit 2 and the 8-bit parallel data Rstm1 [7: 0] to bit bite block 1A-N. STM-1 ReFraming, AU pointer interpretation, TU pointer interpretation, etc., which controls (5A-D) are processed sequentially, and then the control clock signal (Rctrl [83: 0]) and data (Rd), which are the control clocks for each 84 channels, are processed. [7: 0]) are outputted to the bit-knitting blocks 5A-D of the corresponding bit-knicking block portions 1A-N, respectively.

As a result, the SDH processor 3 transmits information indicating 84 VC11 or 63 channel VC12, a pointer stuff decision signal for bit-kneading, and information bits of each T1 / E1 channel in the distinct VC11 / VC12 signal. The Rctrl signal and the data signal indicating a separate control signal for each 84 channels such as the enable signal to be expressed are output to the corresponding bit-knicking block units 1A-N.

At this time, the mux address generator 9 of the mux address unit 4 divides the 25M clock signal provided from the data extraction processing unit 2 into four first and fourth latch units 10A-D, and outputs two bits. A mux address signal muxad [1: 0] is generated and outputted to the mux part 6 provided in each bit-knicking block part 1A-N. At the same time as the operation, the first to fourth latch units 10A-D of the mux address unit 4 respectively shift the 6M clock signals divided by 4 by the mux address generator 9 in series to each bit. By outputting to the plurality of bit nicking blocks 5A-D provided in the nicking block portions 1A-N, the plurality of bit nicking blocks 5A-D of the respective bit nicking block portions 1A-N are different from each other. A four phase clock, e.g., a 6 M clock signal, is provided to have timing.

For example, the first latch portion 10A is connected to the input terminal of the bit knocking block 5A, and the second latch portion 10B is connected to the input terminal of the bit knitting block 5B. Is connected to the input terminal of the bit kneeling block 5C, and the fourth latch portion 10D is connected to the input terminal of the bit kneeling block 5D, respectively.

On the other hand, the corresponding bit-knitting blocks 5A-D of the bit-knicking block sections 1A-N are provided from the data extraction processing section 2 using a control signal system clock independent of the data input signal for each channel. 6M clock signal provided from 19M and first to fourth latch units 10A-D and control clock signal Rctrl [83: 0] and data Rd [7: 0] provided from the SDH processor 3. Based on this, the actual T1 / E1 data rxdt and the clock rck are reproduced and output to the mux section 6.

Here, the mux part 6 provided in each of the bit-knicking block parts 1A-N is formed at the timing of each bit-knicking block by the 6M clocks of the first to fourth latch units 10A-D. 5A-D) to read and multiplex the data, wherein the mux section 6 reads and multiplexes the data according to the mux address signal provided from the mux address generator 9 of the mux address section 4 and outputs the multiplexed signal. (s_rxdt) is output to the latch 7. Then, the latch 7 latches and outputs a predetermined clock, for example, a 25M clock signal to stabilize the data signal multiplexed by the mux unit 6 (rxdt [0]-[20].

That is, the mux unit 6 provided in each of the bit-knicking block units 1A-N multiplexes the data signals of the bit-knicking blocks 5A-D provided in the bit-knicking block units 1A-N. Because of the output, the conventional output of 84 channels is output only to 21 signal lines of 1/4.

Therefore, when using the device of the present invention, the number of ports can be considerably reduced.

Meanwhile, while the data output process is in progress, each of the bit knocking blocks 5A-D transmits the respective clock signals rck0 to rck3 to the first to fourth phases of the clock phase latch unit 8 for data phase alignment. Output to the forward latch parts 11A-D and the 1-4th latch part 12A-D, respectively.

Then, the first-fourth forward latches 11A-D of the clock phase latching unit 8 allow the clock edge of the 25M clock signal provided from the system clock, that is, the data extraction processing unit 2 to be at the center of the data. In order to receive each clock output signal of the bit-kneading block (5A-D) to receive a 25M clock signal at the clocked edge of the clock output. At the same time, the first-4 latch portions 12A-D also output the clocks of the bit-neaking blocks 5A-D so that the width of the system clock, that is, the 25M clock signal, is at the center of the data. It receives the signal and latches it on the negative edge of the clock with 25M clock signal.

Therefore, if the clock is processed through the above process, the same data value can be obtained at both the positive edge and the negative edge of each channel, so that a control signal for controlling the phase relationship between the separately outputted data and the clock is not necessary. Will not.

As described above, the present invention provides a PDH demultiplexed from each bit kneeling block part by multiplexing signals of the plurality of bit kneeling block parts by providing a mux and a clock means in a bit kneeling block part having a plurality of bit nicking blocks. Since the number of line ports of the signal is considerably reduced, the space design of the transmission system can be maximized accordingly.

In addition, according to the present invention, as the number of lines of PDH data is reduced in the demultiplexing direction, the number of pins of a system implemented as a chip is also considerably reduced, thereby reducing the manufacturing cost of the SDH transmission device.

Claims (8)

Demultiplexing the PDH signal received from an external device and outputting a predetermined clock and parallel data among serial bit input block units composed of a plurality of blocks and optical signal serial data input from an external device, respectively, connected to the bit nicking block unit. Demultiplexing the STM-1 signal sequentially using the data extraction processing unit, the clock signal output from the data extraction processing unit, and parallel data, and then outputs the control clock and data signal for each 84 channel to each bit knee block. SDH processor and a mux address unit for generating a clock signal of a predetermined phase by dividing the clock signal of the data extraction processing unit and generating a mux address signal (muxad) to read data in different phases Transmission device. 2. The apparatus of claim 1, wherein the mux address unit divides the clock signal of the data extraction processing unit into four to generate 6M clock. 2. The MUX address generator according to claim 1, wherein the MUX address unit divides the system clock signal of the data extraction processing unit into four and outputs the MUX address signal, and generates a MUX address signal, and the 6 M clock signal divided by four by the MUX address generator. An SD transmission apparatus comprising: first to fourth latches for generating a 4-phase 6M clock signal by serial shifting so that a plurality of bit-knitting blocks have different timings. The apparatus of claim 3, wherein the first to fourth latch units are configured as D flip-flops. The bit biting block unit of claim 1, wherein the bit biting block unit is configured to reproduce the actual T1 / E1 data (rxdt) and the clock (rck) using a control signal system clock independent of the data input signal for each channel; A mux part which is connected to the data output terminals rxdt [0 ~ 3] of the N bit knocking blocks, respectively and multiplexes and outputs the data of the bit nicking block according to the muxad signal muxad of the mux address part; A latch for latching a system clock signal to stabilize the multiplexed data signal, and a plurality of latches connected to each clock terminal of the bit knocking block to convert a clock signal of each channel into a system clock signal. An SD transmission apparatus comprising a plurality of clock phase latches latched at an edge of each falling edge. 6. The apparatus of claim 5, wherein the latch is configured of a D flip flop. The clock phase latch unit of claim 5, wherein the clock phase latch unit receives the respective clock output signals of the bit-knocking block and latches them at a positive edge of the clock as a system clock signal, and outputs the latched signals. SD transmission apparatus comprising a first to four latch portion for receiving each clock output signal of the latch and outputs the system clock signal by latching at the negative edge of the clock. 8. The apparatus of claim 7, wherein the first to fourth latch portions and the first to fourth latch portions comprise D flip flops.