KR0152724B1 - E1-ds3 multiplexing/demultiplexing device - Google Patents

Abstract

The present invention provides a clock synchronization unit 103 for synchronizing E1 signals at 2.048 MHz synchronized with 44.736 MHz, and a stuffing block for performing bit filling by inputting the E1 signals synchronized by the clock synchronization unit 103 ( 102, the 21-channel multiplexing block 101 for multiplexing the bit signals filled by the stuffing block 102 according to the 21-channel simultaneous stuffing request signal, and the signal of the 21-channel multiplexing block 101 again DS-3. A DS-3 multiplexing block 100 for multiplexing the signal, a synchronous clock extracting unit 104 for providing a clock signal synchronized with a predetermined signal to each of the blocks, and E1 inverting the multiplexed signal of the SD-3; DS-3 demultiplexing block 200, 21-channel demultiplexing block 201, and de-stuffing block 202, and the signals of the DS-3 multiplexing and demultiplexing block 100, 200 for extracting the signals into signals. Composed of DS-3 bipolar connection unit 300 for switching output to input and output signals 20 DS-1E (E1: 2.048 Kbps) paths, which are pseudo-synchronous digital hierarchy (PDH), capable of accepting B or 2B + D channels in digital transmission, to DS-3 (44.736 Mbps). Can be multiple / demultiplex

Description

E1-DS3 Multiple / Demultiplex Devices

1 is a block diagram showing a preferred embodiment of the E1-DS3 multiple / demultiplex apparatus according to the present invention.

2 is an E1-DS3 frame structure diagram according to the present invention.

3 is a circuit diagram showing an embodiment of the stuffing block shown in FIG.

4 is a timing chart for the main block of FIG.

* Explanation of symbols for main parts of the drawings

100: DS3 multiplexed block 101: 21 channel multiplexed block

102 stuffing block 103 clock synchronization unit

104: synchronous clock extraction unit 200: DS-3 demultiplexing block

201: 21-channel demultiplexing block 202: De-stamping block

300: DS-3 bipolar connection 400,401: D flip flop

The present invention relates to an E1-DS3 multiple / demultiplex apparatus applied to a multi-transmission system. More specifically, the DS-1E (E1) signal, which is a different scheme of PDH, is a DS-3 signal. E1-multiplexing or demultiplexing 21 E1 signals using the batch-aligned bit filling (hereinafter referred to as bit buffering) in synchronism with the E1 signal and the DS-3 clock. A DS3 multiple / demultiplex device.

Pseudo-synchronous digital hierarchy (PDH), which is typically used for digital transmission, is divided into North American and European styles, and hierarchical multiplexing has been performed only in the same manner. In other words, in the North American DS-1, DS-2 and DD-4E, the lower level signal can be multiplexed into the upper level signal, but the European DS-1E signal is multiplexed into the North American type DS-2 or DS-3. Was not much. However, at present, most transmission devices adopt DS-3 class transmission, and the hierarchical signal used for B channel or 2B + D channel is adopted from DS-1 (T1) to DS-1E (E1) signal. In order to transmit the E1 signal through the transmission device at the time point (especially in Korea), a multiple / demultiplex device is required in the DS-3 class.

Conventionally, in order to multiplex E1 signal to DS-3, E1 (2.048Mbps) signal is multiplexed into RAM DS-3E (34.368Mbps) signal, and this DS-3E signal is mapped to DS-3 (44.736Mbps) signal. Although the multiplexing method has been used, this method has a problem that it becomes a very inefficient multiplex transmission method due to the excessive number of overheads.

The present invention has been made in view of the above problems, and an object of the present invention is DS-1E (E1), which is a Pliochronous Digital Hierarchy (PDH) that can accommodate a B channel or a 2B + D channel in digital transmission. A device capable of multiplexing / demultiplexing 20 signals of 2.048 Kbps to DS-3 (44.736 Mbps), wherever E1 signals such as video on demand (VOD) or digital telephone networks or narrowband ISDN networks are required. It is to provide a possible E1-DS3 multiple / demultiplex device.

It is a further object of the present invention to provide an input of multiple demultiplexing for bit-giving stuffing alignment in such a manner that bit-interleaving 21 E1 signals and performing synchronous synchronous multiplexing directly to DS-3 signals. The present invention provides an E1-DS3 multiple / demultiplex device using a method of eliminating the difference in the output clock.

It is still another object of the present invention to provide an E1-DS3 multiple / demultiplex apparatus capable of performing efficient multiplexing by directly reducing an overhead by multiplexing an E1 signal into a DS-3 signal.

A feature of the E1-DS3 multiple / demultiplex apparatus according to the present invention for achieving the above objects is a clock synchronizing unit for synchronizing E1 signals at 2.048 MHz synchronized to 44.736 MHz, and an E1 signal synchronized by the clock synchronizing unit. A stuffing block for performing bit filling by inputting the input signal, a 21 channel multiplexing block for multiplexing bit signals filled by the stuffing block according to a 21 channel simultaneous stuffing request signal, and a signal of the 21 channel multiplexing block. A DS-3 multiplexing block multiplexed into a -3 signal, a synchronous clock extracting unit providing a clock signal synchronized with each predetermined block to each block, and extracting the SD-3 multiplexed signal as an E1 signal DS-3 demultiplexing block, 21-channel demultiplexing block and de-stamping block, and DS-3 bypass for switching and outputting signals of the DS-3 multiplexing and demultiplexing block into input / output signals It is the point consisting of La connection.

Hereinafter, one preferred embodiment of the E1-DS3 multiple / demultiplex apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a preferred embodiment of the E1-DS3 multiple / demultiplexer according to the present invention.

Referring to FIG. 1, the E1-DS3 multiplexing / demultiplexing apparatus includes a clock synchronizing unit 103 for synchronizing E1 signals at 2.048 MHz synchronized with 44.736 MHz, and E1 synchronized by the clock synchronizing unit 103. A stuffing block 102 for bit filling by inputting signals, a 21 channel multiplexing block 101 for multiplexing the bit signals filled by the stuffing block 102 according to a 21 channel simultaneous stuffing request signal, and A DS-3 multiplexing block (100) for multiplexing the signals of the 21-channel multiplexing block (101) again with a DS-3 signal; and a synchronous clock extracting unit (104) for providing a clock signal synchronized with a predetermined signal to each of the blocks; Consists of

In addition, in order to demultiplex the DS3 signal into the E1 signal, the DS-3 demultiplexing block 200, the 21 channel demultiplexing block 201, and the demultiplexer for extracting the multiplexed signal of the SD-3 into the E1 signal inversely. It is composed of a stuffing block 202, and finally the DS-3 bipolar connection unit 300 for switching the output signal of the DS-3 multiplexing and demultiplexing block 100, 200 into an input / output signal, the block 100 It is a structure connected to the rear end of the ().

Therefore, according to FIG. 1, 20 E1 (2.048 Mbps) signals are multi- or demultiplexed using DS-3 (44.736 Mbps) signals.

First, the clock synchronizer 103 of the input stage synchronizes the E1 signals at 2.048 MHz in synchronization with the DS-3 clock 44.7336 MHz. Since the 2.048 MHz clock cannot be divided by the 44.736 MHz clock, 64 MHz, which is a common factor of 2.048 MHz and 44.736 MHz, is selected to make 2.048 MHz synchronized to 44.736 MHz using a digital phase loop lock (DPLL). This part is unnecessary if the E1 input signals are synchronized at 44.736 MHz.

Multiple / demultiplex devices use the basic structure of the North American DS-3 basic frame and accept E1 (2.048 Mbps) data using the payload bits except the DS2's own overhead bits in the basic MS-3 signal frame. 2 shows a DS-3 frame structure for mapping 21 E1 signals to DS-3.

The total number of bits in the DS-3 frame is 4760 bits. In the frame structure of Figure 2, the payload area excluding the overhead is 4585 bits, so the DS-3 read clock is 43.09129412MHz because the DS-3 frame rate is 9398.319328㎐. In addition, since 21 E1 write clocks are 2.048 MHz x 21 = 43.008 MHz, the difference in data rate resulting from the difference between the write clock and the read clock is compensated by bit stuffing alignment.

Meanwhile, the stuffing block 102 shown in FIG. 1 is composed of an elastic store buffer and a stuffing request signal generating circuit. As an example, a circuit composed of two D flip-flops 400 and 401 is shown in FIG. 3, which is an example of a stuffing request signal generation circuit when the elastic storage buffer is configured as an 8-bit buffer cell. .

Therefore, an elastic storage buffer is configured for stuffing to compensate the allowable input jitter and to act as a data storage buffer for clock differences.

In this example, the stuffing request signal is generated when the 8-division output of the write clock (43.09129412 21 = 2.051966387MHz) latches the 8-division output of the write clock (2.048MHz) clock and there is stuffing demand during the HIGH output. (See also FIG. 4 waveform).

In the frame structure shown in FIG. 2, since the payload area allocated is 4585 bits and the total number of bits in one frame is 4760 bits, the transmission rate of payload data is transmitted at a speed of 44.736 (4585/4760) = 43.09129412 Mbps. When using 21 bits of stuffing for 21 signals, at 44.736 (21 / (4760x) = 43.09129412-43.008, x must transmit 2.369491459, or 21 bits of stuffing invalid bits per 2.369491459 frame, with a stuffing rate of 1 / x = 0.422031458.

Conversely, during demultiplexing, the detection of stuffing control bits (ST-FLAG: Stuffing Bit Flag Bits in Figure 2) must be prioritized for de-stamping, and the extracted data determines the presence of stuffing by a majority decision method. For example, it is determined that there is stuffing when three or more of the five bits are recognized as one.

Therefore, this system is a device that demultiplexes 21 synchronous E1 (2.048Mbps) signals to DS-3 (44.736Mbps) signals and fills the difference between multiple input and output clocks. Rewarded in a way.

The present invention is a device that multi / demultiplexes DS-1E (E1) data to DS-3 level, a system for multi / demultiplexing E1 signal to DS-3 level, digital telephone network, N-ISDN networks as well as BOD system. For example, it can be used anywhere in a system that multiplexes E1 signals to DS-3.

Therefore, according to the present invention, 21 E1 signals are configured as DS-3 frames shown in FIG. 2, and the 21 demultiplexing devices are used to multiply 21 E1 signals synchronized with a DS-3 44.736MHz clock. The bit-stuffing method can be used to multiplex and reverse demultiplex the DS-3 data signals.

As described above, according to the E1-DS3 multiple / demultiplex apparatus according to the present invention, a clock synchronizing unit for synchronizing E1 signals with 2.048 MHz synchronized with 44.736 MHz, and E1 signals synchronized with the clock synchronizing unit are inputted. A stuffing block for performing bit filling, a 21 channel multiplexing block for multiplexing the bit signals filled by the stuffing block according to a 21 channel simultaneous stuffing request signal, and a signal of the 21 channel multiplexing block again multiplexed into a DS-3 signal A DS-3 multiplexing block, a synchronous clock extracting unit for providing a clock signal synchronized to each block with a predetermined signal, and a DS-3 inverse to extract the multiplexed signal of the SD-3 as an E1 signal Multiplexing block, 21-channel demultiplexing block and de-stuffing block, and DS-3 bipolar connection for switching and outputting signals of the DS-3 multiplexing and demultiplexing blocks into input / output signals 20 DS-1E (E1: 2.048 Kbps) signals, which are pseudo-synchronous digital hierarchy (PDH), that can accommodate B or 2B + D channels in digital transmission. ) Can be multiple / demultiplexed by

Therefore, the present invention has an advantage that can be directly applied to multiple transmission systems such as digital telephone or narrowband integrated telecommunication network (ISDN) or VOD service network.

In addition, the overhead can be greatly reduced by the conventional method, so that multiple DS-1E channels can be multiplexed to the DS-3, which is economically advantageous.

Claims (1)

A clock synchronizing unit 103 for synchronizing the E1 signals at 2.048 MHz synchronized with 44.736 MHz, a stuffing block 102 for performing bit filling by inputting the E1 signals synchronized by the clock synchronizing unit 103; 21-channel multiplexing block 101 for multiplexing the bit signals filled by the stuffing block 102 according to the 21-channel simultaneous stuffing request signal, and multiplexing the signals of the 21-channel multiplexing block 101 into DS-3 signals. The DS-3 multiplexing block 100, a synchronous clock extracting unit 104 for providing a clock signal synchronized to each block with a predetermined signal, and the multiplexed signal of the SD-3 is reversely extracted as an E1 signal. DS-3 demultiplexing block 200, 21-channel demultiplexing block 201, and de-stamping block 202, and the signals of the DS-3 multiplexing and demultiplexing block 100, 200 for outputting the signals as input / output signals. E1-DS3 consisting of DS-3 bipolar connections 300 for switching output. Medium / Demultiplex Device.