KR970004489A

KR970004489A - E1-DS3 Multiple Demultiplex Devices

Info

Publication number: KR970004489A
Application number: KR1019950017954A
Authority: KR
Inventors: 박경용
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-06-28
Filing date: 1995-06-28
Publication date: 1997-01-29
Also published as: KR0152724B1

Abstract

본 발명은 44.7㎒에 동기된 2.048㎒로 E1신호들을 동기화 시키는 클럭동기부(103)와, 상기 클럭동기부(103)에 의해 동기된 E1신호들을 입력으로 하여 비트 채워넣기를 수행하는 스터핑 블럭(102)과, 상기 스터핑 블럭(102)에 의해 채워진 비트신호들을 21채널 동시 스터핑 요구신호에 따라 다중화 하는 21채널 다중화 블럭(101)과, 상기 21채널 다중화 블럭(101)의 신호를 재차 DS-3 신호로 다중화 하는 DS-3 다중화 블럭(100)과, 상기 각각의 블럭에 소정신호로 동기된 클럭신호를제공하는 동기클럭 추출부(104)와, 상기 SD-3의 다중화된 신호를 역으로 E1신호로 추출해내기 위한 DS-3 역다중화 블럭(200), 21채널 역다중화 블럭(201) 및 디스터핑 블럭(202)과, 상기 DS-3 다중화 및 역다중화블럭(100)(200)의 신호를 입출력 신호로 스위칭 출력하기 위한 DS-3 바이폴라 접속부(300)로 구성되어서, 디지탈 전송에서 B 채널 또는 2B+D 채널을 수용할 수 있는 유사동기식 디지탈 계위(PDH : Pliochronous Digital Hierarchy)인 DS-1E(E1 : 2.048Kbps)신로 20개를 DS-3(44.736Mbps)로 다중/역다중할 수 있다.The present invention provides a clock synchronizing unit 103 for synchronizing E1 signals at 2.048 MHz synchronized with 44.7 MHz, and a stuffing block for performing bit filling by inputting the E1 signals synchronized by the clock synchronizing unit 103 ( 102, the 21-channel multiplexing block 101 for multiplexing the bit signals filled by the stuffing block 102 according to the 21-channel simultaneous stuffing request signal, and the signal of the 21-channel multiplexing block 101 again DS-3. A DS-3 multiplexing block 100 for multiplexing the signal, a synchronous clock extracting unit 104 for providing a clock signal synchronized to each block with a predetermined signal, and E1 inversely multiplexing the multiplexed signal of the SD-3; DS-3 demultiplexing block 200, 21-channel demultiplexing block 201, and de- stuffing block 202, and DS-3 multiplexing and demultiplexing blocks 100 and 200 for extracting the signals into signals. DS-3 bipolar connection 300 for switching output to input and output signals Thus, 20 DS-1E (E1: 2.048 Kbps) signals, which are pseudo-synchronous digital hierarchy (PDH), that can accommodate either B or 2B + D channels in digital transmission, are transferred to DS-3 (44.736 Mbps). Can be multiple / demultiplex

Description

E1-DS3 Multiple / Demultiplex Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 E1-DS3 다중/역다중 장치의 바람직한 일실시예를 나타낸 블럭도, 제2도는 본 발명에 따른 E1-DS3 프레임 구조도, 제3도는 제1도에 도시된 스터핑 블럭의 일 실시예를 나타낸 회로도이다.FIG. 1 is a block diagram showing a preferred embodiment of the E1-DS3 multiple / demultiplex apparatus according to the present invention, FIG. 2 is an E1-DS3 frame structure diagram according to the present invention, and FIG. 3 is a stuffing block shown in FIG. A circuit diagram showing one embodiment of the present invention.

Claims

A clock synchronizing unit 103 for synchronizing E1 signals at 2.048 MHz synchronized with 44.36 MHz, a stuffing block 102 for performing bit filling by inputting the E1 signals synchronized by the clock synchronizing unit 103; 21-channel multiplexing block 101 for multiplexing the bit signals filled by the stuffing block 102 according to the 21-channel simultaneous stuffing request signal, and multiplexing the signals of the 21-channel multiplexing block 101 into DS-3 signals. The DS-3 multiplexing block 100, a synchronous clock extracting unit 104 for providing a clock signal synchronized to each block with a predetermined signal, and the multiplexed signal of the DS-3 is reversely extracted as an E1 signal. DS-3 demultiplexing block 200, 21-channel demultiplexing block 201, and de-stuffing block 202, and the signals of the DS-3 multiplexing and demultiplexing block 100, 200 for outputting the signals as input / output signals. E1-DS3 consisting of DS-3 bipolar connections 300 for switching output. / Demultiplexer devices.

※ Note: The disclosure is based on the initial application.