KR100382696B1 - European Type Plesiochronous Multiplexing System Accommodating both DS-1E and DS-1 - Google Patents

Abstract

The present invention relates to a European asynchronous multiplexing system that can accommodate DS-1E according to the European digital hierarchy as well as DS-1 according to the North American digital hierarchy for asynchronous multiplexing in the European fashion.

The multiplexing system of the present invention includes a line matching unit and first to fourth line matching devices each including an elastic buffer; The multiplexing unit is configured to multiplex four parallel input signals output from the elastic buffers of the first to fourth line matching devices by mapping them to one DS-2E serial signal.

In this case, the internal frames of the multiplexing unit are each composed of first to fourth sets of 212 bits, and in case of multiplexing data of four parallel input signals according to the North American digital hierarchy method, among the data mapping of the frames according to the European digital hierarchy method. In the first to fourth sets of data bits (# 1-# 205), data bits # 4, # 8, ..., # 200, # 204 at positions corresponding to multiples of 4 are not mapped. By inserting the dance bit, the DS-1E input signal according to the European digital hierarchy and the DS-1 input signal according to the North American digital hierarchy can be selected and accommodated.

Description

European Type Plesiochronous Multiplexing System Accommodating both DS-1E and DS-1}

The present invention relates to a European-style asynchronous multiplexing system, and more particularly to a European-style asynchronous multiplexing system that can accommodate DS-1E according to the European digital hierarchy as well as DS-1 according to the North American digital hierarchy to the European-style asynchronous multiplexing. It is about.

The European Plesiochronous Digital Hierarchy (PDH), or multiplexing system, uses four 2.048 Mbps European Digital Signal-Level 1 (DS-1E) signals of 8.448 Mbps for the European Digital Signal-Level (PDH). Multiplexes one (2) DS-2E signal.

In the conventional asynchronous multiplexing system, each line matching unit 11 converts input DS-1E bipolar signals into unipolar signals, and maps to DS-2E bit streams for multiplexing the converted unipolar signals. Output from the first to fourth line matching device (1a-1d) and the first to fourth line matching device (1a-1d) consisting of an elastic buffer 12 for the buffering action It consists of a multiplexer 3 which maps four parallel input signals DS-1E (1) to DS-1E (4) to one DS-2E serial signal.

Here, the overall structure of the frame inside the multiplexer 3 is shown in FIG. 2A, and the detailed structure for each set SETI-SETIV is shown in FIG. 2B.

The frame inside the multiplexer 3 consists of 848 bits in total, and is composed of first to fourth sets (SETI-SETIV) each of 212 bits.

The first set SETI comprises 50 bits each consisting of a 10-bit DS-2E synchronization signal F, a 1-bit alarm bit A, a 1-bit reserved bit N, and 4 bits each. The second set SETII is composed of four bits of the first stuffing control bit C1 and 52 DS-1E data bits (four bits each). The third set (SETIII) is composed of four bits of the second stuffing control bit (C2) and 52 DS-1E data bits (# 103- # 154) each of four bits; The fourth set (SETIV) is a 4-bit third stuffing control bit (C3), 4-bit DS-1E data or dance bit (V), and 51 DS-1E data bits (# 155) each consisting of 4 bits. -# 205).

In the asynchronous multiplexing of the multiplexer 3, the clock of the input DS-1E signal and the common clock used in the DS-2E are independent of each other, and stuffing control bits equal to the speed difference between the common clock and the input signal clock. ) Requires insertion.

The DS-1E input signal clock is 2.048MHz and the common clock is divided into four by dividing 8.448MHz and removing the overhead area, resulting in 2.04226-2.05223MHz with or without stuffing.

The above can be summarized as an expression.

When inserting the dance bit into the V position: 2.112 * (205/212) = 2.04226 MHz

When mapping data to V position: 2.112 * (206/212) = 2.05223 MHz

In other words, if DS-1E data is mapped to V position, the input signal clock is faster than common clock, so there is a phase difference between the two clocks. When the difference is 1 bit, the dance bit is inserted into the V position and the stuffing control bit (C) Stuffing information is sent to send. Since the input signal clock is delayed every time the dance bit is inserted, the phase difference between the two clocks is corrected.

Here, the data of each DS-1E (1) to DS-1E (4) is always mapped bitwise to the data bits (# 1- # 205) positions of the DS-2E frame, and the V position is common to the input signal clock. If the phase difference of the clock is less than 1 bit, the data of DS-1E is mapped. If more than 1 bit, the dance bit is inserted. At this time, if the data bit is mapped to the V position, "0" is allocated to the stuffing control bits C1, C2, and C3, and "1" is allocated when the dance bit is inserted.

Therefore, in order to maintain the average speed of the common clock at 2.048 MHz equal to the input signal clock speed, the following results are obtained.

8.448 = 2.048 * 4 * (848/824) * (206 / (206-S))

S = 0.424

In other words, the dance bit insertion rate in the V position is 42.4%.

The European asynchronous multiplexing is only possible for multiplexing the DS-1E (2.048 Mbps) signal according to the European digital hierarchy.

However, in Korea, digital signal-level 1 (DS-1) signals of 1.544 Mbps according to the North American digital hierarchy are also used. The European asynchronous multiplexing is inherently impossible to accept the North American digital hierarchy.

Accordingly, the present invention has been made in view of the problems of the prior art, and its object is to accommodate DS-1E signals according to the European digital hierarchy as well as DS-1 signals according to the North American digital hierarchy for asynchronous multiplexing in the European system. It is to provide a European asynchronous multiplexing system.

1 is a schematic block diagram of a conventional European asynchronous multiplexing system,

2A and 2B are an overall structural diagram of each of the multiplexing unit of FIG. 1 and a detailed structural diagram of each set;

3 is a schematic block diagram of a European asynchronous multiplexing system for accommodating DS-1E and DS-1 according to the present invention;

4A and 4B are structural diagrams of the entire internal frame of the multiplexer of FIG. 3 and detailed structural diagrams of each set.

* Explanation of Signs of Major Parts of Drawings *

21; Line matching part 22; Elastic buffer

31a-31d; Line matching device 33; Multiplexer

In order to achieve the above object, the present invention converts one of the DS-1 bipolar signal according to the North American digital hierarchy and the DS-1E bipolar signal according to the European digital hierarchy into a unipolar signal, respectively, according to the selection signal. A first and fourth line matching device including a line matching unit for setting an electrical interface condition according to the type, and an elastic buffer buffering to map the converted unipolar signal to a DS-2E bit stream for multiplexing the converted unipolar signal; ; A multiplexer for multiplexing four parallel input signals output from the elastic buffers of the first to fourth line matching devices by mapping them to one DS-2E serial signal; The internal frame of the multiplexer is composed of first to fourth sets of 212 bits each, and the first set is a 10-bit DS-2E synchronization when multiplexing data of four parallel input signals according to the European digital hierarchy method. Signal, one bit of alarm bit, one bit of reserved bit, and 50 data bits (# 1- # 50) each consisting of four bits, and the second set includes four bits of first stuffing control bits, respectively. 52 data bits (# 51- # 102) of 4 bits, and a third set of 52 data bits (# 103- # 154) of 4 bits, respectively, and a second stuffing control bit of 4 bits. The fourth set is composed of four bits of third stuffing control bits, four bits of data bits or dance bits, and 51 data bits (# 155- # 205) each of four bits, and according to the North American digital hierarchy method. When multiplexing data of four parallel input signals Data bits (# 4, # 8, ..., ...) at positions corresponding to multiples of four in the first to fourth sets of data bits (# 1- # 205) among the data mapping of frames according to the European digital hierarchy method. # 200, # 204) can be accommodated by selecting the DS-1E input signal according to the European digital hierarchy and the DS-1 input signal according to the North American digital hierarchy by inserting dance bits without mapping data. Provides European asynchronous multiplexing system.

As described above, in the conventional European asynchronous multiplexing system, only the multiplexing of DS-1E (2.048 Mbps) according to the European digital hierarchy was possible and the acceptance of DS-1 (1.544 Mbps) according to the North American digital hierarchy was fundamentally impossible. In the present invention, both can be accommodated by appropriately inserting a dance bit into an internal frame of the multiplexer.

(Example)

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 3 is a schematic block diagram of a European asynchronous multiplexing system for accommodating DS-1E and DS-1 according to the present invention, and FIGS. 4A and 4B are internal structural views of the multiplexing unit of FIG. Detailed structural diagram of each set.

The asynchronous multiplexing system according to the present invention can accommodate not only DS-1E according to the European digital hierarchy but also DS-1 according to the North American digital hierarchy for asynchronous multiplexing in the European system. As described above, the line matching unit 21 converts one of the DS-1 and DS-1E bipolar signals inputted according to the selection signal of the multiplexer 33 into a unipolar signal and sets an electrical interface condition according to the input signal type. And first to fourth line matching devices 31a to 31d each including an elastic buffer 22 for buffering the DS-2E bit stream for multiplexing the converted unipolar signal. Four parallel input signals DS-1 / DS-1E (1) to DS-1 / DS-1E (4) output from the elastic buffers 22 of the first to fourth line matching devices 31a to 31d, respectively. ) To the multiplexer 33 for mapping one DS-2E serial signal. It is sex.

Here, the overall structure of the frame inside the multiplexer 33 is shown in FIG. 4A, and the detailed structure for each set SETI-SETIV is shown in FIG. 4B.

The frame inside the multiplexer 3 is composed of 848 bits in total as in the prior art, and is composed of first to fourth sets (SETI-SETIV) each of 212 bits, and the detailed data format of each set is set as follows. .

Unlike in the past, the line matching unit 21 of the present invention accepts the input signals of the DS-1 and the DS-1E, and the DS-1E is the same as the conventional operation. However, when multiplexing the input signal of DS-1, the input signal clock is 1.544MHz, so the speed difference between common clock and input signal clock when multiplexing DS-1E multiplexes exceeds the control range by stuffing. Therefore, the dancing bit is regularly inserted in the DS-2E frame so that the common clock speed is closest to 1.544 MHz so that it can be controlled by stuffing.

Therefore, when multiplexing data of each DS-1E in FIG. 4B, all of them are mapped to data bits (# 1-# 205) of the DS-2E frame as in the prior art.

That is, when multiplexing DS-1E data, the first set SETI includes a 10-bit DS-2E synchronization signal F, a 1-bit alarm bit A, and a 1-bit reserved bit. (N) and 50 DS-1E data bits (# 1-# 50) each consisting of 4 bits, and the second set (SETII) is composed of 4 bits of the first stuffing control bit (C1), respectively. It consists of 52 DS-1E data bits (# 51- # 102) of 4 bits, and the third set (SETIII) consists of 4 bits of the second stuffing control bit (C2) and 52 DS-1E data of 4 bits each. Bits (# 103- # 154), and the fourth set (SETIV) is composed of four bits of the third stuffing control bit (C3), four bits of DS-1 / DS-1E data or dance bit (V). And 51 DS-1E data bits (# 155- # 205) each of 4 bits.

However, when multiplexing the data of DS-1, the data bit positions (# 4, # 8, # 12, ..., # 200, # 204) corresponding to multiples of 4 among the data bits (# 1- # 205). In this example, the dance bit is inserted without mapping data. Therefore, when multiplexing DS-1, 51 of the total 205 data bit positions are always inserted with dance bits, and the stuffing control bits C1, C2, and C3 and V are used in the same manner as in the case of DS-1E.

The DS-1 input signal clock is 1.544MHz and the common clock is 8.4434MHz-1.54415MHz with or without stuffing after removing 8.448MHz by 4 and removing the overhead and dance bit areas.

The above can be summarized as an expression.

When inserting the dance bit in the V position: 2.112 * ((205-51) / 212) = 1.53419 MHz

When mapping data to the V position: 2.112 * ((206-51) / 212) = 1.54415 MHz

Therefore, in order to maintain the average speed of the common clock at 2.048 MHz, which is the same as the clock speed of the DS-1E input signal, the same method as in the prior art is used. In order to maintain 1.544MHz, the following result is obtained.

8.448 = 1.544 * 4 * (848/620) * (155 / (155-S))

S = 0.015

That is, the dance bit insertion rate in the V position is 1.5%.

As described above, in the conventional European asynchronous multiplexing system, only the multiplexing of DS-1E (2.048 Mbps) according to the European digital hierarchy was possible and the acceptance of DS-1 (1.544 Mbps) according to the North American digital hierarchy was fundamentally impossible. In the present invention, both the accommodating bits can be accommodated by appropriately inserting a dance bit into the internal frame of the multiplexer 33.

As described above, in the present invention, multiple bits can be selectively multiplexed with the DS-1E according to the European digital hierarchy and the DS-1 according to the North American digital hierarchy by inserting and using a dance bit appropriately in the internal frame of the multiplexing unit.

In the above, the present invention has been illustrated and described with reference to specific preferred embodiments, but the present invention is not limited to the above-described embodiments and is not limited to the spirit of the present invention. Various changes and modifications can be made by those who have

Claims (1)

A line that converts one of the DS-1 bipolar signal according to the North American digital hierarchy and the DS-1E bipolar signal according to the European digital hierarchy into a unipolar signal according to the selected signal, and sets the electrical interface conditions according to the input signal type. First to fourth line matching devices comprising a matching unit and an elastic buffer buffered to map a DS-2E bit stream for multiplexing the converted unipolar signal; Four parallel input signals DS-1 / DS-1E (1) to DS-1 / DS-1E (4) output from the elastic buffers of the first to fourth line matching devices are connected to one DS-2E. A multiplexer for mapping and multiplexing the serial signal; The internal frame of the multiplexer is composed of first to fourth sets of 212 bits, respectively. In the case of multiplexing data of four parallel input signals DS-1E (1) to DS-1E (4) according to the European digital hierarchy method, the first set includes a 10-bit DS-2E synchronization signal F. And one bit of alarm bit (A), one bit of reserved bit (Reserved) (N), and 50 data bits (# 1- # 50) each consisting of four bits. The first set of control bits (C1) and 52 data bits (# 51- # 102) consisting of four bits each, the third set of four bits of the second stuffing control bit (C2) and 52 bits each consisting of four bits The fourth set consists of four bits of the third stuffing control bit (C3), four bits of data bits or dance bits (V), and four bits of 51 pieces of data. Bits (# 155- # 205), In the case of multiplexing data of four parallel input signals DS-1 (1) to DS-1 (4) according to the North American digital hierarchy method, the first through the first to the second data mapping of the frame according to the European digital hierarchy method. In the four sets of data bits (# 1- # 205), the data bits (# 4, # 8, ..., # 200, # 204) at positions corresponding to multiples of four are inserted with no dance bits. And a DS-1E input signal according to the European digital hierarchy and a DS-1 input signal according to the North American digital hierarchy.