KR19980015805A - VC Payload Extraction Clock Generation Circuit Based on Positioning in Synchronous Multiplexer - Google Patents

Abstract

The present invention generates a VC1 payload extraction clock according to whether the received TUG2 clock is aligned with the received TUG2 clock to store the corresponding VC1 payload from the TUG2 data in the extraction buffer 46 and reads the data from the buffer 46 according to the transmission clock A TU clock generating unit (41) for generating a TU pointer clock and a VC1 clock indicating a position of a TU pointer from a TUG2 clock; A pointer analyzer 42 for analyzing the V1 and V2 vectors from the received TUG2 data according to the TU pointer clock to detect occurrence of alignment; A pointer increase signal ptrinc is output if the new data flag NDF and the size ss are normal according to the output of the pointer analysis unit and the pointer decrement signal ptrdec is output A fitting determination section 43; A payload extraction clock generation unit 44 for receiving the output of the TU clock generation unit 41 and the output of the alignment determination unit and generating a write clock for extracting the corresponding VC1 payload from the TUG2 data, it is possible to extract a pure payload in consideration of justification.

Description

A VC payload clock generation circuit based on position alignment in a synchronous multiplexer (VC payload clock according to a synchronous multiplexer)

The present invention relates to a synchronous multiplexing apparatus, and more particularly to a circuit for generating a VC payload extraction clock considering justification for extracting a VC payload from a TUG received from a counterpart and transmitting the payload to another counterpart will be.

In general, a synchronous optical transmission apparatus synchronously multiplexes signals (for example, DS1 and DS1E) multiplexed in a pseudo-synchronous manner, converts the signals into optical signals from an optical transmitter, transmits the optical signals to an opposite station through an optical cable, And converts the signal into an electric signal, and outputs the synchronized demultiplexed signal. A process of forming a STM-1 frame of 155.520 Mbps by synchronously multiplexing pseudo-synchronous multiplexed signals in such a synchronous optical transmission apparatus is schematically described as follows.

The DS1 frame input from the user side is mapped to the C-Container and becomes C-11. When path overhead (POH) is added to the C-11, the virtual container VC-11 becomes a virtual container A pointer (PTR) is added to the tally unit (TU: TU-11). In addition, TU-11 is grouped into four groups of TU-2, and then multiplexed into VC-3 and VC-4, and VC-3 is multiplexed through AU (Admistrative Unit) AU-3 3 are multiplexed to become a management unit group (AUG), and a section overhead (SOH) is added thereto to finally become STM-1. At this time, the European type DS1E is mapped to C-12, and path overhead (POH) is added to become a virtual box VC-12. Here, the box C is a basic unit constituting a synchronous multiplexing structure (that is, a payload of a VC), and existing asynchronous digital hierarchical signals are mapped in a corresponding box and multiplexed in a synchronous manner. There are C-1, C-2, C-3 and C-4, C-1 is again C-11 for mapping North American DS1E and C-12 is for mapping European DS1EE. A virtual container (VC) is formed by adding path overhead (POH) to a virtual box as a signal unit for supporting connection between path layers in a synchronous transmission, and the gradation signal unit (TU) A pointer is added to a virtual box for adapting between layers VC-1 and VC-2 and an upper path layer VC-3 and VC-4, (AU) uses an AU pointer as a signal unit for providing an adaptation function between an upper path layer and a multiplexer section layer, and an AU pointer is used as a signal unit for providing an adaptation function between an upper path layer and a multiplexer section layer. AU (AU) refers to a combination of one or more management unit (AU) signals arranged in a fixed location in the STM paid space.

On the other hand, the structure of the VC11 formed by mapping the DS1 of the North American system is as shown in Fig. 1a, and the format of the low path overhead (referred to as V5) is as shown in Fig.

In FIG. 1A, the structure of VC11 is formed by 26 bytes in one frame of 125 Ls, and four frames are gathered to form a multi-frame of 500 Ls. Therefore, the entirety of the VC-11 consists of 104 bytes, and the first byte of the first frame is also referred to as V5 as the low path overhead (POH), and has a format as shown in FIG. V5 followed by one byte with fixed bits (R, R, R, R, R, R, I, R) followed by 24 bytes of information data mapped to DS1. The second frame consists of J2 bytes, Y1 bytes with C1, C2, O, O, O, O, I, R format and 24 bytes of information data. The third frame consists of Z6 bytes and C1, C2, O, O , Y2 bytes having O, O, I, R format, and 24 bytes of information data. The fourth frame consists of Z7 bytes and Y3 bytes having C1, C2, R, R, R, , And 24 bytes of information data.

Where S1 represents a stuffing bit, I represents an information bit, C1 and C2 represent a justification control bit, S1 and S2 represent alignment firing bits, and eight O bits and Z6 represent a pre- It is used as a head.

As shown in FIG. 1B, the low path overhead V5 is composed of BIP-2, FEBE (REI), RFI, signal levels L1, L2 and L3 and remote alarm 'Indicates the result of the even parity for the odd-numbered bits in all the bytes of the immediately preceding VC11 at 1 and inserts the result of the even parity for the even-numbered bits into the 2-bit. If the number of error blocks is more than one, the 'REI' is transmitted to the transmitting side and the 'RFI' is transmitted to the transmitting side. TU-1 / TU-2 AIS "or" 1 "when the FAIL signal is not released. A signal level (L1, L2, L3) indicates that the signal level is set to 0 in the unconfigured mode and 1 in the unspecified mode, 10 indicates asynchronous floating, 11 indicates bit synchronous, and 100 indicates byte synchronous.

FIG. 2 is a diagram showing the structure of a VC 12 to which a DS1E of the European scheme is mapped. The structure of the VC-12 is formed by 35 bytes in one frame of 125 Ls. . Thus, the entire VC-12 consists of 140 bytes, and the first byte of the first frame is V5, which is the low path overhead (POH). V5 followed by an R * byte with a fixed bit followed by 32 bytes of information data mapped by the DS1E. The second frame consists of Y1 bytes and 32 bytes of information data in J2 byte and C1, C2, O, O, O, O, R, R formats, the third frame consists of Z6 bytes and C1, Y2 bytes and 32 bytes of information data having O, O, R, R format, the fourth frame consists of K4 bytes and Y3 bytes having formats C1, C2, R, R, R, R, Bytes of information data.

Where S1, S2 represent the alignment opportunity bits, and 8 O bits and Z6, K4 represent the stuffing bits, where I represents the information bits, C1 and C2 represent the justification control bits, It is used as a spare overhead.

FIG. 3A is a diagram showing that the low-order pointers V1, V2, V3, and V4 are added to the format of VC1 to form the TU1 signal. In the VC11, pointers V1, V2, V3, and V4 are added to become TU11, V1, V2, V3, and V4 are added to become TU12. When four such TU11s are aligned, they become TUG2, and when three TU12s are aligned, they become TUG2.

Here, V1, V2, and V3 are used as low-level pointers, the structure of which is shown in FIG. 2B, and the use of V4 is reserved. At this time, the high-level pointers (H1, H2, H3) used in AU-4, AU3, TU-3 and the like are similar to the pointers (V1, V2, V3)

In FIG. 3B, the first four bits (NNNN) of V1 (H1) are a new data flag bit, which is inverted to 1101 when the pointer is in a normal operating state and is changed to 1001 when the pointer value is changed to a new value. Subsequently, ss is set to 10 in the high-level pointers (H1, H2, H3) and 0 in TU2, 11 in TU11 and 10 in TU12 in the low-level pointers (V1, V2 and V3). The address of this pointer means that the address of the pointer is shifted from the pointer H3 to the start point of the VC in the case of the high-level pointer. In the case of the low-level pointer, the value of the pointer from the pointer V2 It indicates the degree of deviation to the VC start point. The 10-bit pointer consists of a 5-bit increment (I) bit and a 5-bit decrement (D) bit. When positive justification is in progress, the I bit is inverted and a negative justification The D bit is inverted. The address ranges of these pointers are summarized in Table 1 below.

Pointer-specific address ranges Pointer Size (ss) Address Range Pointer Size (ss) Address Range AU-4 10 0 to 782 TU-2 00 0 to 427 AU-3 10 0 to 782 TU-12 10 0 to 139 TU-3 10 0-764 TU-11 11 0 to 103

As shown in Table 1, the size (ss) is 11 and the address range is 0 to 103 in case of TU11. Then, V3 is used as a byte for transmitting valid data at the time of sub-alignment, and the first byte after V3 is used as a byte (invalid address) Opportunity bytes).

As described above, the lower gradation signals are mapped to the VC using the synchronous transmission method, and then floating freely in the payload space of the corresponding TU. At this time, the positional relationship of the lower gradation signals is shifted to the pointers (V1, V2, V3) Lt; / RTI > In this way, when the VC is aligned with the TU, the position is not fixed but is changed by the pointer. The floating mode is referred to as floating. On the other hand, when the TU is synchronized with the VC, (Locked mode).

On the other hand, when a synchronous transmission system is operated in an add / drop (ADD / DROP) type, it is necessary to transmit the lower level signal received from the counterpart to the other party, It is necessary to form a payload extraction clock. That is, since the position of the payload is changed according to the alignment of the received TUG2 clock and data, it is necessary to form a payload extraction clock considering the alignment through the analysis process.

The object of the present invention is to provide a circuit for generating a clock for extracting a VC payload in consideration of alignment in switching the received scrambling signal on a per VC basis in order to satisfy the above requirement .

According to another aspect of the present invention, there is provided a method of controlling a data processing apparatus, the method comprising: generating a VC1 payload extraction clock according to whether the received TUG2 clock is aligned with a received TUG2 clock, storing the VC1 payload from the TUG2 data in an extraction buffer, A TU clock generator for generating a TU pointer clock and a VC1 clock indicating a position of a TU pointer from a TUG2 clock; A pointer analyzer for analyzing the V1 and V2 vectors from the received TUG data according to the TU pointer clock to detect occurrence of alignment; An alignment determination unit for outputting a pointer increase signal if the new data flag NDF and the size ss are normal according to the output of the pointer analysis unit if the bit is inverted and output a pointer decrement signal if the bit is inverted; And a payload extraction clock generator for generating an output of the TU clock generator and an output of the alignment determining unit and generating a write clock for extracting the VC payload from the TUG2 data.

Thus, by generating the payload extraction clock in consideration of the variation of data due to the justification, it is possible to extract and process only the payload accurately in the floating mode.

FIG. 1A is a structure diagram mapping NAS DS1 to VC-11, FIG.

Figure 1B also shows the format of V5, the low path overhead,

FIG. 2 is a schematic diagram illustrating mapping of DS1E to VC12;

FIG. 3A is a diagram illustrating a concept of forming TU1 from VC-1,

FIG. 3B is a format showing a structure of a general pointer,

Figure 4 is a block diagram illustrating a circuit for extracting a payload from a received TUG in accordance with the present invention;

5 is a detailed block diagram of the alignment determination unit shown in FIG. 4,

FIG. 6 is a detailed block diagram of the payload extraction clock generation unit shown in FIG. 4,

FIG. 7 is a timing chart showing clocks at zero alignment,

8 is a timing chart showing each clock in sub-alignment,

Fig. 9 is a timing chart showing each of the clocks at the time of correct positioning.

DESCRIPTION OF THE REFERENCE NUMERALS

41: TU clock generation unit 42: Pointer analysis unit

43: alignment determination unit 44: payload extraction clock generation unit

45: write counter 46: buffer

47: Lead counter

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram showing a portion for generating a VC payload extraction clock from a TUG2 received from a counterpart according to the present invention and extracting the VC data and transmitting it to another counterpart. 4, the circuit for extracting the payload from the received TUG 2 includes a TU clock generation unit 41, a pointer analysis unit 42, an alignment determination unit 43, a payload extraction clock generation unit 44, A counter 45, a buffer 46, and a read counter 47.

The TU clock generator 41 generates a TU pointer clock for extracting the TU pointers V1, V2, and V3 from the TUG2 clock and generates a VC1 clock and a reception TU clock. The pointer analyzer 42 receives V1 And outputs a pointer clock for extracting the V2 and a VC1 clock, a V3 clock, and a reception TU clock rxtu_clk to the payload extraction clock generation unit 44. [ The TUG2 clock is a clock for transmitting TUG2 data of about 6048 Kbps as shown in FIG. 7D, and the reception TU clock is a clock including a TU pointer and a payload of VC1. When the VC1 clock is VC11, Pointer V1, V2, V3, and V4 by one bit for every 26 bits.

The pointer analyzing unit 42 latches the V1 pointer and the V2 pointer from the received TUG2 data according to the TU pointer clock and analyzes the signal so that the signal (ndfnorm) and the size (ss) indicating whether the new data flag (Ssnorm) indicating whether it is normal, and a signal indicating an increment bit inversion (Iinv) or a decrement bit inversion (Dinv), respectively. That is, as described above in the pointer, the first 4 bits (NNNN) of V1 is the new data flag bit, which is 110 when the pointer is in the normal operating state and is inverted to 1001 when the pointer value is changed to the new value . Therefore, the ndfnorm signal is 1 when the new data flag (NDF) is 110, and becomes 0 when it is inverted to indicate new data. The size (ss) is a bit for distinguishing the size of the payload, and is set to 0 for TU2, 11 for TU11, and 10 for TU12. Therefore, the ssnorm signal is set to 1 when the received data and the set size coincide with each other. The 10 bits represent the pointer value or the increment (I) bit of 5 bits and the decrement (D) bit of 5 bits, which is the sum of 2 bits of V1 and V2. Positive justification When proceeding, Iinv becomes 1, Dinv becomes 1 when the D bit is inverted and negative justification proceeds.

5, when the ndfnorm signal and the ssnorm signal input from the pointer analyzing unit 42 are both "1", the position alignment determination unit 43 performs an incremental inversion When the signal Iinv is 1, the pointer increase signal ptrinc is set to 1. When the decrease inversion signal Dinv is 1 when the ndfnorm signal and the ssnorm signal input from the pointer analyzing unit 42 are both 1, The pointer decrement signal (ptrdec) is set to 1 and output.

6, the payload extraction clock generation unit 44 receives the VC1 clock, the V3 clock, and the reception TU clock rxtu_clk from the TU clock generation unit 41. The payload extraction clock generation unit 44 receives from the alignment determination unit 43 a pointer (Ptrinc) and the pointer decrement signal (ptrdec) to generate a VC payload extraction clock (write clock) considering alignment. This clock is divided by the write counter 45 to generate the write address of the buffer, which is referred to as a write clock. 6, a VC1 clock is input to a d0 input terminal of the multiplexer 65. A V3 clock, a pointer increase signal ptrinc, and a VC1 clock, which are delayed by a predetermined clock from the delay unit 63, And the V3 clock and the pointer decrement signal ptrdec are ANDed in the AND gate 61 and input to the d3 input stage of the AND gate 64. Then, The computed clock is input. The pointer increase signal ptrinc and the pointer decrease signal ptrdec are input to the selected terminals s1 and s2 of the multiplexer 65 and one of the three inputs is selected as shown in Table 2 below.

Multiplexer selection signal S2 (ptrdec) S1 (ptrinc) Print Operating state 0 0 d0 Zero alignment (normal) 0 One d1 Fixed position alignment One 0 d2 Sub-position alignment

As shown in Table 2, when the pointer increase signal ptrinc is 0 and the pointer decrement signal ptrdec is 0, the VC1 clock (d0 input) is selected and output as the zero justification state, At this time, the V3 clock is gapped as shown in FIGS. 7A to 7H. If the pointer decrement signal ptrdec is 1 and the pointer increase signal ptrinc is 0, the d2 input is selected and output as a negative justification, and as shown in FIGS. 8A to 8H, V3 clock exists because valid data is transmitted. In contrast, when the pointer increasing signal ptrinc is 1 and the pointer decreasing signal ptrdec is 0, the d1 input is selected and outputted as a positive justification. Since the invalid data is transmitted to the clock, the V3 digit and the next clock are gapped.

The write counter 45 generates a write address in accordance with the write clock output from the payload extraction clock generator 44. The read counter 47 generates a read address in accordance with the read clock. The buffer 46 extracts and stores a payload from the TUG2 data at the address specified by the write address, and outputs the data specified by the read address as a payload for transmission.

Figs. 7A to 7H are timing charts showing respective clocks at zero alignment. Fig. 7A shows a pointer decreasing signal ptrdec, and Fig. 7B shows a pointer increasing signal ptrinc. FIG. 7C shows the reset signal, FIG. 7D shows the TUG2 clock, and FIG. 7E shows the TU clock. FIG. 7F shows the VC1 clock, FIG. 7G shows the V3 clock, and FIG. 7H shows the VC payload extraction clock (write clock). 7A to 7H, since the pointer increasing signal ptrinc and the pointer decreasing signal ptrdec are both 0, the VC payload extracting clock 7H is in the V3 vector clock Is a gapped clock.

Figs. 8A to 8H are timing charts showing respective clocks at the time of sub-alignment. Fig. 8A shows the pointer decrement signal ptrdec, and Fig. 8B shows the pointer increasing signal ptrinc. 8C shows a reset signal, FIG. 8D shows a TUG2 clock, and FIG. 8E shows a TU clock. FIG. 8F shows the VC1 clock, FIG. 8G shows the V3 clock, and FIG. 8H shows the VC payload extraction clock (write clock). 8A to 8H, since the pointer decrement signal (ptrdec) is 1 and the pointer increase signal (ptrinc) indicates 0, the VC payload extraction clock includes the V3 vector clock, so that V3 So that it is possible to extract the payload transmitted through the network.

9A to 9H are timing charts showing respective clocks at the time of proper positioning, in which FIG. 9A shows a pointer decrement (ptrdec) signal and FIG. 9B shows a pointer increment (ptrinc) signal. FIG. 9C shows the reset signal, FIG. 9D shows the TUG2 clock, and FIG. 9E shows the TU clock. FIG. 9F shows the VC1 clock, FIG. 9G shows the V3 clock, and FIG. 9H shows the VC payload extraction clock (write clock). 9A to 9H, since the pointer increasing signal ptrinc is 1 and the pointer decreasing signal ptrdec is 0, the VC payload extracting clock is set to 0 in the next byte of the V3 vector, The V3 clock and the immediately following clock are the gapped clocks.

As described above, according to the present invention, the payload extracting clock is generated according to the pointer increase and pointer decrement signals extracted from the received TUG2 signal, and then the payload of VC1 is extracted from the TUG2 data, and a simple payload can be extracted in consideration of justification.

Claims (2)

A VC1 payload extracting clock is generated according to whether the received TUG2 clock is aligned with the received TUG2 clock to store the corresponding VC1 payload from the TUG2 data in the extraction buffer 46 and the data is read from the buffer 46 in accordance with the transmission clock In the apparatus, A TU clock generator 41 for generating a TU pointer clock and a VC1 clock indicating the position of the TU pointer from the TUG2 clock; A pointer analyzer 42 for analyzing the V1 and V2 vectors from the received TUG2 data according to the TU pointer clock to detect occurrence of alignment; A pointer increase signal ptrinc is output if the new data flag NDF and the size ss are normal according to the output of the pointer analysis unit and the pointer decrement signal ptrdec is output A fitting determination section 43; And a payload extraction clock generation unit 44 that receives the output of the TU clock generation unit 41 and the output of the alignment determination unit and generates a write clock for extracting the corresponding VC1 payload from the TUG2 data, VC1 payload extraction clock generation circuit according to alignment in the device. The payload extracting clock generator (44) of claim 1, wherein the payload extracting clock generator (44) receives the VC1 clock at the d0 input terminal, a V3 clock, a pointer increase signal and a VC1 clock, delayed by a predetermined clock at a delay unit (63) A clock obtained by ANDing the AND gate 64 is inputted to the d3 input terminal and a V3 clock and a pointer decrement signal are ANDed in the AND gate 61 and then inputted to the d3 input terminal. And a multiplexer (65) for selecting one of three inputs according to a pointer increase signal and a pointer decrement signal. The VC1 payload extracting clock generating circuit .