JPH05327642A - Frame conversion method and conversion circuit - Google Patents

Abstract

PURPOSE:To convert a frame of synchronization digital multiplex structure into a frame for synchronization optical transmission network by replacing a position of a fixed stuff of a 1st frame into a determined position in a 2nd frame for the frame conversion. CONSTITUTION:When a 1st frame decided according to the protocol of the synchronization digital hierarchy(SDH) is converted into a 2nd frame decided by the protocol for a network different from the synchronization digital hierarchy, the frame is converted by replacing the position of a fixed stuff of the 1st frame into a predetermined position of the 2nd frame. That is, the position of the fixed stuff at the 2nd column and the 3rd column of the frame of a virtual container 4 (VC-4) of a synchronous transfer module N(STM-N) is replaced into a position of a fixed stuff in a VC-3 and the VC-3 subject to frame conversion is mapped to a management unit (AU-3).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame conversion method and a conversion circuit used in a digital transmission device, and more particularly,
Synchronous digital multiplexing structure (Synchronous Diplex)
VC-4 (Virtual Container 4, hereinafter referred to as VC-4) included in a Synchronous Transport Module N (hereinafter referred to as STM-N) in a gital hierarchy (hereinafter referred to as SDH)
The frame of the synchronous optical transmission network (Synchronous Op
tical network (hereinafter, referred to as SONET)).

[0002]

2. Description of the Related Art Generally, a protocol for a digital transmission device of this type includes a CEPT (Europian Post and
G70 of the International Telegraph and Telephone Consultative Committee (CCITT) based on the specifications of the Telecommunication Conference system.
7, G708, G709, and this protocol is defined on the premise of SDH. STM-N based on this protocol
Is a section overhead (hereinafter referred to as SOH), a management unit (Administrative Uni
t, hereinafter referred to as AU) and a payload, and the VC included in the payload is POH (Pass Ove).
rhead) and a data area. In particular,
The VC-4 is composed of 9 rows × 261 columns, and has a structure in which 1-byte POH is arranged in the first column and the subsequent 261-byte data is arranged in the remaining 260-byte column. In this case, fixed staffs are fixedly arranged in the second and third columns.

[0003]

Conventionally, the above-mentioned C.
C. I. T. No proposal has been made to convert SDH frames defined by T G707, G708, and G709 into SONET frames.

However, it is considered that such SDH frame containing VC-4 may be applied to SONET in the future, and when such application is considered, it is used for SONET. Frame is S
Since it is different from the TM-N frame, it is extremely important to consider the method and circuit for converting the SDH frame into the SONET frame.

Therefore, the technical problem of the present invention is, for example,
CEPT type SPEC. C. C. I. T. T's G707,
It is an object of the present invention to provide a frame conversion method and a conversion circuit for converting an SDH frame defined by G708 and G709 into a SONET frame.

Further, another technical problem of the present invention is SON.
Just connect the frame conversion circuit to the LSI for ET,
It is to provide a frame conversion circuit that can also be used as an SDH-compatible LSI.

[0007]

According to the present invention, it is defined according to the protocol of Synchronous Digital Hierarchy (SDH) having a path overhead and a fixed stuff provided at a fixed position with respect to the path overhead. A method of converting a first frame into a second frame defined by a protocol defined in a network different from that of the synchronous digital hierarchy, wherein a fixed stuff position of the first frame is defined in the second frame. A frame conversion method is obtained which is characterized in that conversion is performed by replacing the position with a predetermined position.

Such a frame conversion method can be realized by a simple conversion circuit by combining a counter and a memory.

[0009]

In the frame conversion circuit of the present invention, the positions of the fixed stuff in the second and third columns of the STM-N VC-4 frame are replaced with the positions of the fixed stuff in the VC-3 frame. The frame-converted VC-
3 is mapped to AU-3. Furthermore, three AU-3s
Is multiplexed into an AUG, N AUGs are multiplexed,
Furthermore, it outputs in the form of STM-N with SOH. By performing such conversion, it is possible to convert a frame including STM-N apparently including AU-4 into a frame including AU-3.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, there is shown a relationship between an STM-1 frame in SDH converted according to an embodiment of the present invention and a frame to be converted. First, in FIG. 1A, V consisting of 9 rows and 261 columns is used.
Of C-4, the 9-row x 87-column portion to be converted in this embodiment is shown. As a result, in this embodiment, an STM-1 demultiplexed frame (hereinafter, STM-) including a frame having a frequency of 1/3 of VC-4 (hereinafter, represented by (VC-4) / 3) is used. 1/3) is converted, but the entire STM-1 may be a frame to be converted. As shown in the figure, in the first column of VC-4, the path overhead (POH) indicated by J1, B3, C2, etc. is arranged by one byte, and the second and the second columns following the first column are arranged. Third
A fixed stuff R of 2 bytes is arranged in the column. Data is located in the remaining 84-byte columns. The positional relationship among the POH, R, and data portions in each row is floating, that is,
It floats and, as shown, does not necessarily have a rectangular shape. In addition, fixed staffs are arranged over three columns in each of the remaining 1/3 columns of the VC-4.

In the (VC-4) / 3 frame shown in FIG. 1A, as shown in FIG. 1B, a 3-byte section overhead (SOH) is contained in the first to third rows. And the fifth to ninth rows are added. In this case, each SOH is arranged in the first to third columns of each row described above, and the first to third columns of the fourth row are
An administrative unit pointer is arranged and a 90-byte STM-1 / 3 frame is configured.

On the other hand, the SON to be converted in this embodiment
As shown in Fig. 1 (c), the ET frame has a VC
-3 has a format structure. Specifically, the format of VC-3 consists of 9 rows x 87 bytes, and a 1-byte POH is arranged in the first column, but a 1-byte fixed stuff R is stored every 29 bytes from the first column. Are arranged. Even in the VC-3 having such a format structure, the positional relationship of POH, data, etc. in each row is floating.

In this embodiment, as shown in FIG. 1D, SOH and AU pointers are added to the VC-3 shown in FIG. 1C to form a SONET frame.

A frame conversion circuit according to an embodiment of the present invention will be described with reference to FIG. The illustrated frame conversion circuit includes a pointer processing / demultiplexing unit 1 that receives STM-1 input data and performs an operation described below, and a conversion unit 10 connected to the pointer processing / demultiplexing unit 1. I have it.

Here, the illustrated conversion unit 10 includes a clock signal (hereinafter referred to as 6M CLK) having a repetition frequency of 6.48 Mb / S from the outside (not shown), a pointer processing and demultiplexing unit 1. Received STM-1 / 3 from
It is connected to the memory unit 2 that converts a frame and sends the data in the converted frame in parallel one byte at a time, and is connected to the memory unit 2 and the pointer processing and demultiplexing unit 1 at the timing necessary for frame conversion. The memory unit 2 is provided with a counter unit 3 that supplies various pulses to be described later.

The illustrated pointer processing and demultiplexing unit 1
Is a terminal for outputting STM-1 / 3 demultiplexed from STM-1 in parallel for each byte (STM-1 /
3), POH placed at the beginning of the STM-1 frame
JI PLS that detects (J1) and shows its position
Output terminal, STM-1 / 3 SOH position and P
The destuff pulse (DSTF P for detecting the position of OH and preventing the pulse from being output to that position
LS) is output. JI PLS and DSTF PLS are given to the counter unit 3 together with 6M CLK, and the counter unit 3 tells the memory unit 2 that
A write pulse (hereinafter referred to as W CLK), a read pulse (hereinafter referred to as R CLK), and a pulse (hereinafter referred to as POH CLK) that defines the position of POH are supplied.

The memory portion is the above-mentioned STM-1 / 3, 6
M CLK, W CLK, R CLK, and POH C
Using LK, perform STM-1 / 3 frame conversion,
The converted data is output in 8-bit parallel.

The operation of FIG. 2 will be briefly described with reference to FIG. First, when the frame conversion circuit is activated by RST, when the STM-1 is input in this state, the pointer processing and demultiplexing unit 1 detects the SOH of the first to third columns of the STM-1. Then, during the period corresponding to these 3 bytes, the DSTF PLS is used for the counter unit 3
Give to. At this time, the counter unit 3 has 6M CL
K is given, and the period counter unit 3 of the first to third columns designated by the DSTF PLS does not perform the counter operation. As a result, W CLK is not supplied to the memory unit 2, and the memory unit 2 does not perform the SOH write operation during this period.

Further, in the example of FIG. 3, after the SOH arrives, VC is set in the 8th byte (that is, the 11th byte from the beginning).
-4 POH J1 is input. Therefore, 1
J1 PLS is output from the counter unit 3 to the memory unit 2 at the first byte. At the same time, the DSTF PLS is also output from the counter unit 3 to the memory unit 2. J1P
When receiving the LS, the counter unit 3 considers that the 2-byte period following J1 is the fixed stuff R period, and the W CLK is stored in the memory unit 2 for the fixed stuff R period.
Do not output to. Furthermore, in the example shown in FIG.
When the J1 placed at the beginning of the counter is detected, the counter unit 3 detects 1 / 29L PL every 29 bytes after detecting the J1.
S is output to the memory unit 2 to indicate the position of the fixed stuff R in the converted frame.

Data of STM-1 / 3 is written in the memory unit 2 in parallel as input data (8 bits), and is read according to R CLK as shown in FIG. As a result, a frame in which the fixed stuff R is arranged every 29 bytes from J1 positioned at the head of the converted POH is obtained.

The operation of the memory section 2 will be described in more detail with reference to FIG.

First, the pointer processing and demultiplexing unit 1 performs S
8 data signals having a bit rate of 6.48 Mb / S expanded in 8 parallel in the form of STM-1 / 3 obtained by demultiplexing TM-1 and a clock signal of 6.48 M (6
M CLK) is input to the memory unit 2. On the other hand, DST
F PLS (the SOH byte existing in STM-1 and the positive or negative stuff portion generated by the AU pointer are output as an active blow signal),
And J1 PLS are input to the counter unit 3. In the counter unit 3, as described above, the 1 / 29L PLS
Make PLS, DSTF PLS, J1 PL
W missing tooth with S, POH PLS, and 6M CLK
-Create CLK and R-CLK. Here, 1 / 29L
In PLS, the R position of the frame is 29 from POH
The byte and the next R have a relationship such as the position of the 29th byte from the previous position, and the acte blow signal is output to the POH and R portions.

Next, the memory section 2 is, as shown in FIG.
W CLK and POH PLS made by the counter unit 3
Write counter signal (W-COUNTER) from
Extend the number of bytes of input data expanded in parallel.
In addition, a read counter signal (R-COUNTER) is created by R CLK and POHPLS, and the extended data signal is extracted by this pulse signal, so that the position of R is exchanged and the frame of STM-1 / 3 of AU-3 + SOH is replaced. Can be converted to frames.

[0025]

As described above, according to the present invention, according to a certain positional relationship between POH and R,
By exchanging the position of R, it is possible to provide a frame conversion circuit capable of converting an STM-1 / 3 frame to an AU-3 + SOH frame.

Further, according to the present invention, it is possible to provide a synchronous digital transmission system capable of reducing the number of parts by using the frame conversion circuit. In the embodiment, the case of STM-1 / 3 has been described, but according to the experiments by the present inventors, it was confirmed that the frame conversion can be easily performed using the same method even with STM-1. ..

[Brief description of drawings]

FIG. 1 is an STM-frame-converted according to the present invention.
It is a figure which shows the structure of No. 1, and the frame structure after conversion.

FIG. 2 is a block diagram showing a frame conversion circuit according to an embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the counter unit used in the frame conversion circuit of FIG.

FIG. 4 is a timing chart for explaining the operation of the memory unit of the frame conversion circuit of FIG.

[Explanation of symbols]

 1 pointer processing and demultiplexing unit 2 memory unit 3 counter unit

Claims (3)

[Claims] 1. A first frame defined according to a protocol of a synchronous digital hierarchy (SDH) having a path overhead and a fixed stuff provided at a fixed position with respect to the path overhead, is defined as the synchronous digital hierarchy. Is a method of converting into a second frame defined by a protocol defined in a different network, the conversion is performed by replacing the position of the fixed stuff in the first frame with the position defined in the second frame. A frame conversion method characterized by the above. 2. The network according to claim 1, wherein the network is a Synchronous Optical Network.
k, hereinafter referred to as SONET). 3. An STM-N (Synchronous) defined in a predetermined synchronous digital hierarchy.
VC-4 (Virtual Co included in Transport Module-N)
In the circuit for converting the first frame of the ntainer 4) into the second frame including the VC-3 and the management unit (AU-3) defined in the synchronous optical transmission network, the memory unit and the counter unit are combined. By controlling the writing and reading of the memory unit by the counter, the position of the fixed stuff in the specific 3 columns following the path overhead of the VC-4 is set to the VC forming the AU-3.
-3 to the position of the fixed stuff in the second frame, VC-3 obtained by frame conversion AU-3
A frame conversion circuit, characterized in that the second frame is obtained by mapping to.