JP4239668B2 - Data memory control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data memory control system, and in particular, data that can reduce the storage capacity of a data memory composed of two surfaces necessary for the implementation of cross-connect when the cross-connect TSW function in SDH is realized by LSI. The present invention relates to a memory control method.
[0002]
[Prior art]
In recent years, with the advancement of integrated services for telephone, data, video and other electronic information (multi-media using broadband ISDN), the electronic information sent by information terminal users in the US, Europe, etc. can be obtained instantly while in Japan. It has become possible to do. For transmission and reception of this electronic information, a digital transmission method is employed in which high-speed data at different speeds is processed by a hierarchical structure (hierarchy).
[0003]
By the way, before the development of multimedia, PDH (Plesiochronous Digital Hierarchy) having different digital transmission systems existed in Japan, the United States, and Europe. This different PDH has been found to hinder the deployment of broadband ISDN based on a globally unified user network interface.
[0004]
Therefore, CCITT (current ITU, International Telecommunications Union) at that time standardized SDH (Synchronous Digital Hierarchy) as a user network interface in 1988 and made a recommendation in 1996 after various studies. Integrated into G.707.
Although there is SONET (Synchronous Optical Network) which has been studied as a North American standard, since it is almost the same technology as SDH, it is generally expressed as SONET / SDH.
[0005]
Here, prior to the description of the prior art according to the present invention, the technical features and concepts of SDH and the image of multiplexing will be described.
This explanation is based on “Easy-to-understand SDH / SONET transmission method” (Ohm, co-authored by Kasai, Kaoru, Tsuji, Ueda) and Recommendation G.707 (03/96) of ITU-T (Telecommunication Standardization Sector of ITU).
[0006]
The features of SDH can be summarized in the following three points.
(1) A synchronous interface that is unified throughout the world, and can handle both 1.5 Mbit / s and 2 Mbit / s systems existing in PDH on an equal basis, and enables multi-vendor communication devices. Further, since they are synchronized, the multiplexed information can be directly accessed without being separated at a low speed.
[0007]
{Circle around (2)} Various types of information can be flexibly multiplexed, and from voice information based on 64 kbit / s to high-speed data information can be multiplexed. Therefore, an infrastructure for realizing future broadband services can be constructed from the time of introduction.
[0008]
(3) An interface that is rich in operation and maintenance, and enables end-to-end online monitoring of multiplexed information. For this reason, it is possible to improve the function and quality of the network.
[0009]
FIG. 4A is a diagram showing a multiplexing structure standardized by ITU-T, and FIG. 4B is a diagram showing a TTC standard multiplexing structure used in Japan. Here, TTC (The Telecommunication Technology Committee) is a telecommunications technology committee, and establishes domestic standards in response to ITU international standard recommendations.
FIG. 5 is a diagram showing an image (concept) of multiplexing in SDH.
[0010]
As shown in FIGS. 4A and 4B, the multiplexing structures of the ITU-T standard and the TTC standard each have eight layers.
In this specification, “C-11 → VC-11 → TU-11 → TUG-2 → TUG-3 → VC-4 → AU-4 → AUG → STM-” from the lower right to the upper left of FIG. The case of passing through the N ”multiplexing route (route (1)) will be mainly described.
[0011]
Abbreviations such as VC-4 in the drawing will be described later as necessary.
In addition, AU and the like in the figure are shaded to indicate that a pointer operation (pointer processing) is being performed. The pointer can identify low-speed information in a high-speed signal and pass a frequency phase difference very efficiently, and is a major feature of SDH (described later).
[0012]
Mapping refers to accommodating multiplexed information in a VC (virtual container) (described later).
Aligning means accommodating a VC in a TU (Tributary Unit) (described later).
[0013]
FIG. 5 is a diagram illustrating a multiplexing format in SDH, taking as an example a case where “balls” corresponding to electronic information are put in a box and carried by “freight trains” corresponding to SOH.
FIG. 5 shows a case where information of 1.544 Mbit / s, which is a Japanese digital primary group signal, is multiplexed into STM-1 (described later).
[0014]
That is, from the lower right to the upper left in FIG. 4 (B), the route “C-11 → VC-11 → TU-11 → TUG-2 → VC-3 → AU-3 → AUG → STM-N” 2)). The difference between the route (1) and the route (2) is that VC-4 is replaced with VC-3 and TUG-3 is not required.
[0015]
As shown in FIG. 5, a ball (electronic information) is put in a box (container: C-11), a shipping slip (POH) is attached to each box to form a virtual container (VC-11), and the loading position on the pallet is determined. Display (TU-11) and bind the boxes with four strings (TUG-2).
[0016]
Then, four bundle boxes are stacked on 7 pallets (VC-3), a transportation slip is attached (POH), the loading position on the freight car is displayed (pointer), and the freight car is loaded (AU-3). Furthermore, with three freight cars connected (AUG), locomotives are connected (SOH) and carried to the destination (STM-1).
[0017]
Another significant feature of SDH is that it clearly incorporates the concept of layered transmission networks in the frame structure. As a result, network design and operation and maintenance can be hierarchized, and advanced network services can be provided.
[0018]
As shown in FIG. 6 (A), the transmission network is hierarchized, and the line network and the transmission system defined for the service are unaware of the path network independent of any service and the transmission medium for multiplexing the path network. It is divided into four layers, a section network and a transmission medium network composed of optical fibers and space.
[0019]
In SDH, as shown in FIG. 6B, the section network layer portion is defined as a section, and the path network layer path portion is defined as a high-order path and a low-order path. As a result, if the SDH transmission system is introduced, the operation and maintenance of the network will be advanced, which will have a great impact on the network business operation.
[0020]
Next, “VC-4 to AUG multiplexing” shown in FIGS. 4A and 4B and FIG. 5 will be described.
Here, VC is a virtual container (virtual container, virtual container), which is a standardized unit box (standardized transmission capacity unit) (see FIG. 5).
[0021]
Since this VC accommodates information with a margin, various types of information can be flexibly multiplexed. The multiplexing structure is all byte-multiplexed, and the transmission rate is an integral multiple of the basic rate.
As VCs, VC-4, VC-3, VC-2, VC-12, and VC-11 are defined corresponding to the speed of the accommodation information. There is also a container that collects an arbitrary number of VC-n.
[0022]
AU is an Administrative Unit, which is a box in which a management unit (AU) pointer is added to VC-3 or VC-4. Two types of AU-3 and AU-4 are defined.
An AU is an Administrative Unit Group, which is a single AU-4 or a multiplex of three AU-3s (see FIG. 5).
[0023]
FIG. 7A is a diagram showing a process of forming AU-4 from VC-4 and multiplexing to AUG, and FIG. 7B is a diagram showing a process of multiplexing from AUG to STM-N. .
As shown in FIGS. 7A and 7B, VC-4 is composed of 9 rows and 261 columns, and the first column is POH (Path Overhead).
[0024]
The POH is assigned at a generation point such as a VC-11 or VC-3 path defined as a path, and is stored up to a terminal point after information is transmitted. This ensures that when information is transferred in the network, the state of transmission information, such as a sign error, is monitored end to end, and advanced network operation and maintenance is possible.
[0025]
As shown in FIG. 7A, the higher-order path POH is located in the first column of VC-4, and bytes of J1, B3, C2, G1, F2, H4, F3, K3, and N1 are defined. The The byte position on the right side of the pointer byte is “0”, and an address is assigned for each byte.
[0026]
J1 is the first byte of the VC, and this position is indicated by the AU pointer. J1 is used to check whether the path setting is correct by transmitting a signal (API) having a specific pattern for each path generation point and checking the API at the end point of the path.
[0027]
J1 can be placed at any address 0 to 782 of the STM-1 signal (described later with reference to FIG. 8B). The address value (address) of the byte in which J1 is entered is converted into a binary value and is placed on H1 and H2 (position display).
[0028]
On the receiving side, the head position (position of J1) of VC-4 can be known (described later) by looking at the values of H1 and H2.
H1 and H2 are used for position indication with respect to the payload of the VC as described above.
A description of bytes other than J1 is omitted.
[0029]
VC-4 is accommodated in AU-4 having H1, H2, H3 bytes (pointers). The phase relationship between VC-4 and AU-4 is independent, and the phase relationship is given by a pointer. The pointer indicates the start position of VC-4 in AU-4. AU-4 becomes an AUG as it is.
[0030]
Next, “multiplexing from AUG to STM-N” shown in FIGS. 4A and 4B and FIG. 5 will be described.
ST M-N is Synchronous Transport Module-N. N indicates how many times the transmission rate (bit rate) is the basic STM-1, and is an integer. 1, 4, 16, and 64 are standardized as the value of N, and the basic speed (N = 1) is 155.52 Mbit / s.
[0031]
As shown in FIG. 7B, the AUG has a 1 row and 9 column protrusion on the 4th row of the 9 row and 261 column box. This protrusion is a pointer. AUG # 1, AUG # 2,..., AUG # N are byte-interleaved to form an STM-N of 9 rows and N × 261 columns.
The first N × 9 columns of the STM-N are SOH described below, among which the first to third rows are RSOH and the fifth to ninth rows are MSOH. In the fourth row, the pointers of AU-3 and AU-4 constituting each AUG are multiplexed.
[0032]
SOH is Section Overhead (section overhead), and has various operational functions such as a frame synchronization signal, a bit error detection code, an alarm state display, and transmission path switching control.
The SOH includes a relay SOH (RSOH) used between the intermediate relay devices or between the intermediate relay device and the terminal multiplex relay device, and the terminal relay multiplex intermediate relay device There are multiple SOH (MSOH) used between.
[0033]
FIG. 8A is a conceptual diagram of an STM-1 multiplexed frame, and FIG. 8B is a diagram showing an offset value of an AU-4 pointer.
As shown in FIG. 8A, the 1st to 9th columns are the SOH and the pointer, and the 9th row × 261th column after the 10th column is the payload. The payload contains main information (voice information, high-speed data, etc.).
[0034]
As shown in FIG. 8B, the address (offset value) is assigned to the payload of STM-1 from the byte next to the H3 byte. Addresses are assigned like “0, −, −, 2, −, −,..., 782, −, −” from the byte following the H3 byte. The address (offset value) where the J1 byte of VC-4 exists becomes the pointer value (see FIG. 11A). For example, when the J1 byte of VC-4 is located at the beginning of the first line of STM-1, the pointer value is 522.
[0035]
Next, the main topic of the prior art related to the present invention is entered.
In a SONET / SDH device for a user network interface manufactured based on Recommendation G.707, the cross-connect capacity has also increased with the recent increase in transmission capacity and diversification of device interfaces.
[0036]
Here, the SONET / SDH device is a notation of SONET and SDH, which are technologies that connect network nodes in a relay network between telecommunications carrier stations and multiplex-transmit data as described above. SONET and SDH are both technologies that synchronize between nodes and perform high-speed communication.
[0037]
Cross connect refers to a line setting technique that enables switching of time slots (ТS: a part for multiplexing information) in units of paths (line bundles) from multiplexed signals. Specifically, a technology for setting a line for each purpose, such as a line connected to an exchange, a line connected to a dedicated line transmission device, and a line that passes through the telephone station and is transmitted to another telephone station. Say.
[0038]
The cross-connect capacity is the total amount that can be cross-connected (line setting) during high-speed communication.
FIG. 9 is a diagram illustrating the positioning of the cross-connect device in SDH.
[0039]
Next, with reference to FIGS. 10A and 10B, the concept of the circuit configuration and processing in the case of performing cross-connect using TSW will be described. Here, TSW is a time switch (time division type switch), which is a switching circuit configured by hardware and firmware.
FIG. 10A is a block diagram of a conventional TSW, and FIG. 10B is a conceptual diagram of STM-1.
[0040]
10A and 10B, reference numeral 101 denotes a data memory having an area for one row of the serial STM-1 signal 110. The first surface 101a for writing and the second surface for reading. 101b. Reference numeral 102 denotes a write control circuit that performs write control of the STM-1 signal to the data memory 101.
[0041]
A control memory 103 stores an address for reading data from the data memory 101, and a read control circuit 104 reads the address from the control memory 103 and performs read control from the data memory 101.
110a is a payload, 110b is an RSOH (relay SOH), 110c is a management pointer (AUPТR), and 110d is an MSOH (multiple SOH).
[0042]
Next, cross connect in the data memory 101 will be described.
When sequentially writing one row of the STM-1 signal 110 to the data memory 101, as shown in FIG. 11A, it is assumed that the first byte (J1 byte) of VC-4 is at the position shown in the figure. In this case, since the J1 byte does not match the time slot (TS) in a single vertical column, the cross connect cannot be performed.
[0043]
Therefore, as shown in FIG. 11B, phase adjustment is performed so that the J1 byte is in the column adjacent to the SOH. One row of the phase-adjusted STM-1 signal 110 is sequentially written into the data memory 101. Then, the read control circuit 104 switches the order of reading data from the data memory 101 and performs cross-connect.
[0044]
[Problems to be solved by the invention]
However, when the cross-connect TSW function is realized by an LSI (integrated circuit) using the conventional technique, there are the following problems.
That is, in the SONET / SDH apparatus, the cross-connect capacity increases with an increase in interfaces, and the data memory capacity becomes enormous. As a result, there is a problem that the mounting space pattern wiring by H / W (hardware) and the control by F / W (firmware) become complicated.
[0045]
The present invention is considered in view of the above circumstances, and when the TSW function of the cross connect in SDH is realized by LSI, it is possible to reduce the storage capacity of the data memory consisting of two surfaces necessary for implementing the cross connect. A data memory control method is provided.
[0046]
[Means for Solving the Problems]
In order to achieve the above object, the first aspect of the present invention provides a first memory (data memory 11) comprising a first surface and a second surface for performing cross-connect processing on input data, and the first memory A second memory (control memory 17) for storing address data at the time of cross-connect processing in the memory, and a control means for controlling the cross-connect processing based on the address data stored in the second memory In the data memory control method,
The control means includes
Reference pulse extraction means (frame pulse extraction unit 12) for extracting a pulse serving as a reference at the time of cross-connect processing from the input data;
Based on the reference pulse extracted by the reference pulse extracting means, a first pulse train is generated for each number of pulses corresponding to the number of storage areas in each row of the first surface and the second surface in the first memory. Pulse generating means (720-ary counter 14);
Based on the reference pulse extracted by the reference pulse extracting means, second pulse generating means (1080 decimal counter 15) for generating a second pulse train for each number of pulses corresponding to the number of storage areas in one row in the second memory. When,
Third pulse generating means (binary counter 16) for generating a binary pulse based on the reference pulse extracted by the reference pulse extracting means;
The data obtained by equally dividing the second pulse train is configured to perform cross-connect processing corresponding to 0 or 1 of the binary pulse.
[0047]
In this way, for example, as shown in FIG. 2 and FIG. 3, the 1080 bytes of data stored in the second memory are equally divided according to the 0 or 1 level from the third pulse generating means. Since the data is sequentially stored on the first surface and the second surface of the first memory, the capacity of the first memory can be reduced.
[0048]
Next, the invention according to claim 2 is the data memory control system according to claim 1,
When the number of storage areas in one row of the second memory is P (integer), and the number of storage areas in each row of the first surface and the second surface of the first memory is Q (integer), P / Q is divisible.
In this way, a memory having a general storage area (for example, 720 bytes and 1080 bytes) can be used effectively without waste.
[0049]
Next, the invention according to claim 3 is the data memory control system according to claim 1 or 2, wherein
The input data is configured as an STM signal used for a SONET / SDH device.
[0050]
In this way, it is possible to reduce the memory capacity used for the STM signal cross-connect processing.
[0051]
Next, the invention according to claim 4 is the data memory control system according to any one of claims 1 to 3,
The STM signal is configured to be an STM-4 signal.
In this way, the memory capacity used for the STM-4 signal cross-connect process can be reduced.
[0052]
Next, the invention according to claim 5 is the data memory control system according to any one of claims 1 to 4,
The number of storage areas of the first and second surfaces of the first memory is 720 bytes, and the number of storage areas of the second memory is 1080 bytes.
[0053]
In this way, the number of storage areas of the first and second surfaces of the conventional first memory is 1080 bytes, but according to the present invention, it can be reduced to 720 bytes. However, a memory capacity of 2/3 is sufficient.
[0054]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on the illustrated embodiments.
FIG. 1 is a block diagram of the present embodiment, FIG. 2 is a time chart of cross-connect implementation in TSW, and FIG. 3 is a conceptual diagram of cross-connect implementation.
[0055]
In the present embodiment, a TSW operation for converting the STM-4 signal into 8 bits in parallel is performed. This STM-4 signal is a multiplexed transmission system in which a bit string to be transmitted is divided into frames of a certain length and is periodically repeated. The signal of one channel is transmitted at the same bit position or time / time in the frame. It is a method of carrying by slot (ТS).
[0056]
As shown in FIG. 1, the input STM-4 signal is input to the data memory 11 via an S / P (serial / parallel conversion) unit 13 and directly input to the frame pulse extraction unit 12.
The data memory 11 includes a first surface 11a for writing and a second surface 11b for reading, and each has a memory area of 720 bytes.
[0057]
As shown in FIGS. 11A and 11B, the S / P unit 13 converts the input STM-4 signal into the first byte (J1 byte) of VC-4 / 3 of the payload as RSOH, MSOH. The phase is adjusted so as to come to the next column, and converted into 8-bit parallel data and output to the data memory 11.
[0058]
The frame pulse extraction unit 12 outputs a 4 KHz frame pulse obtained by dividing an 8 kHz frame extracted from one frame of the STM-4 signal by 2 to the 720-ary counter 14, the 1080-ary counter 15, and the binary counter 16, respectively.
[0059]
The 720-ary counter 14 outputs a sequential address for writing the 8-bit parallel data from the S / P unit 13 to the data memory 11 to the data memory 11 (see symbol A in FIG. 2).
[0060]
The 1080 base counter 15 outputs a 1080 base counter value to the control memory 17 (see reference B in FIG. 2).
The binary counter 16 outputs a binary counter value to the calculation unit 18 (see reference C in FIG. 2).
The control memory 17 outputs the data in the control memory 17 to the arithmetic unit 18 using the counter value from the 1080-count counter 15 as an address.
[0061]
The calculation unit 18 outputs a read address to the data memory 11 based on information from the control memory 17 and the binary counter 16.
The data memory 11 outputs the read address data from the calculation unit 18 to a P / S (parallel / serial conversion) unit 19.
The P / S unit 19 converts the 8-bit parallel data from the data memory 11 into 622.08 MHz serial data and outputs an STM-4 signal.
[0062]
Next, the operation of this embodiment will be described.
In this embodiment, the control memory 17 has an area of two-thirds of one row (720 bytes with respect to 1080 bytes), and the data memory 11 includes the first surface 11a and the second surface 11b. A TSW operation for one cycle is performed.
[0063]
That is, in the case of the STM-4 signal, since one row is 1080 bytes, the conventional data memory requires 1080 bytes, but according to this embodiment, the TSW operation is performed even with 720 bytes in the two-thirds area. Can be realized.
[0064]
The frame pulse extraction unit 12 performs frame synchronization of the input STM-4 signal and extracts an 8 KHz frame. Since the STM-N frame has 9 rows, in this embodiment, the TSW operation has one cycle of 2 rows as described above. Therefore, the 720-decimal counter 14, the 1080-decimal counter 15, and the binary counter 16 are set to 8 KHz pulses. Can not be loaded with. For this reason, an 8 KHz frame is loaded with a 4 KHz pulse obtained by further dividing the frequency by 2 in a free run.
[0065]
The 720-ary counter 14 outputs a counter value (every 720 frame pulses) as a sequential address for writing data from the S / P unit 13 to the data memory 11 (see symbol A in FIG. 2).
The 1080-adic counter 15 outputs an address for every 1080 frame pulses to the control memory 17 having cross-connect information (data memory read address for one row) for one row, and the control memory 17 reads the data memory. Output address (see symbol B in FIG. 2).
[0066]
The binary counter 16 outputs the count value to the calculation unit 18 at an 8 KHz cycle.
The arithmetic unit 18 converts the data memory read address for one row from the control memory 17 and the counter value from the binary counter 16 into a data memory read address and outputs the data memory 11 to the data memory 11.
[0067]
The data memory 11 outputs the data to the P / S unit 19 in accordance with the converted read address from the arithmetic unit 18, and the P / S unit 19 converts the 8-bit parallel data into 622.08 MHz serial data. 4 signals are output.
[0068]
Next, a calculation method in the calculation unit 18 will be described with reference to FIGS.
<When the binary counter is 0> (see symbol C in FIG. 2)
If the number of frame pulses is “0 to 359”, it is recognized as “area 1”, and the address data read from the control memory 17 is output as it is as the read address of the data memory 11.
[0069]
If the number of frame pulses is “360 to 719”, it is recognized as “area 2”, and the address data read from the control memory 17 is output as it is as the read address of the data memory 11.
If the number of frame pulses is 720-1079, it is recognized as “area 3”, and a calculation result of minus 720 is output from the address data read from the control memory 17 as the read address of the data memory 11.
[0070]
<When binary counter is 1>
If the number of frame pulses is “0 to 359”, it is recognized as “area 4”, and a calculation result of plus 360 is output from the address data read from the control memory 17 as the read address of the data memory 11.
[0071]
If the number of frame pulses is “360 to 719”, it is recognized as “area 5”, and a calculation result of plus 360 is output from the address data read from the control memory 17 as the read address of the data memory 11.
[0072]
If the number of frame pulses is 720 to 1079, it is recognized as “area 6” and is output as it is from the address data read from the control memory 17 as the read address of the data memory 11.
[0073]
In this way, as shown in FIG. 3, the 1080 bytes of address data stored in the 1080 bytes of the control memory 17 are written into the two-byte data memory 11 (11a, 11b) of 720 bytes. It becomes possible. Therefore, while the conventional data memory capacity is 1080 bytes, according to the present embodiment, the data memory capacity is 720 bytes, and 720 bytes are necessary.
[0074]
In this embodiment, the case of STM signal cross-connecting has been described. However, parallel data is input to a first memory (data memory) having two surfaces and an address stored in the second memory (control memory). Needless to say, it can be used as means for reducing the capacity of the first memory when it is stored in the first memory based on data.
[0075]
【The invention's effect】
As described above, according to the present invention, the following effects can be exhibited.
According to the first aspect of the present invention, for example, as shown in FIG. 2 and FIG. 3, the 1080 bytes of data stored in the second memory are equally divided, and 0 or 1 from the third pulse generating means is obtained. Since the data is sequentially stored in the first and second surfaces of the first memory according to the level, the capacity of the first memory can be reduced.
[0076]
According to the second aspect of the present invention, a memory having a general storage area (for example, 720 bytes and 1080 bytes) can be used effectively without waste.
According to the third aspect of the present invention, the capacity of the memory used for the STM signal cross-connect process can be reduced.
[0077]
According to the fourth aspect of the present invention, the memory capacity used for the STM-4 signal cross-connect processing can be reduced.
According to the invention described in claim 5, the number of storage areas on the first and second surfaces of the conventional first memory is 1080 bytes, but according to the present invention, it is possible to suffice with 720 bytes. Compared to the conventional example, a memory capacity of 2/3 is sufficient.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a data processing time chart in the embodiment;
FIG. 3 is a diagram illustrating a concept of data processing in the embodiment.
4A and 4B are diagrams for explaining the prior art, in which FIG. 4A shows a multiplexing structure standardized by ITU-T, and FIG. 4B shows multiplexing of a TTC standard used in Japan. It is a figure which shows a structure.
FIG. 5 is a diagram illustrating a multiplexing format in SDH, taking as an example a case where “apples” corresponding to electronic information are put in a box and transported by “freight trains” corresponding to SOH.
6A is a diagram showing the hierarchization of a transmission network, and FIG. 6B is a diagram showing the positioning of sections and paths in SDH.
7A is a diagram showing a process of forming AU-4 from VC-4 and multiplexing to AUG, and FIG. 7B is a diagram showing a process of multiplexing from AUG to STM-N. .
8A is a conceptual diagram of an STM-1 multiplexed frame, and FIG. 8B is a diagram illustrating an offset value of an AU-4 pointer.
FIG. 9 is a diagram showing the positioning of the cross-connect device in SDH.
10A is a block diagram for implementing TSW, and FIG. 10B is a conceptual diagram of STM-1.
11A and 11B are diagrams for explaining phase adjustment, in which FIG. 11A shows the position of the first byte (J1 byte) before phase adjustment, and FIG. 11B shows the position of the first byte (J1 byte) after phase adjustment; FIG.
[Explanation of symbols]
11 Data memory
11a First aspect of data memory
11b Second side of data memory
12 Frame pulse extractor
13 S / P section
14 720 base counter
15 1080 decimal counter
16 Binary counter
17 Control memory
18 Calculation unit
19 P / S part

Claims (5)

A first memory having a first surface and a second surface for performing cross-connect processing on input data; a second memory for storing address data at the time of cross-connect processing in the first memory; In a data memory control system comprising control means for controlling the cross-connect process based on address data stored in a second memory,
The control means includes
Reference pulse extraction means for extracting a pulse serving as a reference at the time of cross-connect processing from the input data;
Based on the reference pulse extracted by the reference pulse extracting means, a first pulse train is generated for each number of pulses corresponding to the number of storage areas in each row of the first surface and the second surface in the first memory. Pulse generating means;
Second pulse generating means for generating a second pulse train for each number of pulses corresponding to the number of storage areas in one row in the second memory, based on the reference pulse extracted by the reference pulse extracting means;
A third pulse generating means for generating a binary pulse based on the reference pulse extracted by the reference pulse extracting means;
A data memory control system, wherein data obtained by equally dividing the second pulse train is subjected to cross-connect processing corresponding to 0 or 1 of the binary pulse. The data memory control system according to claim 1, wherein
When the number of storage areas in one row of the second memory is P (integer), and the number of storage areas in each row of the first surface and the second surface of the first memory is Q (integer), A data memory control system characterized in that P / Q is divisible. In the data memory control system according to claim 1 or 2,
A data memory control system, wherein the input data is an STM signal used for a SONET / SDH device. In the data memory control system according to any one of claims 1 to 3,
The data memory control system, wherein the STM signal is an STM-4 signal. In the data memory control system according to any one of claims 1 to 4,
A data memory control system, wherein the number of storage areas of the first and second surfaces of the first memory is 720 bytes, and the number of storage areas of the second memory is 1080 bytes.

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