JP2004336391A - Data memory control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data memory control system capable of reducing the storage capacity of a data memory composed of two surfaces required for the performance of cross-connection. <P>SOLUTION: The data memory control system is provided with a means 12 for extracting a reference pulse at the time of cross-connection processing from input data, a means 14 for generating a first pulse train for every number of pulses equivalent to the number of storage areas of each row of a first surface and a second surface in a first memory on the basis of the extracted reference pulse, a means 15 for generating a second pulse train for every number of the pulses equivalent to the number of the storage areas of one row in a second memory on the basis of the extracted reference pulse, and a means 16 for generating binary pulses on the basis of the extracted reference pulse. Data for which the second pulse train is equally divided are made to correspond to 0 or 1 of binary pulses and the cross-connection processing is performed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data memory control method, and more particularly to a data memory control method capable of reducing the storage capacity of a two-sided data memory required for implementing a cross connect when a cross connect TSW function in SDH is realized by an LSI. It relates to a memory control method.
[0002]
[Prior art]
In recent years, with the development of integrated services of electronic information such as telephone, data, and video (multimedia by broadband ISDN), the electronic information transmitted by information terminal users in the United States, Europe, etc. can be obtained instantly while in Japan. Is becoming possible. For transmission and reception of the electronic information, a digital transmission system for processing high-speed data of different speeds in a hierarchical structure (hierarchy) is employed.
[0003]
By the way, before the advance of multimedia, there were PDH (Plesiochronous Digital Hierarchy) in which digital transmission systems were different from each other in Japan, the United States and Europe. This different PDH has been found to hinder the deployment of broadband ISDN based on a globally unified user network interface.
[0004]
At that time, CCITT (now ITU, International Telecommunication Union) standardized SDH (Synchronous Digital Hierarchy) as a user network interface in 1988, and after various studies, made a recommendation in 1996. G. FIG. 707.
Although there is SONET (Synchronous Optical Network: Optical Synchronous Transmission Network) which has been studied as a North American standard, it is generally described as SONET / SDH because it is almost the same technology as SDH.
[0005]
Here, prior to the description of the prior art related to the present invention, the technical features and concept of SDH and an image of multiplexing will be described.
Note that this description is based on the recommendation G. of “Easy-to-understand SDH / SONET Transmission System” (Ohm Co., Kasai, Maki, Tsuji, Ueda) and ITU-T (Telecommunication Standardization Sector of ITU). 707 (03/96).
[0006]
The features of SDH can be summarized into the following three points.
{Circle around (1)} A globally unified synchronous interface that can handle both 1.5 Mbit / s and 2 Mbit / s information existing in the PDH on an equal basis, and enables multi-vendor communication devices. Further, since the information is synchronized, the multiplexed information can be directly accessed without being separated at a low speed.
[0007]
(2) Flexible multiplexing of various types of information is possible, and it is possible to multiplex from audio information based on 64 kbit / s to high-speed data information. Therefore, an infrastructure for realizing a broadband service in the future can be constructed from the time of introduction.
[0008]
(3) This interface is rich in operation and maintenance, and enables end-to-end online monitoring of multiplexed information. For this reason, the function and quality of the network can be improved.
[0009]
FIG. 4A is a diagram illustrating a multiplexing structure standardized by ITU-T, and FIG. 4B is a diagram illustrating a multiplexing structure of a TTC standard used in Japan. Here, the TTC (The Telecommunications Technology Committee) is a telecommunications technical committee, and establishes standards in Japan in response to ITU international standard recommendations.
FIG. 5 is a diagram showing an image (concept) of multiplexing in SDH.
[0010]
As shown in FIGS. 4A and 4B, the multiplexing structure of the ITU-T standard and the TTC standard each include eight layers.
In this specification, from the lower right to the upper left of FIG. 4A, “C-11 → VC-11 → TU-11 → TUG-2 → TUG-3 → VC-4 → AU-4 → AUG → STM- The case of passing through the multiplexing path (path (1)) of "N" will be mainly described.
[0011]
Abbreviations such as VC-4 in the figure will be described later as necessary.
Also, AUs and the like in the figure are hatched to indicate that a pointer operation (pointer processing) is being performed. The pointer can identify the low-speed information in the high-speed signal and pass the frequency phase difference very efficiently, which is one of the major features of the SDH (described later).
[0012]
Mapping refers to storing information to be multiplexed in a VC (virtual container) (described later).
Aligning refers to accommodating a VC in a TU (tributary unit) (described later).
[0013]
FIG. 5 is a diagram illustrating an example of a multiplex format in SDH in which a “ball” corresponding to electronic information is put in a box and carried by a “freight train” corresponding to an SOH.
FIG. 5 shows a case where information of 1.544 Mbit / s, which is a digital primary group signal in Japan, is multiplexed into STM-1 (described later).
[0014]
That is, from the lower right to the upper left in FIG. 4B, the route of “C-11 → VC-11 → TU-11 → TUG-2 → VC-3 → AU-3 → AUG → STM-N” (route ▲ 2)). The difference between the route (1) and the route (2) is that VC-4 is replaced with VC-3 and TUG-3 is not required.
[0015]
As shown in FIG. 5, a ball (electronic information) is put in a box (container: C-11), and a shipping slip (POH) is attached to each box to form a virtual container (VC-11). It is displayed (TU-11), and the boxes are bundled with four strings (TUG-2).
[0016]
Then, the boxes of four bundles are stacked on seven pallets (VC-3), a transportation slip is attached (POH), the position of loading on the freight car is displayed (pointer), and the freight car is loaded on the freight car (AU-3). Further, with three wagons connected (AUG), the locomotive is connected (SOH) and transported to the destination (STM-1).
[0017]
Another major feature of SDH is that the concept of layering the transmission network has been clearly incorporated into the frame structure. As a result, network design and operation and maintenance can be hierarchized, and advanced network services can be provided.
[0018]
As shown in FIG. 6A, the transmission network is hierarchized, and the transmission network is not aware of a path network independent of any service and a transmission medium for multiplexing the path network, as shown in FIG. It is divided into four layers: a section network and a transmission medium network composed of optical fibers and spaces.
[0019]
In the SDH, as shown in FIG. 6B, the section of the section network layer is defined as a section, and the path of the path network layer is defined as a higher-order path and a lower-order path. As a result, if the SDH transmission system is introduced, the operation and maintenance of the network will be advanced, which will have a great impact on the operation of the network business.
[0020]
Next, "multiplexing from VC-4 to AUG" shown in FIGS. 4A, 4B and 5 will be described.
Here, VC is a virtual container (virtual container), and is a box of standardized multiplexing units (units of standardized transmission capacity) (see FIG. 5).
[0021]
Since this VC accommodates information with a margin, it allows flexible multiplexing of various types of information, and all multiplexing structures are byte multiplexed, and the transmission speed is an integral multiple of the basic speed.
As the VC, VC-4, VC-3, VC-2, VC-12, and VC-11 are defined corresponding to the speed of the accommodation information. Note that there is a container in which an arbitrary number of VC-n are collected.
[0022]
The AU is an administrative unit (management unit), which is a box in which a management unit (AU) pointer is added to the VC-3 or VC-4. Two types, AU-3 and AU-4, are defined.
The AUG is an administrative unit group (management unit group), which is obtained by multiplexing one AU-4 or three AU-3s (see FIG. 5).
[0023]
FIG. 7A is a diagram showing a process of forming AU-4 from VC-4 and multiplexing to AUG, and FIG. 7B is a diagram showing a process of multiplexing AUG to STM-N. .
As shown in FIGS. 7A and 7B, VC-4 is composed of 9 rows and 261 columns, and the first column is a POH (Path Overhead: path overhead).
[0024]
The POH is given at a generation point such as a VC-11 or VC-3 path defined as a path, and is stored up to a terminal point after information is transmitted. This ensures that when information is transferred in the network, the state of the transmission information, such as a code error, is monitored end-to-end, thereby enabling advanced network operation and maintenance.
[0025]
As shown in FIG. 7A, the POH of the higher order path is located in the first column of VC-4, and bytes J1, B3, C2, G1, F2, H4, F3, K3, and N1 are defined. You. The byte position on the right of the pointer byte is "0", and an address is assigned for each byte.
[0026]
J1 is the first byte of the VC, the location of which is indicated by the AU pointer. J1 transmits a signal (API) having a specific pattern for each path generation point, and is used to check whether the path setting is correct by checking the API at the end point of the path.
[0027]
J1 can be placed at any of the addresses 0 to 782 of the STM-1 signal (described later using FIG. 8B). The address value (address) of the byte in which J1 is inserted is converted into a binary value and placed on H1 and H2 (position display).
[0028]
On the receiving side, the head position of VC-4 (the position of J1) can be known by checking the values of H1 and H2 (described later).
H1 and H2 are used for position indication with respect to the payload of the VC as described above.
The description of the bytes other than J1 is omitted.
[0029]
VC-4 is accommodated in AU-4 having H1, H2, and H3 bytes (pointer). The phase relationship between VC-4 and AU-4 is independent, and the phase relationship is given by a pointer. The pointer indicates the head position of VC-4 in AU-4. AU-4 becomes AUG as it is.
[0030]
Next, "multiplexing from AUG to STM-N" shown in FIGS. 4A, 4B and 5 will be described.
S @ M-N is a Synchronous Transport Module (synchronous transfer module) -N. N indicates how many times the transmission speed (bit rate) of the basic STM-1 is, and is an integer. 1, 4, 16, and 64 are standardized as the value of N, and the basic speed (N = 1) is 155.52 Mbit / s.
[0031]
As shown in FIG. 7B, in the AUG, a box of 9 rows and 261 columns has a protrusion of 1 row and 9 columns on the fourth row. This ledge is the pointer. AUG # 1, AUG # 2,..., AUG # N are byte-interleaved to form an STM-N of 9 rows and N × 261 columns.
The first N × 9 columns of the STM-N are SOHs described below, of which the first to third rows are RSOH and the fifth to ninth rows are MSOH. On the fourth line, pointers of AU-3 and AU-4 constituting each AUG are multiplexed.
[0032]
The SOH is a section overhead (section overhead), and has various operational functions such as a frame synchronization signal, a bit error detection code, an alarm generation state display, and a transmission line switching control.
The SOH includes a relay SOH (RSOH) used between intermediate repeaters or between an intermediate repeater and a terminal multiplex repeater, and a terminal multiplex intermediate repeater / intermediate repeater without any processing in the intermediate repeater. There is multiple SOH (MSOH) used between.
[0033]
FIG. 8A is a conceptual diagram of an STM-1 multiplexed frame, and FIG. 8B is a diagram showing an offset value of an AU-4 pointer.
As shown in FIG. 8A, the 1st to 9th columns are the SOH and the pointer, and the 9th row × 261 columns after the 10th column are the payload. The payload contains main information (voice information, high-speed data, etc.).
[0034]
As shown in FIG. 8B, an address (offset value) is assigned to the STM-1 payload from the byte next to the H3 byte. Addresses are assigned from the byte next to the H3 byte as "0,-,-, 2,-,-, ..., 782,-,-". The address (offset value) where the J1 byte of VC-4 exists becomes the pointer value (see FIG. 11A). For example, when the J1 byte of VC-4 is located at the beginning of the first line of STM-1, the pointer value is 522.
[0035]
Next, the main point of the prior art related to the present invention will be described.
Recommendation G. In a SONET / SDH device for a user network interface manufactured based on 707, the cross-connect capacity has increased with the recent increase in transmission capacity and diversification of device interfaces.
[0036]
Here, the SONET / SDH apparatus is mainly referred to as SONET and SDH, which is a technology for connecting network nodes in a relay network between stations of a communication carrier and for multiplexing data as described above. SONET and SDH are both technologies that synchronize between nodes and perform high-speed communication.
[0037]
The cross-connect refers to a line setting technique that enables the exchange of time slots (： S: a part for multiplexing information) in units of paths (line bundles) from multiplexed signals. Specifically, there is a technology for setting a line for each purpose, such as a line connected to an exchange, a line connected to a dedicated line transmission device, and a line that passes through the central office and is transmitted to another central office. Say.
[0038]
The cross-connect capacity refers to the total amount of cross-connect (line setting) that can be performed during high-speed communication.
FIG. 9 is a diagram illustrating the positioning of the cross-connect device in the SDH.
[0039]
Next, with reference to FIGS. 10A and 10B, a description will be given of a circuit configuration and a concept of processing in a case where cross-connect is performed using the TSW. Here, the TSW is a time switch (time division switch), and is a switching circuit configured by hardware and firmware.
FIG. 10A is a block diagram of a conventional TSW, and FIG. 10B is a conceptual diagram of STM-1.
[0040]
In FIGS. 10A and 10B, reference numeral 101 denotes a data memory having an area for one row of the serial-type STM-1 signal 110, a first surface 101a for writing and a second surface for reading. 101b. Reference numeral 102 denotes a write control circuit that controls writing of the STM-1 signal to the data memory 101.
[0041]
A control memory 103 stores an address for reading data from the data memory 101, and a read control circuit 104 reads the address from the control memory 103 and controls reading from the data memory 101.
110a is the payload, 110b is the RSOH (relay SOH), 110c is the management pointer (AUP @ R), and 110d is the MSOH (multiple SOH).
[0042]
Next, a cross connect in the data memory 101 will be described.
When one row of the STM-1 signal 110 is sequentially written to the data memory 101, it is assumed that the first byte (J1 byte) of the VC-4 is at the illustrated position as shown in FIG. In this case, since the J1 byte does not match a vertically aligned time slot (TS), cross-connect cannot be performed.
[0043]
Therefore, as shown in FIG. 11B, the phase is adjusted so that the J1 byte comes in the column next to the SOH. One row of the phase-adjusted STM-1 signal 110 is sequentially written to the data memory 101. Then, the read control circuit 104 switches the order of reading data from the data memory 101 to perform cross-connect.
[0044]
[Problems to be solved by the invention]
However, when the cross-connect TSW function is realized by an LSI (integrated circuit) using the conventional technology, there are the following problems.
That is, in the SONET / SDH apparatus, the cross-connect capacity increases as the number of interfaces increases, and the capacity of the data memory becomes enormous. As a result, there is a problem that mounting space pattern wiring by H / W (hardware) and control by F / W (firmware) become complicated.
[0045]
The present invention has been made in view of the above circumstances, and when the TSW function of the cross connect in SDH is realized by an LSI, it is possible to reduce the storage capacity of the two-sided data memory required for performing the cross connect. A data memory control method is provided.
[0046]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 includes a first memory (data memory 11) having a first surface and a second surface for performing cross-connect processing on input data; A second memory (control memory 17) for storing address data at the time of cross-connect processing in the memory; and control means for controlling the cross-connect processing based on the address data stored in the second memory. In the data memory control method,
The control means,
A reference pulse extracting unit (frame pulse extracting unit 12) for extracting a pulse serving as a reference at the time of cross-connect processing from the input data;
A first pulse train for generating a first pulse train for each pulse number corresponding to the number of storage areas in each row of the first surface and the second surface in the first memory, based on the reference pulse extracted by the reference pulse extracting means. Pulse generating means (720-base counter 14);
A second pulse generating means (1080 base counter 15) for generating a second pulse train for each pulse number corresponding to the number of storage areas in one row in the second memory based on the reference pulse extracted by the reference pulse extracting means; When,
A third pulse generator (binary counter 16) for generating a binary pulse based on the reference pulse extracted by the reference pulse extractor;
The data obtained by equally dividing the second pulse train is subjected to cross-connect processing in correspondence with 0 or 1 of the binary pulse.
[0047]
In this way, for example, as shown in FIGS. 2 and 3, the 1080-byte data stored in the second memory is equally divided, and according to the level of 0 or 1 from the third pulse generating means. Since the data is sequentially stored on the first surface and the second surface of the first memory, the capacity of the first memory can be reduced.
[0048]
Next, according to a second aspect of the present invention, in the data memory control method according to the first aspect,
When the number of storage areas in one row of the second memory is P (integer) and the number of storage areas in each row of the first and second faces of the first memory is Q (integer), P / Q has a divisible configuration.
In this way, a memory having a general storage area (for example, 720 bytes and 1080 bytes) can be used effectively without waste.
[0049]
Next, a third aspect of the present invention is the data memory control system according to the first or second aspect,
The input data is an STM signal used for a SONET / SDH device.
[0050]
In this way, the capacity of the memory used for the STM signal cross-connect processing can be reduced.
[0051]
Next, according to a fourth aspect of the present invention, in the data memory control system according to any one of the first to third aspects,
The STM signal is an STM-4 signal.
By doing so, the memory capacity used for the cross-connect processing of the STM-4 signal can be reduced.
[0052]
Next, according to a fifth aspect of the present invention, in the data memory control system according to any one of the first to fourth aspects,
The number of storage areas on the first and second sides of the first memory is 720 bytes, and the number of storage areas on the second memory is 1080 bytes.
[0053]
By doing so, the number of storage areas on the first side and the second side of the conventional first memory is 1080 bytes, but according to the present invention, it can be reduced to 720 bytes. Only 2/3 of the memory capacity is required.
[0054]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described based on the illustrated embodiments.
FIG. 1 is a block diagram of the present embodiment, FIG. 2 is a time chart of the cross-connect implementation in the TSW, and FIG. 3 is a conceptual diagram of the cross-connect implementation.
[0055]
In the present embodiment, a TSW operation for parallel-converting an STM-4 signal into 8 bits is performed. The STM-4 signal is a multiplex transmission system in which a bit sequence to be transmitted is divided into frames of a fixed length and periodically repeated, and a signal of one channel is transmitted at the same bit position or time in a frame. This is a method of carrying by slot ($ S).
[0056]
As shown in FIG. 1, the input STM-4 signal is input to a data memory 11 via an S / P (serial / parallel conversion) unit 13 and directly to a frame pulse extraction unit 12.
The data memory 11 includes a first surface 11a for writing and a second surface 11b for reading, and each has a memory area of 720 bytes.
[0057]
The S / P unit 13 converts the input STM-4 signal into the first byte (J1 byte) of the VC-4 / 3 of the payload, as shown in FIGS. 11A and 11B, by using RSOH and MSOH. Is adjusted so as to be in the column next to, converted into 8-bit parallel data, and output to the data memory 11.
[0058]
The frame pulse extraction unit 12 outputs a 4 kHz frame pulse obtained by dividing an 8 kHz frame extracted from one frame of the STM-4 signal by 2 to the 720-decimal counter 14, the 1080-decimal counter 15, and the binary counter 16, respectively.
[0059]
The 720-decimal counter 14 outputs, to the data memory 11, a sequential address for writing 8-bit parallel data from the S / P unit 13 to the data memory 11 (see reference numeral A in FIG. 2).
[0060]
The 1080-decimal counter 15 outputs a 1080-decimal counter value to the control memory 17 (see reference numeral B in FIG. 2).
The binary counter 16 outputs a binary counter value to the calculation unit 18 (see reference numeral C in FIG. 2).
The control memory 17 outputs the data of the control memory 17 to the arithmetic unit 18 using the counter value from the 1080-base counter 15 as an address.
[0061]
The operation unit 18 outputs a read address to the data memory 11 based on information from the control memory 17 and the binary counter 16.
The data memory 11 outputs the data of the read address from the arithmetic unit 18 to a P / S (parallel / serial conversion) unit 19.
The P / S unit 19 converts the 8-bit parallel data from the data memory 11 into 622.08 MHz serial data and outputs an STM-4 signal.
[0062]
Next, the operation of the present embodiment will be described.
In the present embodiment, the control memory 17 has an area of two-thirds of one row (720 bytes for 1080 bytes) and the data memory 11 has the first surface 11a and the second surface 11b. A TSW operation for one cycle is performed.
[0063]
That is, in the case of the STM-4 signal, one row is 1080 bytes, and therefore, the conventional data memory requires 1080 bytes. However, according to the present embodiment, the TSW operation is performed even with 720 bytes in the two-thirds area. Can be realized.
[0064]
The frame pulse extraction unit 12 synchronizes the input STM-4 signal with a frame and extracts an 8 KHz frame. Since the STM-N frame has nine rows, in this embodiment, the TSW operation is performed in one cycle with two rows as described above. Therefore, the 720-decimal counter 14, the 1080-decimal counter 15, and the binary counter 16 are set to a pulse of 8 KHz. Can not be loaded with Therefore, an 8 KHz frame is loaded with a 4 KHz pulse obtained by further dividing the frequency by 2 in free-run.
[0065]
The 720-decimal counter 14 outputs a counter value (for each 720 frame pulse) as a sequential address for writing data from the S / P unit 13 to the data memory 11 (see reference sign A in FIG. 2).
The 1080-decimal counter 15 outputs an address for each 1080 frame pulse to the control memory 17 having the cross-connect information for one row (data memory read address for one row), and the control memory 17 reads the data memory. The address for use is output (see B in FIG. 2).
[0066]
The binary counter 16 outputs a count value to the calculation unit 18 at a period of 8 KHz.
The operation unit 18 converts the data memory read address for one row from the control memory 17 and the counter value from the binary counter 16 into a data memory read address, and outputs it to the data memory 11.
[0067]
The data memory 11 outputs the data to the P / S unit 19 based on the converted read address from the arithmetic unit 18, and the P / S unit 19 converts the 8-bit parallel data into 622.08 MHz serial data. −4 signal is output.
[0068]
Next, a calculation method in the calculation unit 18 will be described with reference to FIGS.
<When the binary counter is 0> (see symbol C in FIG. 2)
If the number of frame pulses is “0 to 359”, it is recognized as “area 1”, and the address data read from the control memory 17 is directly output as the read address of the data memory 11.
[0069]
If the number of frame pulses is “360 to 719”, it is recognized as “area 2”, and the address data read from the control memory 17 is directly output as the read address of the data memory 11.
If the number of frame pulses is 720 to 1079, the area is recognized as “area 3”, and a calculation result of minus 720 is output from the address data read from the control memory 17 as a read address of the data memory 11.
[0070]
<When the binary counter is 1>
If the number of frame pulses is “0 to 359”, it is recognized as “area 4”, and as a read address of the data memory 11, a calculation result of plus 360 is output from the address data read from the control memory 17.
[0071]
If the number of frame pulses is “360 to 719”, it is recognized as “area 5”, and as a read address of the data memory 11, a calculation result of plus 360 is output from the address data read from the control memory 17.
[0072]
If the number of frame pulses is 720 to 1079, it is recognized as “area 6”, and is output as it is from the address data read from the control memory 17 as a read address of the data memory 11.
[0073]
In this way, as shown in FIG. 3, the 1080-byte address data of one row stored in the 1080-byte control memory 17 is written to the 720-byte two-sided data memory 11 (11a, 11b). It becomes possible. Therefore, according to the present embodiment, the data memory capacity is only 720 bytes, whereas the conventional data memory capacity is 1080 bytes, and 720 bytes are required.
[0074]
In this embodiment, the case of the cross connection of the STM signal has been described. However, the parallel data is input to the first memory (data memory) composed of two planes and the address stored in the second memory (control memory). Of course, when data is stored in the first memory based on data, it can be used as a means for reducing the capacity of the first memory.
[0075]
【The invention's effect】
As described above, according to the present invention, the following effects can be exerted.
According to the first aspect of the present invention, for example, as shown in FIGS. 2 and 3, the 1080-byte data stored in the second memory is equally divided, and the 0 or 1 signal from the third pulse generating means is divided into 0 and 1 bits. Since the data is sequentially stored on the first surface and the second surface of the first memory according to the level, the capacity of the first memory can be reduced.
[0076]
According to the second aspect of the present invention, a memory having a general storage area (for example, 720 bytes and 1080 bytes) can be effectively used without waste.
According to the third aspect of the present invention, it is possible to reduce the capacity of the memory used for the STM signal cross-connect processing.
[0077]
According to the fourth aspect of the invention, it is possible to reduce the memory capacity used for the cross-connect processing of the STM-4 signal.
According to the invention described in claim 5, the number of storage areas on the first and second surfaces of the conventional first memory is 1080 bytes, but according to the present invention, it can be reduced to 720 bytes. Only 2/3 the memory capacity is required as compared with the conventional example.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a time chart of data processing in the embodiment.
FIG. 3 is a diagram illustrating the concept of data processing in the embodiment.
4A and 4B are diagrams for explaining the prior art, in which FIG. 4A shows a multiplexing structure standardized by ITU-T, and FIG. 4B shows multiplexing of the TTC standard used in Japan. It is a figure showing a structure.
FIG. 5 is a diagram illustrating an example of a multiplex format in SDH in a case where “apples” corresponding to electronic information are put in a box and carried by a “freight train” corresponding to SOH.
FIG. 6 (A) is a diagram showing layering of a transmission network, and FIG. 6 (B) is a diagram showing positioning of sections and paths in SDH.
FIG. 7A is a diagram showing a process of forming AU-4 from VC-4 and multiplexing to AUG, and FIG. 7B is a diagram showing a process of multiplexing AUG to STM-N. .
8A is a conceptual diagram of an STM-1 multiplexed frame, and FIG. 8B is a diagram showing an offset value of an AU-4 pointer.
FIG. 9 is a diagram showing the positioning of a cross-connect device in SDH.
FIG. 10A is a block diagram for implementing TSW, and FIG. 10B is a conceptual diagram of STM-1.
11A and 11B are diagrams illustrating phase adjustment, in which FIG. 11A shows the position of the first byte (J1 byte) before the phase adjustment, and FIG. 11B shows the position of the first byte (J1 byte) after the phase adjustment. FIG.
[Explanation of symbols]
11 Data memory
11a First side of data memory
11b Second side of data memory
12 Frame pulse extraction unit
13 S / P section
14 720 decimal counter
15 1080 decimal counter
16 binary counter
17 Control memory
18 Arithmetic unit
19 P / S section

Claims (5)

A first memory having a first surface and a second surface for performing cross-connect processing on input data, a second memory for storing address data at the time of cross-connect processing in the first memory; A control means for controlling the cross-connect processing based on the address data stored in the second memory;
The control means,
From the input data, reference pulse extracting means for extracting a pulse serving as a reference at the time of cross-connect processing,
A first pulse train for generating a first pulse train for each pulse number corresponding to the number of storage areas in each row of the first surface and the second surface in the first memory, based on the reference pulse extracted by the reference pulse extracting means. Pulse generating means;
A second pulse generation unit that generates a second pulse train for each pulse number corresponding to the number of storage areas in one row in the second memory based on the reference pulse extracted by the reference pulse extraction unit;
A third pulse generation unit that generates a binary pulse based on the reference pulse extracted by the reference pulse extraction unit;
A data memory control method, wherein data obtained by equally dividing the second pulse train is subjected to cross-connect processing in correspondence with 0 or 1 of the binary pulse. The data memory control method according to claim 1,
When the number of storage areas in one row of the second memory is P (integer) and the number of storage areas in each row of the first and second faces of the first memory is Q (integer), A data memory control method wherein P / Q is divisible. In the data memory control method according to claim 1 or 2,
2. The data memory control method according to claim 1, wherein the input data is an STM signal used for a SONET / SDH device. The data memory control method according to any one of claims 1 to 3,
The data memory control method according to claim 1, wherein the STM signal is an STM-4 signal. The data memory control method according to any one of claims 1 to 4,
A data memory control method, wherein the number of storage areas on the first and second sides of the first memory is 720 bytes, and the number of storage areas on the second memory is 1080 bytes.

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