KR0126846B1 - A multiplexing apparatus of stm-4 - Google Patents

Abstract

A multiplexer of a STM-4 class equalizing a connection relation of 4 AUG signals forming STM-4 signal, and easily employs DS1-N, DS1-E, DS3 signal and a STM-1 signal unit, thereby providing a stable STM-4 multiple device. The multiplexer includes: a DS1-N signal AUG multiplexer(1) for multiplexing DS1-N signal; a DS1-E signal AUG multiplexer(1) for multiplexing DS1-E signal; a AUG multiplexer(3) of DS3 signal to multiplex DS3 signal; STM-1 signal forming means(4) for receiving STM-1 signal as an input; STM-4 signal forming means(5) having a commong parallel AUG data and a reference clock format; and a system timing generator for providing a system timing to the multiplexers(1,2,3,4,5).

Description

STM-4 class multi device

1 is a functional block diagram for the STM-4 multi-device configuration of the present invention,

2 is a connection diagram between an AUG multiple part and an STM-4 signal forming part of a DS-N signal;

3 is a connection diagram between an AUG multiple part and an STM-4 signal forming part of a DS1-E signal,

4 is a connection diagram between an AUG multiple part and an STM-4 signal forming part of a DS3 signal;

5 is a connection diagram between an STM-1 signal generator and an STM-4 signal generator;

6 is a signal waveform diagram of FIGS.

7 is an AUG multiplexing diagram of a DS1-N signal,

8 is an AUG multiplexing diagram of a DS1-E signal,

9 is an AUG multiplexing diagram of a DS3 signal.

10 is a block diagram of the STM-1 signal forming unit;

11 is a block diagram of the STM-4 signal generator;

* Explanation of symbols for main parts of the drawings

1: AUG multiple part of DS1-N signal 2: AUG multiple part of DS1-E signal

3: AUG multiple part of DS3 signal 4: STM-1 signal forming part

5: STM-4 signal generator 6: system timing generator

Among the asynchronous transmission signals of the present invention, the North American DS1 class 1.544Mb / s signal (hereinafter referred to as DS1-N) and the European DS1 class 2.048Mb / s signal (hereinafter referred to as DS1-E), 44.736Mb / s A synchronous 622.080 Mb / s optical signal (hereinafter referred to as STM-4) is used as a slave signal using a signal (hereinafter referred to as DS3) and a synchronous 155.520 Mb / s signal (hereinafter referred to as STM-1). A STM-4 class synchronous multiple device to be formed.

According to the present invention, DS1 through an exchange of units forming an AUG signal by equalizing the connection relationship of four AUG signals forming an STM-4 signal in the construction of an STM-4 class synchronous multiple device at a rate of 622.080 Mb / s. The objective is to provide a flexible and stable STM-4 multi-device by allowing interoperability using -N, DS1-E, DS3 signals, and STM-1 capacitive signal units.

In order to achieve the above object, the present invention provides a DS1-N signal AUG multiplexing means for multiplexing a DS1-N (North American DS1 class, 1.544 Mb / s signal among asynchronous transmission signals) signal; AUG multiple means of DS1-E signal to multiplex DS1-E (European DS1 class 2.048 Mb / s signal) signal; AUG multiplexing of the DS3 signal to multiplex the DS3 (44.736 Mb / s signal) signal; STM-1 signal forming means for inputting an STM-1 (synchronous 155.520 Mb / s signal) signal; STM-4 (synchronous 622.080) having a common parallel AUG data and a reference clock form connected to the DS1-N signal AUG multiple means, the AUG multiple means of the DS1-E signal, the AUG multiple means of the DS3 signal, and the STM-1 signal forming means. Mb / s optical signal) signal forming means; And system timing generating means for providing system timing to the DS1-N signal AUG multiple means, the AUG multiple means of the DS1-E signal, the AUG multiple means of the DS3 signal, the STM-1 signal forming means, and the STM-4 signal forming means. It characterized by having a.

The STM-4 class multi-valued value of the present invention accommodates STM-1, DS3 and all STM-4 sub-level transmission signals including DS1-N and DS1-E.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a functional block diagram of an STM-4 multi-device of the present invention.

STM-4 multi-device will accept DS1-1, DS1-E, DS3 and STM-1 bidirectional transmission signals as medium speed signals. The AUG multiplexer (1) of DS1-N signal accepts up to 84 DS1-N signals and passes STM through multiplexing paths of DS1-N- -VC11- -TU11 (TU12)--TUG2- -VC3- -AUG. -4 is connected to the signal forming unit 5.

AUG multiplexing (2) of DS1-E signal accommodates up to 63 DS1-E signals to form STM-4 signal through multiplexing path of DS1-E--VC12- -TUG2- -VC3- -AU3-AUG It is connected to the unit (5).

The AUG multiplexer 3 of the DS3 signal accepts up to three DS3 signals and is connected to the STM-4 signal generator 5 via a multiplexing path of DS3- -VC3- -AU3- -AUG.

The STM-1 signal generator 4 receives one STM-1 signal and connects it to the STM-4 signal generator 5 via a path of STM-1- -AUG-AU3- -AUG.

The STM-4 signal generator 5 multiplexes four AUG signals through the multiplexing path to form and transmit an STM-4 signal, and the basic clock signal required for each function block is transmitted from the system timing generator 6. to provide.

2 is a connection means between the AUG multiple part of the DS1-N signal and the STM-4 signal forming part.

AUG multiple of DS1-N signal receives 19.44Mb / s parallel AUG data by receiving 19.44MHz of parallel AUG clock at STM-4 signal generator, 3.328MHz of VC11 formation clock and 50.112MHz of VC3 formation clock at system timing generator. To form.

Access to the STM-4 signal generator consists of parallel AUG data of 19.44 Mb / s and a reference clock of 8 KHz indicating the start of the AUG frame. The reverse process receives the parallel AUG clock 19.44 MHz, 19.44 Mb / s parallel AUG data from the STM-4 signal generator, and a reference clock of 8 KHz indicating the starting point of the AUG frame. The DS1-N signal is formed and output using a phase locked loop circuit.

3 is a connection diagram between an AUG multiple part and an STM-signal part of a DS1-E signal.

Similarly to the second diagram, the AUG multiple part of the DS1-E signal receives the parallel AUG clock 19.44 MHz in the STM-4 signal generator and 4.480 MHz in the VC12 forming clock and 50.112 MHz in the VC3 forming clock in the system timing generator. Produce parallel AUG data in / s.

Access to the STM-4 signal generator consists of parallel AUG data of 19.44 Mb / s and a reference clock of 8 KHz indicating the start of the AUG frame. The reverse process receives the parallel AUG clock 19.44 MHz, 19.44 Mb / s parallel AUG data from the STM-4 signal generator, and a reference clock of 8 KHz indicating the starting point of the AUG frame. The DS1-E signal is formed and output by using a phase locked loop circuit.

4 shows parallel AUG data of 19.44Mb / s by receiving the parallel AUG clock 19.44MHz from the AUG multiple part of the DS3 signal and the STM-4 signal forming part and 50.112MHz of the VC3 forming clock from the system timing generator.

Access to the STM-4 signal generator consists of parallel AUG data of 19.44 Mb / s and a reference clock of 8 KHz indicating the start of the AUG frame. The reverse process receives the parallel AUG clock 19.44 MHz, 19.44 Mb / s parallel AUG data from the STM-4 signal generator, and a reference clock of 8 KHz indicating the start point of the AUG frame. Form and output DS3 signal using (Phase Locked Loop) circuit.

5 is a connection diagram between the STM-1 signal generator and the STM-4 signal generator.

The STM-1 signal generator receives the parallel AUG clock 19.44 MHz from the STM-4 signal generator to form parallel AUG data of 19.44 Mb / s.

Access to the STM-4 signal generator consists of parallel AUG data of 19.44 Mb / s and a reference clock of 8 KHz indicating the start of the AUG frame. The reverse process receives the parallel AUG clock 19.44 MHz, 19.44 Mb / s parallel AUG data from the STM-4 signal generator, and a reference clock of 8 KHz indicating the starting point of the AUG frame. A STM-1 signal is formed and output using a furnace (multiplying 19.44 MHz to 15.520 MHz).

6 is a signal waveform diagram of FIGS.

Signal waveform between the AUG multiple part of the DS1-E signal and the STM-4 signal forming part of FIG. 2, signal waveform between the AUG multiple part and the STM-4 signal forming part of the DS1-E signal of FIG. 3, and AUG of the DS3 signal of FIG. Signal waveforms between the central portion and the STM-4 signal forming portion, the signal waveforms between the STM-1 signal forming portion and the STM-4 signal forming portion in FIG. 5 have a common signal waveform as shown in FIG.

The primary clock source is the 19.44 MHz parallel AUG clock, which indicates the starting point of the AUG transmission frame as a reference clock of 8 KHz.At this time, the 19.44 Mb / s parallel AUG data indicates the position of the frame word A1A1A1A2A2A2 at the zero point of the 8 KHz clock. Done.

7 is an AUG multiplexing diagram of the DS1-N signal.

The LPS accepts bidirectional DS1-N signals and consists of a switching relay device for switching LSM-N modules.

The LSM-N receives the DS1-N signal from the LPS, multiplexes it with C11-VC11-TU11 (TU12) -TIUG2, and simultaneously performs the reverse function of the above function.

HSM-1 has a function of connecting the TUG2 signal from the LSM-N and multiplexing it to the TUG2-C3-VC3-AUG signal, or conversely, demultiplexing the AUG signal to the VC3-C3-TUG2 and sending it to the LSM-N.

8 is an AUG multiplexing diagram of the DS1-E signal.

Similar to Figure 7, the LPS accepts bidirectional DS1-E signals and consists of switching relay elements for switching LSE-E modules. The LSM-E receives the DS1-E signal from the LPS, multiplexes it into C12-VC12-TUG12, and simultaneously performs the reverse function of the above function. HSM-1 connects TUG2 signal from LSM-E, connects TUG2 signal, connects TUG2 signal, multiplexes to TUG2-C3-VC3-AUG signal, or conversely demultiplexes AUG signal to VC3-C3-TUG2 to LSM- Has the function of sending to E

9 is an AUG multiplexing diagram of a DS3 signal.

The AUG multiplex of the DS3 signal directly connects three DS3 signals to multiplex the C3-VC3-AUG signal and conversely demultiplexes the AUG signal to C3 to transmit the DS3 signal.

10 is a block diagram of the STM-1 signal generator.

The STM-1 signal forming unit connects the STM-1 optical signal and puts an AU frame alignment function on the receiving side of the STM-1 to form the AUG signal by aligning the received data by transmission timing, and simultaneously receives the AUG signal to receive the STM-1. Form a signal and send it out.

11 is a block diagram of the STM-4 signal generator.

The STM-4 signal generator performs the STM-4 optical transmission function after connecting and multiplexing four AUG signals to perform signal insertion, generation, scrambling, and STM-4 framing.

In addition, the STM-4 optical signal is received to perform reframing, descrambling, reception clock, and reception data regeneration functions. After processing the STM-4 section overhead, the signal is demultiplexed into four AUG signals and transmitted.

The present invention configures the STM-4 class synchronous multi-device as described above, and the DS1-N, DS1-E, DS3 signal, and also through the interchange of the units forming the AUG signal by making the same connection relationship of the four AUG signals The STM-1 capacitive signal unit can be easily mixed and used to not only have a flexible functional configuration but also provide a stable multiple device at a speed of less than 20 MHz by parallelizing the connected signals. It can accommodate STM-1, DS3 and all STM-4 sub-level transmission signals including DS1-N, DS1-E, and in particular, can provide a device that can accommodate DS1 level signals.

Claims (5)

A DS1-N signal AUG multiplexer 1 for multiplexing a DS1-N (North American DS1 class, 1.544 Mb / s signal among asynchronous transmission signals) signal; AUG multiple means 2 of DS1-E signals for multiplexing the DS1-E (European DS1 class 2.048 Mb / s signal) signal; AUG multiplexing 3 of the DS3 signal to multiplex the DS3 (44.73 Mb / s signal) signal; STM-1 signal forming means 4 for receiving an STM-1 (synchronous 155.520 Mb / s signal) signal; Parallel AUG data connected to the DS1-N signal AUG multiple means 1 and the AUG multiple means 2 of the DS1-E signal and the AUG multiple means 3 of the DS3 signal and the STM-1 signal forming means 4 in common. And STM-4 (synchronous 622.080Mb / s optical signal) signal forming means (5) having a reference clock form; And the DS1-N signal AUG multiple means (1), the AUG multiple means (2) of the DS1-E signal, the AUG multiple means (3) of the DS3 signal, and the STM-1 signal forming means (4), and the STM-4 signal. STM-4 class multiplexing device comprising system timing generating means (6) for providing system timing to the forming means (5). 2. A method according to claim 1, wherein the connecting means between the AUG multiple means (1) and the STM-4 signal forming means (5) of the DS1-N signal has a parallel AUG signal form and from the system timing generating means (6) to DS1-N. STM-4 class multi-device, characterized in that the AUG multiple means (1) of the signal is provided to provide 50.112MHz, 3.328MHz and STM-4 signal forming means (5) is provided to 19.44MHz. The method according to claim 1, wherein the connecting means between the AUG multiple means (2) and the STM-4 signal forming means (5) of the DS1-E signal has a parallel AUG signal form and from the system timing generating means (6) to the DS1-E. AUG multiple means (2) of the E signal is provided 50.112MHz, 4.480MHz STM-4 signal forming unit (5) STM-4 class multiplexer, characterized in that configured to receive 19.44MHz. 2. A method according to claim 1, wherein the connection means between the AUG multiple means (3) of the DS3 signal and the STM-4 signal forming means (5) has a parallel AUG signal form and the AUG multiple of the DS3 signal from the system timing generating means (6). Means (2) is provided to 50.112MHz and said STM-4 signal forming means (5) is configured to receive 19.44MHz STM-4 class multi-device. The method of claim 1, wherein the connecting means between the STM-1 signal forming section 4 and the STM-4 signal forming means 5 has a parallel AUG signal form and the STM-1 signal forming from the system timing generating means 6 Means (4) is STM-4 class multiple device, characterized in that the STM-4 signal forming means (5) is configured to receive only 19.44MHz without being provided a clock.