KR0179505B1 - Apparatus for lining up frame of tu signal for low-speed switching - Google Patents

Abstract

The present invention relates to a frame aligner of a TU signal for low-speed switching, comprising: clock generation and channel selection means (100) for processing received VC3 data from the outside or extracting a received clock from a received clock; VC3 POII detection and processing means (200) connected to the clock generation and channel selection means (100) for detecting and processing 9 bytes of VC3 overhead; TU frame alignment means (300) connected to the VC3 POH detection and processing means (200) to rearrange 21 TU12 frames according to a new reference clock; A data multiple means (400) connected to the TU frame alignment means (300) and outputting TU12 data and a clock by multiplexing three data in synchronization with a system clock; LPOM means (800) connected to the TU frame alignment means (300) for monitoring and processing data of V5; Data selection and TU signal monitoring means 700 for monitoring 21 TU signals from the outside to insert a UNEQUIPPED signal when a signal is not present; A VC3 POH insert 600 connected to the data selection and TU signal monitoring means 700 to insert and process a VC3 overhead; It is connected to the VC3 POH insert means 600, characterized in that it comprises a clock generation and channel transmission means 500 for interface with the required clock and the upper both of the transmitter.

Description

Frame Aligner for TUI Signals for Slow Switching

1 is a schematic diagram of a system to which the present invention is applied.

2 is a block diagram of an embodiment of a TU frame rearranger according to the present invention.

3 is a detailed view of one embodiment of FIG.

4a to 4d are timing diagrams in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

100: clock generation and channel selector 200: VC3 POH detection and processor

300: TU frame sorter 400: data multiplexer

500: clock generation and channel transmitter 600: VC3 POH insertion unit

700: data selection and TV signal monitor 800: LPOM unit

The present invention is directed to the extraction and rearrangement of a TU (Tributary Unit) signal multiplexed on a fast AU3 (Administration Unit 3) signal in a system that performs circuit branching and distribution functions of a broadband transmission network, and to multiple / demultiplexing into an AU signal. A frame aligner of a TU signal for low-speed switching in units of TUs.

In general, in the broadband circuit branching and distribution system, switching of the high speed unit and TU unit of the high speed unit and the TU unit of the low speed unit are necessary for efficient connection of the transmission network during the bypass route of the optical transmission device, the fire and the line breakage, or the call congestion of some telephone networks. need.

In the conventional case, a PLL (Phase-Locked Loop) is performed in processing a plurality of TU signals that are multiplexed after extracting VC3 (Virtual Container 3) data from an AU3 signal to perform related overhead processing and rearrangement of TU pointers. Due to the use of and complex clock system, there is a problem that the switching of TU unit requires the application of complex hardware and multi-level clock. Therefore, in order to perform efficient TU unit switching, a simple clock system using a synchronized system clock is required.

It is an object of the present invention to provide a frame aligner of a TU signal for low speed switching using a clock needed for overhead processing and interpretation and rearrangement of the TU pointer using a simplified system clock.

In order to achieve the above object, the present invention comprises: clock generation and channel selection means for processing received VC (Virtual Container) 3 data from the outside or extracting a received clock from a received clock; VC3 POH (Path OverHead) processing means connected to the clock generation and channel selection means for detecting and processing VC3 overhead; TU frame alignment means connected to the VC3 POH processing means to rearrange a plurality of channels of a Tributary Unit (TU) 12 frame according to a reference clock; A multiple means connected to the TU frame alignment means and multiplexing a plurality of data in synchronization with a system clock to output TU12 data and a clock; LPOM (Lower-Order Path Mapping) means connected to the TU frame alignment means for monitoring and processing data of V5; Data selection and TU signal monitoring means for monitoring a plurality of TU signals from the outside and inserting a UNEQUIPPED signal into a corresponding channel when no signal exists; VC3 POH insertion means coupled to the data selection and TU signal monitoring means for insertion and processing of VC3 overhead; And a clock generation means and a channel transmission means connected to the VC3 POH insertion means to interface with a clock and a higher module of the transmitter.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 shows a broadband inter-switch matching board (TSMB) to which the present invention is applied.

As shown in FIG. 1, between an AU pointer termination processor (AUTP) ASIC chip (2) functioning as an AU3 pointer termination function and a Timew Switch fjor Tu12 (TUTS) ASIC chip (4) performing a UU12 unit time switching function, as shown in FIG. It consists of a TUSM ASIC chip (3) that performs VC3 POH (Path OverHead) termination, TU12 frame alignment, monitoring VC3 POH, and monitoring and processing VC12 access signals.

First, the main functions that are included in the Supervisory Monitoring for TU (ASU) ASIC are: VC3 POH processing, TU pointer interpretation (PI), TU12 pointer processing (PG), Lower Order Unequipped Signal Label Generator (LUG) for TU1 signals, Lower-Order Path Mapping (LPOM), and CPU interface functions.

The CPU interface module 6 includes an address decoder, an interrupt processor, and various registers, which collect and process various types of information on alarms and performances according to pointer status and circuit status, and directly interface with the CPU. Performs operation control and status reporting to the CPU.

AUTP 2 and TUSM 3 shown in the figure are 19.44 Mbps 8-bit parallel signals, and three channels of VC3 signals are byte-multiplexed to interface with a GAPPED 19.44 Mbps signal structure. The data can then be retimed to 6.48 Mbps, which means that it interfaces with data and clocks with a gapped VC3 frame structure.

The interface with the TUTS 4 also has a parallel data structure having a structure in which a TU12 signal having a gap of a synchronous signal of 19.44 Mbps is multiplexed by 22 × 3.

In addition, S77M of the clock driver 7 represents a system clock, S8K represents a system 8kHz frame clock, and S2K represents a system 2kHz frame clock, and supplies corresponding clocks to AUTP (2), TUSM (3), and TUTS (4), respectively. .

The clock of the AUTP 2 is divided into a transmission clock and a reception clock, and there are T77MD, T77MC, T8K in the transmission clock system, and R77M, R77MC, and R8K in the reception clock system.

Here, T77MC is a 77MHz transmission block, T8K is an 8kHz frame clock, and T77MD is a data signal synchronized with T77MC and T8K.

R77MC is 77MHz as a reception clock, R8K is an 8kHz frame clock, and R77MD is a data signal synchronized with R77MC and R8K.

In addition, the TUTS 4 uses the same clock system for both transmission and reception, T38MC represents a clock of 38 MHz, T2K represents a 2 kHz frame clock, and T38MD represents data synchronized to T38MC and T2K.

The VC3 POH processing unit in TUSM (3) processes J1 bytes in the 16-byte format specified by 1TU-T, processes and inserts B3, H4, G1, and C2 bytes, and stores Z bytes in preparation for tandem connection. It handles pointer interpretation, pointer generation, and pointer buffer functions to align TU12 signal frames. The signals input at parallel 6.264 Mbps are synchronized with the J1 clock. The J1 clock is used as a reference clock to process the POH part, and the POH-processed data is demultiplexed into 7 TUG data and applied to the TU12 pointer processing function. Here, the reference clock 2KHa is generated by recognizing the V5 position, and new values of V1 and V2 are formed based on the reference clock of the system. Pointer for V5 Position Interpreted Reference Clock is a pointer that indicates the V5 position only via the 21 selector inputs. The reference clock has 21 selector inputs and only selected channels can be connected to the CPU with V5 data. This function is called LPOM function. The TU12 data read from the pointer buffer is 288K, which is parallel data. This parallel data is gathered and becomes 66: 1 multiplex with one dummy channel, which is the structure of Fig. 4a with 19.44Mbps multiplexed data (LBUS).

2 is a block diagram of an embodiment of a TU frame rearranger according to the present invention. The VC3 POH detection and analysis unit 200, the TU frame alignment unit 300 for rearranging 21 TU12 signals, and the V5 in the TU12 signal are shown in FIG. LPOM function 800 for monitoring the overhead in the data and monitoring the overhead therein, data selection and TU signal for detecting and inserting the UNEQUIPPED signal in the signal label bit of V5 depending on the presence or absence of TU12 signal. The clock generation and channel selector 100, data, which makes the unity of the clock and the interface by using the gap (LUG) 700, the VC3 overhead insertion unit 600, the synchronous signal and the clocked gap clock. A central portion 400 and a clock and channel transmitter 500 are provided.

Detailed block and design contents are described below.

First, the VC3 POH detection and analysis unit 200 processes nine overheads from a 6.264 Mbps signal, and the processing speed of the overhead is detected and inserted by 8 bits at a speed of 72 KHz. Overhead detection and insertion is performed in the form of regular gaps and data in 6.48Mbps signals, which extracts and multiplexes 21 TU12 signals with 3 bytes missing from the VC3 frame. The 8 KHz clock, which is the J1 signal, is delayed to a 72 KHz clock to insert and detect the 9-byte VC3 overhead.

The VC3 overhead insertion unit 600 performs VC3 overhead insertion and processing without disassembly on the frame for each channel. The overhead to be handled is 9 bytes, which is handled as follows:

(1) J1 (PATHTRACE) byte processing: It is used for path tracking and requires 16 bytes of memory. The CPU interface is made, and the first byte has the result of the start of the frame and the calculation of CRC-7 of the previous frame.

(2) B32 bytes (BIP-8): Used for performance monitoring on the VC3 path, the value calculated for each bit for all bytes is inserted into the next frame, and the number of errors is sent in FEBE bytes of G1 bytes. do.

(3) C2 (Signal Label) Byte: Monitors the CPU interface by monitoring the use of VC3 path and the special signal combination structure of payload for 3 consecutive frames.

(4) G1 (Path Status Byte): Bits 1-4 are processed as FEBE (performance received by detecting B3 of the large station), bits 5 RAI, and bits 6-8 unused.

(5) H4 byte: TU12's multi-frame indication, overhead indicating the location and starting pointer of TU1 frame.

All of the above overhead bytes must be terminated in this circuit to take care of all of the overhead of VC3.

Next, the TU frame alignment unit 300 will be described in detail with reference to FIG. 3.

First, when the pointer analysis function (pointer generation PG) 340 has a TU12 pointer interpretation function for one TU12 signal, 21 modules each independently operate the same function. The V5 clock is analyzed by pointer analysis in V1 and V2 bytes to extract V5 data and write the VC12 signal to the pointer buffer. At this time, the extracted V5 data is transmitted to the module that performs the LPOM function.

All'l (AIS_ind), NDF bit, SS bit, PV invalid, I / D inversion state, etc. are detected from the reception pointer word PW, and the result is sent to the pointer state determination module.

When creating V5, if the pointer value is determined by recognizing V1 and V2 data, the value is determined within the range of 1 to 140 by the counter, and the pointer value is extracted from it, which indicates the position of V5.

The pointer buffer (PB) 330 must be buffered for the removal of a fixed dummy biter and for the generation of a new frame pointer between the clock received at AUTP (2 in Figure 1) and the system clock, so that the capacity of the pointer buffer uses the system clock. TX, RX gap between clocks, 2 bytes by V1, V2, V3, V4, 1 byte by reception P / N Justification according to transmission P / N Justification 4 bytes for byte, jitter and wonder absorption, consisting of 16 bytes in total.

The pointer buffer monitoring and pointer adjustment server (JP) 360 sets the threshold value to +/- 8 bytes and exceeds the buffer limit outside this range, and thus cannot be accommodated for position adjustment to generate an alarm.

The 16-point pointer buffer reflects this because it is a type of clock with a regular gap due to the use of a synchronous frequency division clock.

The overhead to be monitored in LPOM 390 of VC1 should be accessible and handled by V5, J2, N2, K4 bytes.

(1) V5 byte: bit 1-2 for BIP 2, bit 3 for REI, bit 4 for RFI in VC unit, bit 5-7 SIGNAL LABEL, bit 8 for AIS in TU unit or RDI detection in case of failure Used as

(2) J2 byte processing: The monitor for 21 channels can be inserted by one CPU access.

Overhead extraction should be performed at the front end of the pointer buffer after the interpretation of the pointer. At this time, data should be latched by the overhead data and signals of 2Khz (V5) and 8Khz, and these data use only 3 channel capacity (TUG unit). do.

Among the functions of the LUG 700, the overhead of being interpreted and inserted for each channel by being interconnected with the downlink LPOM includes FEBE and FERF informing J2 bytes and power alarm. It is designed to be detected in hardware because it informs the performance and alarm of the signal coming from the station.

LUG; If there is no signal by monitoring V1, V2, and V5, insert it into the signal label position of V5, and monitor the UNUGQUIPPED signal with the LUG module.The signal coming from TU12 in conjunction with the part generating the signal of TU12 (K Alternatively, select (m) and send the signal (n) generated by the LUG module.

The monitor 720 of the non-mounted signal monitors all zero signals three frames and transmits a TU12 frame n when all signals are zero. FERFs and FEBEs are detected on the reception link and inserted on the transmission.

The interface module 400 with TUTS (4 in FIG. 1) uses a dummy channel of one channel in a VC3-class capacity that processes 21 TU12 capacity of 6.264 Mbps, which is a parallel interface of VC3, to multiplex to 6.48 Mbps. Using the regular GAPPED for 22 channels with a speed of 288K with the capacity of VC3, the system clock is generated as a synchronized signal by multiplexing to simplify the clock system.

As shown in FIG. 4C, 8-bit parallel 19.44 Mbps 3-phase data (288 kHz 22 X 38 bits (e1, e2), received in TUTS (4 in Fig. 1), 19.44 Mbps 3-phase data 8 bits (d1, d2) transmitted to TUTS Interface allows the use of a simple divided single clock of the system clock.

AUTP (2 in FIG. 1) and this interface (100,500) are connected to 19,44 Mbps (6.264 Mbps VC3 data 8 bits (a1)) with AUGT in AUPT (2 in FIG. 1), as shown in FIG. 4D. 19.44 Mbps 3-phase multiplexed 8-bit (b1) with transmission gap, reference clock for transmission / reception 8 kHz: 2-wire (a2, b2), TX system clock (38.88 Mbps; C1) use.

The timing generation module 900 is composed of a reception timing module and a transmission timing module. 72KHz clock and TUG data required for the processing of the receive VC3 path overhead using the system clock (a3) for a clock having a VC3 frame structure with a gap received from the receiving module AUPT (2 in FIG. 1). Create a TUG 864K clock, 2K (h) to extract the V5 data, and a TU12 288K clock (h) needed to interpret the pointer.

The TX timing module generates a clock to interface the TU12 clock (j), TUG clock, and TUTS with the data to be rearranged on the pointer buffer, which is used as a clock to transmit the data received from the TUTS to the AUPT.

In the broadband circuit branch distribution system, which is a function of the transmission equipment of the telephone station, the high speed part needs to be switched in AU units and the low speed part needs to be switched in TU units for the right connection of the optical transmission device.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

According to the present invention as described above, the TU unit frame alignment function for switching the TU unit and monitoring the empty line during the switching, TU unit at the time of line routing, fire and line cutting, or congestion of some long distance telephone network There is an effect that can be efficiently performed when using the line.

Claims (1)

Clock generation and channel selection means for processing external VC (Virtual Container) 3 data from the outside or for extracting a received clock from a received clock; VC3 POH (Path OverHead) processing means connected to the clock generation and channel selection means for detecting and processing VC3 overhead; TU frame alignment means connected to the VC3 POH processing means to rearrange a plurality of channels of a TU (Reibutary Unit) 12 frame according to a reference clock; A multiple means connected to the TU frame alignment means and multiplexing a plurality of data in synchronization with a system clock to output TU12 data and a clock; LPOM (Lower-Order Path Mapping) means connected to the TU frame alignment means for monitoring and processing data of V5; Data selection and TU signal monitoring means for monitoring a plurality of TU signals from the outside to insert a UNEQUIPPED signal into a channel to be disconnected when no signal exists; VC3 POH inserting means connected to diffuser data selection and TU signal monitoring means for inserting VC3 overhead; And a clock generation unit and a channel transmission unit connected to the VC3 POH inserting unit and configured to interface with a clock and a higher module of the transmitter.