KR100198438B1 - Apparatus for arranging signal frame and surveying signal - Google Patents

Abstract

The present invention relates to signal frame alignment and signal monitoring in a TU11 / TU12 mixed mode. In the conventional method, only a TU11 signal or a TU12 signal has a signal frame alignment function, and an additional connection function for the VC1 signal path is disconnected. In order to solve the problem, the present invention has been made to solve the problem, because the monitoring and management function of the signal path is weak. The VC3 signal extracted from the AU signal is terminated and multiplexed in the VC3. It sends the switch network by rearranging the TU signal, which is a low-speed signal, and processes the reverse process, and receives VC3 data and outputs the TU data in the lower end, and vice versa. Demultiplexes the multiplexed VC3 data input from the outside to select and extract a single VC3 data, TU1 signal frame that detects and processes VC3 path overhead in VC3 data, demultiplexes 28 TU11 signals or 21 TU12 signals in VC3 data, and realigns them according to a new reference clock through pointer processing for each TU1 signal. It monitors alignment and path overhead of VC11 / VC12 signal, and monitors up to 28 TU11 signals or 21 TU12 signals from the outside and inserts disconnected signals in the corresponding channel when there is no signal. VC3 frame is formed by inserting the VC3 path overhead into LSUT function and 28 TU11 signals or 21 TU12 signals, and outputs them.The above functions can operate in a mixed mode that can be applied to both TU11 and TU12. In case there is no error, it has a function to monitor and insert the disconnected status so that it can smoothly process the disconnected status signal. That there is an effect.

Description

Signal frame alignment and signal monitoring

The present invention relates to VC3 signal termination, TU11 / TU12 signal frame alignment and signal monitoring, and is a system for providing flexible routing of transmission signals through a signal connection function and a signal switching function between high-speed optical signals in a synchronous transmission network. The circuit distribution system has mutual distribution of signals and branch / combination functions, and performs network management function for synchronous transmission network.

In addition, the synchronous line distribution system (SDH-DXC) simultaneously performs a line distribution function of AU3 / AU4 unit of 50M / 150M class synchronous signal and a line distribution function of TU11 / T U12 unit of 1.5M / 2M class synchronous signal. For TU11 / TU12 unit line distribution, that is, switching, it is necessary to extract the TU11 / TU12 signal frame from the above together with VC3 signal termination and realign it to the system timing, and also to control the switching state. Keep track of the path at all times.

The conventional method mainly has a signal frame alignment function for only one TU11 signal or one TU12 signal, and lacks an additional monitoring function for the VC1 signal path, that is, monitoring and managing an unconnected signal path.

In order to solve the problems of the prior art as described above, the present invention provides a signal frame alignment and an additional monitoring function for a TU11 signal that cannot be processed in the prior art when the SDH-based TU11 / TU12 unit signals are mixed in TUG units. In order to perform this function, a timing generator for generating divided clocks for each mode of each of the TU11 / TU12 signals is provided so that a mode selector capable of accommodating both TU11 / TU12 signals is provided, and no VC1 / VC2 signals are present. It has a function to monitor and insert the disconnected state.

1 is an application example of the present invention.

2 (a) is a STM-1 frame structure diagram according to the present invention.

2 (b) is a TU1 frame structure diagram according to the present invention.

2 (c) is a structural diagram of a TU1 pointer according to the present invention;

Second (d) is a structural diagram of VC1 path overhead (POH) according to the present invention.

3 is an overall configuration diagram of TU11 / TU12 signal frame alignment and signal monitoring according to the present invention.

4 (a) is a downlink input signal timing and frame structure diagram of the present invention.

4 (b) is an upstream output signal timing and frame structure diagram of the present invention.

4 (c) is a diagram illustrating a structure of an internal input frame for a downstream input of the present invention.

5 (a) is a structure diagram of the internal signal frame of the down-end output (upper stage input) for the TU11 mode according to the present invention.

5 (b) is a structure diagram of the internal signal frame of the down-end output (upper stage input) for the TU12 mode according to the present invention.

5 (c) is a structure diagram of a downlink output signal (upstream signal) for TU12 mode.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view of application of the present invention.

1 is an example of application of the signal frame alignment and signal monitor of the TU11 / TU12 mixed mode according to the present invention, the AUG signal generator 100 comprising a multiplexer 110 and a demultiplexer 120, and a TU cross-connect. connect) The signal generator, which is located between the switches 200 and extracts the VC3 signal from the AUG signal, receives the VC3 signal, terminates the VC3 signal 310, and rearranges the TU signals multiplexed therein to form a TU frame. And outputs to the cross connector 200 for TU unit switching (320), and monitors the signal state after TU unit switching (330) and forms (310) the VC3 signal.

Figure 2 (a) is a structural diagram of the STM-1 frame according to the present invention.

The structure is a VC3 signal frame structure input and output to and from the AUG signal generator 100, Figure 2 (b) is the structure of the TU1 frame, Figure 2 (c) is the structure of the TU1 pointer, Figure 2 (d) is VC1 Represents the structure of the path overhead, respectively.

In the following Figure 3, the downstream input and upstream output signals are in the form of an 8-bit parallel signal with an STM-1 frame capacity of 19.44 Mbps, and the input / output signal timing and frame structure diagram thereof are shown in FIG. By extracting and processing (6.48Mbps), it has a processing capacity equivalent to one VC3 class.

In this case, the VC3 data is inputted and outputted as TU1 data is defined as a down-link and vice versa as an up-link.

3 is an overall configuration diagram of TU11 / TU12 signal frame alignment and signal monitoring according to the present invention.

In the overall configuration, the main components of the block VC3 demultiplexer 310, the TUG demultiplexer 320, the VC3 path overhead processor 330, and the TU signal frame aligner 400, TU1 multiple output unit 340, the upper end of the TU1 demultiplex input unit 360, the signal monitoring and TU1 frame forming unit 500, TUG multiple unit 370, VC3 path overhead insertion unit 380, a VC3 multiple output unit 390, and a timing generator 600, and a microprocessor interface unit 800.

In FIG. 3, the downstream VC3 demultiplex input unit 310 includes a VC3 frame offset 32 indicating a start point of the VC3 frame, and a VC3 data enable 33 enabled only for the VC3 frame part. And receiving VC3 data 31 of 19.44 Mbps speed in the form of three multiplexed as shown in FIG. 4 (a) and demultiplexing the multiplexed VC3 data to select one VC3 data 35 as shown in FIG. 4 (c). The VC3 path overhead processor 330 extracts and processes the VC3 path overhead POH from the VC3 data 35, and sends the H4 byte status signal 47 to the timing generator 600 as a result. .

In addition, the TUG demultiplexer 320 separates the seven TUG2 signals 41 and sends them to the TU1 signal demultiplexer 410 of the TUG signal processing unit 400, which is composed of seven, respectively, 28 TU11 signals or 21 TU12 signals 42. Demultiplexed into the TU frame aligner 420.

In addition, the TU frame aligner 420 is composed of four for TU11 and three for TU12 for one TUG2, and the TU1 mode can be selected for each TUG2.

Therefore, up to 28 for TU11 and up to 21 for TU12.

The operation according to the TU1 mode is automatically operated without a separate control process by the timing signal 66 generated by being selected according to the mode in the timing generator 600.

The TU frame aligner 420 receives the respective clock timings according to the TU11 and TU12 modes from the timing generator 600 and the pointer interpreter 430 according to the state signal of H4 byte as shown in the second (b). The TU1 frame is separated at the timing 66 to process the TU1 pointers V1, V2, and V3 bytes as shown in FIG. 2C. As a result, the VC1 frame and the VC1 offset timing signal 43 are extracted and the pointer buffer is extracted. 440 and the VC1 monitor 470.

The VC1 monitor 470 performs a path overhead monitoring function for the VC11 / VC12 signals.

The VC11 / VC12 signal extracted from the pointer interpreter 430 and the offset 43 are aligned through the pointer buffer 440, and a new pointer value according to the offset timing 44 in the pointer generator 450. Regenerate the TU11 / TU12 signal frame.

The four TU11 or three TU12 signals arranged as described above are multiplexed in the TU1 multiple part 460 to form the TUG2 signal 46. The TUG processing unit 400 is output from each TUG processing unit 400. A total of 29 TU11 or 22 TU12 signals are output in a multiplexed form 38 by combining the two TUG2 signals 46 and one dummy TU11 / TU12 signal.

On the contrary, the upstream stage receives the data 51 having the same form as the output to the downstream stage and demultiplexes the input data 360 to process a 6.48M level signal corresponding to itself.

From the 29 multiplexed TU11 signals (22 in the case of TU12) included in the signal, VC3 path overhead is inserted into 28 TU11 or 21 TU12 signals except one dummy TU11 / TU12 channel to form a VC3 frame. Output

In the case of the Unequipped state for VC11 / VC12, the function inserts a corresponding signal label value.

It is 3-state controlled and outputs a 19.44M level signal multiplexed externally.

Referring to FIG. 3, for the downstream end, J1, B3, C2, G1, F2, H4, and F3 bytes of VC3 POH are separated from VC3 data and offset timing, wherein J1 is a byte for path tracking 16 bytes. After accumulating each other, CPUs can be read when necessary, i.e. when an error occurs in the path connection state.

The C2 is a path signal level (signal label), which normally indicates a TUG structure. When the signal is unequipped, that is, when a value of 00000000 is detected for five consecutive frames, a UNEQ state is generated. Release it.

In addition, G1 is a path status information byte, and upper bits 1 to 4 indicate REI (Remote Error Indication), and fifth bit indicates RDI (Remote Defect Indication) information. If 0 is detected for 3 consecutive frames, it is cleared.

The REI information is read by the CPU and the RDI status is reported to the CPU immediately upon occurrence / release.

The B3 is an error performance monitoring byte. The value calculated from the BIP-8 for the current frame is compared with the value of B3 of the next frame. When an error occurs, the value is accumulated and immediately reported to the CPU when the specified threshold is reached. Inserts into the REI of the other transmitting POH.

H4 is used to find the position (V1, V2, V3, V4) of the TU1 frame by decoding the received value for multi-frame recognition.

F2 and F3 allow data to be taken from outside for the user.

Conversely, POH is inserted into the VC3 signal at the upstream and transmits it. The CPU receives the information from the CPU and inserts it.In order to monitor the error performance, the BIP-8 for the entire VC3 frame is calculated and the next frame is used. Insert it into position B3.

In the synchronous transmission network, a pointer synchronization concept compensates for a clock difference between signals inputted and outputted in order to prevent loss of a transmission signal when the network node deteriorates or loses its network synchronizer performance.

The pointer indicates the starting point of each VCn when VCn (n = 1,3) on the upstream is multiplexed on the payload of the higher VCn + 1 or STM-1 frame in transmission signal format, and on the downstream stream. When the upper VCn + 1 or STM-1 is demultiplexed to the lower VCn it serves to inform the starting point.

In this case, when the VCn signal unit in STM-1 is multiplexed to another STM-1, when the input STM-1 clock and the output STM-1 clock are operated as independent clocks, the difference between the VCn clocks included in the STM-1 is in bytes. Compensation is made by adjusting the pointer value, i.e. positive / zero / sub stuffing technique.

Therefore, the above pointer processing is largely composed of a pointer interpreter PI, a pointer buffer PB, and a pointer generator PG, and the pointer is classified into an AU pointer as a fast pointer and a TU pointer as a slow pointer.

The function for TU frame alignment in a synchronous multiple system is configured as shown in FIG.

The pointer interpreter 430 determines the state by interpreting the pointer. The pointer interpretation state is defined as three states of NORM, AIS, and LOP, and when the NORM_state in which the pointer is in a normal state occurs NDF_enable or 3 × norm_point is input. Alternatively, it is defined when incr_ind / decr_ind occurs.

If AIS_ind is generated three consecutive frames in the steady state, the state transitions to the AIS state by satisfying the 3xAIS_ind condition and does not return to the normal state unless 3xnorm_point or NDF_enable is generated.

In addition, if inv_point or NDF_enable occurs continuously for 8 frames in the normal state, the state transitions to the LOP state, and does not return to the normal state unless 3 × norm_point or NDF_enable occurs.

When the AIS_ind signal is input for three consecutive frames in the LOP state, the signal transitions to the AIS state. If the inv_point occurs for eight consecutive frames in the AIS state, the state transitions to the LOP state.

The pointer buffer 440 buffers the difference between the write clock and the read clock. The pointer buffer 440 compares the phases of the two clocks and, if there is a difference, gaps the read clock from the PJ to buffer the buffer. In P / N (Positive / Negative) Justification occurs.

The buffer for the above should have a reasonable size, 2 bytes for the gap allocated for overhead (V1, V2, V3, V4), 1 for the gap by receiving P / N Justification. A byte, a gap according to transmission P / N justification, one byte, and four bytes for jitter and wonder absorption are required, requiring a total of eight bytes.

In addition, the pointer generation unit 450 generates a TU pointer according to the rearranged data and the TU offset through the pointer interpretation and buffer, and inserts the TU pointer into the corresponding frame.

As described above, in the present invention, the pointer analyzer for one TU1 signal, the pointer buffer and the pointer generator, 28 in the case of TU11 and 21 in the case of TU12 operate independently of each other.

Maintenance information of the TU1 frame includes TU-AIS / LOP alarm detection and TU-PPJC / NPJC performance information monitoring.

The TU-AIS occurs when the TU1 signal is all 1 and when the TU1 pointer values (V1, V2) are all 1 consecutively three times, and the TU-LOP is generated when the 8th invalid pointer value and the NDF-enable state. .

The UP-PPJC accumulates the P / N Justification when it occurs and allows the CPU to read it.

The VC1 path signal monitoring function extracts and processes the VC1 path overhead. The VC1 path overhead is for indicating the state of the VC1 signal present in the TU11 / TU12 frame.

The overhead is determined by the pointer position clock (2 ms) in the TU11 / TU12 pointer analyzer (PI) to determine the position in the TU11 / TU12 frame.

The signal monitoring function processed by the VC1 monitor 470 processes unmounted signal termination (LSUT-Sink, LSUT-Source) and path monitoring (LPOM) functions among the functions recommended by ITU-T G.783.

The LSUT-Sink function monitors the unequipped state of the VC1 signal input to the TU switch, and the LPOM function extracts the path overhead in the received VC1 signal to monitor and collect state information. Do this.

In addition, the LSUT-Source function processes a function of inserting and transmitting an unequipped signal into the VC1 signal output from the TU switch stage 200.

The structure of the VC1 path overhead is as shown in (d) of FIG. 2 and is processed as follows.

First, the BIP-2 bit is an error performance monitoring bit of the VC1 frame. After calculating the BIP-2 of the current VC1 frame, it compares it with the received BIP-2 value and accumulates it when the difference is reached. When the specified threshold is reached, the uP interface ( (800) to the CPU.

The REI bit is transmitted by the other station for error monitoring on BIP-2 transmitted by the other party, which enables the CPU to read it at any time.

In addition, RDI bit is a bit that the other party transmits severe signal reception failure status of the other party and alarm such as TU-AIS, and when it receives 1 consecutive 5 times, it generates an alarm and reports it to CPU immediately.

The next RFI bit indicates the other party's severe signal reception failure status. When R1 is received 5 times consecutively, an alarm is generated and immediately reported to the CPU.

The signal label bit is composed of 3 bits and indicates unequipped / equipped status. If a 000 value is received for five consecutive frames, it declares an LP-UNEQ status and reports it to the CPU. If the value is not 000 for 5 consecutive frames, the signal unloaded state is canceled and reported to the CPU.

When the TU1 data input in FIG. 3 passes through the pointer analyzer 430, the VC1 data and the VC1 frame offset (2 ms) timing are extracted, and the VC1 path overhead is separated and processed.

If the value of Signal Label is 3 consecutive frames 000, it generates LP-UNEQ status, which means that the signal of the corresponding VC1 path is not installed and only the payload is for Idle status or monitoring. Indicates data state.

At this time, the monitoring state mode is changed from the general path monitoring state (LPOM) to the unmounted signal monitoring state (LSUT-Sink).

On the contrary, the TU1 data received from the TU switch is simply passed in the normal state, that is, the switch connection state, and operates in the LSUT-Source mode under the control of the CPU in the non-connected state.

In this case, the VC1 frame and the TU1 frame may be generated by itself, a signal level (Signal Label) may be inserted into a 000 value, and the payload data may include specific monitoring data.

The present invention configured and operated as described above has a timing generator for generating a clock for each of TU11 and TU12 modes in TU unit signal frame alignment and monitoring, and adds a mode selection function that can be selected and used using a mux. Therefore, the TU11 / TU12 signal can be accommodated, and when the VC1 signal is not present, it has the effect of monitoring and inserting the unconnected state.

The present invention terminates the VC3 signal from the higher signal STM-n to perform TU11 and TU12 unit cross-connect switching in a synchronous line distribution system (SDH-DXC). Rearrange the signal frames to enable switching, monitor the path overhead for the VC11 and VC12 signals to determine the state of the signal path at the front of the switch, and when the VC11 and VC12 signals are not present at the rear of the switch, that is, the switch connection signal. Its purpose is to enable the use of signal paths for protection switching or monitoring by preserving unconnected signal paths when no signal is available.

Claims (12)

In synchronous line distribution (SDH-DXC), which performs line distribution and branch / combination functions of a broadband transmission network, the VC3 demultiplexer 310, the TUG demultiplexer 320, the VC3 path overhead processor 330, and the TU1 signal frame. Insertion of the lower stage input unit consisting of the aligner 400 and the TU1 multiple unit 340, the TU1 demultiplexer 360, the signal monitoring and the TU1 frame forming unit 520, the TUG multiple unit 370, and the VC3 path overhead insertion. Signal frame alignment and signal monitoring, characterized in that it comprises an upstream output unit consisting of a unit 380 and the VC3 multiple output unit (390), a timing generator (600), and a micro interface unit (800). The signal frame arrangement of claim 1, wherein the VC3 demultiplexer 310 extracts one VC3 data by inputting an STM-1 signal frame including three multiplexed VC3 data in parallel signal form. And signal monitoring. The method of claim 1, wherein the TUG demultiplexer 320 demultiplexes TUG2 data from one piece of VC3 data received from the VC3 data input unit and delivers each TUG2 data to a TU1 signal frame aligner. Signal monitoring. The signal frame alignment and signal monitoring according to claim 1, wherein the VC3 path overhead processor (330) receives VC3 data from the VC3 demultiplexer and extracts and processes VC3 path overhead. [2] The signal frame alignment and signal monitoring according to claim 1, wherein the micro interface unit 800 interfaces with the CPU to transmit control signals of the CPU to each part, and report status signals of each part to the CPU. The signal frame alignment of claim 1, wherein the TU1 signal frame aligner 420 receives one TU11 or TU12 signal from the TU1 signal separator 410 to process a TU1 pointer to rearrange the TU1 signal frame. And signal monitoring. The signal frame arrangement and signal monitoring according to claim 1, wherein the data output unit (340) receives the TUG2 signal from the TUG2 multiplexer and forms a signal format as shown in FIG. The signal frame alignment and signal monitoring according to claim 1, wherein the TU1 demultiplex input unit (360) separates seven TUG2 data from the signal format. The signal frame alignment and signal monitoring according to claim 1, wherein the TUG multiplexer 370 multiplexes the TU1 data coming from the signal selector into four in the case of TU11 and three in the case of TU12. The VC3 data output unit 390 multiplies the data input from the TUG2 multiplexer and the VC3 path signal input from the VC3 path overhead inserter to form VC3 data as shown in FIG. 4 (b). Signal frame alignment and signal monitoring, characterized in that for forming and outputting the signal format. 2. The timing generator 600 generates a TU11 related timing and a TU12 related timing using a 19.44 MHz clock and a 2 ms reference timing, and the TU11 timing signal 64 or the TU12 by the mode selection signal 63. Signal frame alignment and signal monitoring, characterized in that for selecting the timing signal 65 and supplying it to each part. The TU1 frame forming unit 520 receives the VC1 data and the TU1 pointer from the VC1 data forming unit 540 that generates the VC1 data and the TU1 pointer forming unit 530 that generates the TU1 pointer. And a signal selector 560 which forms a TU1 frame and includes TU1 data coming from the TUG demultiplexer and TU1 data generated by the TU1 frame forming unit up to a signal selector 560. Signal monitoring.