KR100315891B1 - Data processing circuit of fiber optic transmission system - Google Patents

Abstract

The present invention relates to a data processing apparatus for converting AU-3 data of a parallel stream into AU-3 data of a serial stream and AU-3 data of a serial stream into AU-3 data of a parallel stream in an optical transmission device.

The apparatus of the present invention includes a clock converter 210 for receiving a system clock and generating a required first clock; A frame pulse generator 231 for receiving a first clock and generating frame pulses; A divider 232 and 238 for dividing the system clock and the first clock to generate a second clock; A parallel data alignment unit 233 for sorting the input AU-3 parallel data; A data converter 234 for converting the input AU-3 parallel data into three groups according to the second clock; A mapping unit 235 for mapping AU-3 data to frame pulses of the system or frame pulses of the frame pulse generator; A parallel-serial converter 236 for converting parallel data in series; Including an serial data aligning unit 237 for aligning serial data according to a system clock, the optical transmission device may locally provide a clock for the commercial chip 220 and synchronize frame pulses.

Description

DATA PROCESSING CIRCUIT OF FIBER OPTIC TRANSMISSION SYSTEM}

The present invention provides a data processing apparatus for converting management unit-3 (AU-3) data of a parallel stream into AU-3 data of a serial stream and converting AU-3 data of a serial stream into AU-3 data of a parallel stream in an optical transmission device. It is about.

In general, the multiplexer in the synchronous optical transmission device receives a management unit signal output from the slave unit and a slave unit for outputting a control unit signal (AU-3 or AU-4) transmitted from the subscriber side by time slot switching. And a high speed unit configured to multiplex the management unit signals output from the branch / combination unit into a synchronous transport module signal STM having a predetermined size. The multiplexed data is then transmitted through the optical cable through the optical transmitter.

In this synchronous optical transmission system, the clock of the system is generated by the system clock generator and provided to each unit. In general, in the case of the 2.5G optical transmission system, the system clock is 51.84 MHz and the frame pulse (FP: 8KHz). Is used.

On the other hand, some commercial chips require 19.44MHz as an operation clock. When implementing a multiplexing board using such commercial chips, it is necessary to provide a required clock by modifying a system clock board.

However, when modifying the system clock board, there is a problem that the cost of the design change is increased because the whole system is required to be changed. In order to solve this problem, it is necessary to generate the required clock by converting the system clock locally in the multiplexing board where commercial chips are used. In this case, the frame pulse provided from the system and the frame pulse caused by the newly generated request clock do not match. There is a problem.

Accordingly, the present invention has been made to solve the above problems, and when using a commercial chip that operates with a clock that can not be provided by the system clock unit, the optical transmission apparatus that can provide a local demand clock and match the frame pulse To provide a data processing circuit of the purpose.

In order to achieve the above object, an apparatus of the present invention includes a clock converter for generating a first clock required by receiving a system clock; A frame pulse generator configured to receive the first clock and generate frame pulses; A divider for dividing the system clock and the first clock to generate a second clock; A parallel data alignment unit for sorting the input AU-3 parallel data; A data converter converting the input AU-3 parallel data into three groups according to the second clock or vice versa; A mapping unit for mapping AU-3 data to frame pulses of the system or frame pulses of the frame pulse generator; Parallel-to-serial / serial-parallel conversion means for converting parallel data in series or serial data in parallel; The optical transmission device may include a serial data aligning unit for aligning serial data according to a system clock, and may provide a clock for a commercial chip, and synchronize frame pulses.

1 is a schematic configuration diagram of a general optical transmission device;

2 is a block diagram showing a data processing circuit of the present invention applied to a transmission portion of an optical transmission device;

3 is a block diagram showing a data processing circuit of the present invention applied to the receiving portion of the optical transmission device;

4 is a timing diagram illustrating a clock of a data processing circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

210: clock converter 220: commercial chip

231: frame pulse generator 232,238: divider

233: parallel data alignment unit 234: data conversion unit

235: mapping unit 236: parallel-to-serial conversion unit

237: serial data alignment unit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a general optical transmission device. Referring to FIG. 1, the optical transmission apparatus forms an STM-1 signal by multiplexing a DS3 signal to form an STM-1 signal or vice versa, and forms an STM-N signal by multiplexing an output of the slave unit 110. The high speed multiplexer 120 operating in the reverse direction, the optical transmitter / receiver 130 for converting an STM-N signal into an optical signal or an STM-N signal, a system controller 140 and a system clock generator 150 It is composed of Subordinate unit 110 is composed of a plurality of low-speed multiplexing unit (111, 112, 113), the system control unit 140 controls the operation of each unit and provides an interface with the operator, the system clock generator 150 is at least 8KHz In addition, the system clock of 51.84MHz is generated and provided to each part.

2 is a block diagram showing a data processing circuit of the present invention applied to the transmitting portion of the optical transmission device. As shown in FIG. 2, the data processing circuit of the present invention includes a clock converter 210, a commercial chip 220, a frame pulse generator 231, a first divider 232, and a parallel data aligner 233. ), A data conversion unit 234, a mapping unit 235, a parallel-serial conversion unit 236, a serial data alignment unit 237, and a second divider 238. In the drawing, the frame pulse generator 231, the divider 232 and 238, the parallel data aligner 233, the data converter 234, the mapper 235, the parallel-serial converter 236, The serial data alignment unit 237 is simply implemented by a programmable device (FPGA).

The clock converting unit 210 receives a 51.84 MHz system clock and an 8 KHz frame pulse (FP) from the clock generation unit 150 of FIG. 1 and generates a 19.44 MHz clock required by a commercial chip.

The commercial chip 220 processes the input data while operating according to the clock (19.44 MHz) input from the clock converter 210 and the frame pulse FP 'input from the frame pulse generator 231 to process the AU-3 parallel. Output the data. At this time, the frame pulse FP 'and 19.44MHz clock for the output data are also output.

The frame pulse generator 231 generates an 8 KHz frame pulse FP ′ to be provided to the commercial chip 220 from 19.44 MHz input from the clock converter 210, and the first divider 232 is a commercial chip. The 19.44 MHz system clock used at 220 is divided and outputs a clock of 6.48 MHz.

The parallel data sorter 233 sorts the AU-3 parallel data input from the commercial chip 220 according to the frame pulse FP 'and the clock (19.44 MHz), and the data converter 234 is a parallel data sorter. The AU-3 parallel data input from 233 is converted into three groups according to the clock (6.48 MHz) of the first divider 232. The second divider 238 divides the 51.84 MHz clock provided from the system to output a 6.48 MHz clock, and the mapping unit 235 receives the 6.48 MHz clock synchronized with the system from the second divider 238 to receive data. The output of the converter 234 is mapped to output data synchronized with the system clock, and the parallel-serial converter 236 receives the parallel data of the mapping unit 235 and converts the serial data to serial. The serial data sorting unit 237 sorts the serially converted data. At this time, the frame pulse after the mapping unit 235 is a frame pulse FP provided by the system, and the clock is a clock synchronized with the system clock.

3 is a block diagram showing a data processing circuit of the present invention applied to the receiving portion of the optical transmission device. As shown in FIG. 3, the data processing circuit of the present invention includes a clock converter 310, a commercial chip 320, a frame pulse generator 331, a first divider 332, and a parallel data aligner 333. ), A data conversion unit 334, a mapping unit 335, a serial-parallel conversion unit 336, a serial data alignment unit 337, and a second divider 338. This configuration is basically the same as that of the transmission unit, except that the data flow is reversed from the case of transmission.

Referring to FIG. 3, the clock converter 310, the frame pulse generator 331, and the first and second dividers 332 and 338 are the same as in the case of transmission, and the commercial chip 320 processes the received data. To other parts of the system. The serial data aligning unit 337 receives the received serial data and the frame pulse FP and aligns them according to the system clock and the frame pulse, and the serial-parallel converter 336 is input from the second divider 338. Convert serial data to parallel data according to 6.48MHz clock. The mapping unit 335 maps parallel data synchronized with the system to synchronize the frame pulse generator 331 with the same frame pulse generator 331 as the frame pulse used in the commercial chip 320, and the data converter 334. ) Receives the 6.48 MHz clock of the first divider 332 and the 19.44 MHz clock used in the commercial chip 320, converts three groups of data into one AU-3, and parallel data alignment unit 333. ) Arranges the parallel data and provides the same to the commercial chip 320.

4 is a timing diagram illustrating a clock of a data processing circuit according to the present invention. FIG. 4A illustrates a 51.84 MHz system clock provided by a system clock generator, and FIG. Represents a 19.44 MHz clock, and (c) represents a 6.48 MHz clock required for data conversion in accordance with the present invention. And (d) represents a frame pulse of 8 KHz.

In the system, the AU-3 data is transmitted in synchronization with a 51.84 MHz system clock as shown in FIG. 4A, which is not supported by the system clock (eg, 19.44 MHz as shown in FIG. 4B). When using a commercial chip 320 that requires a 6.48MHz clock corresponding to the common factor of 51.84MHz and 19.44MHz. And mapping is used to solve the problem that synchronization of frame pulse of commercial chip and frame pulse of system is not matched.

As described above, in the present invention, when a request clock of a commercial chip to process AU-3 data in the optical transmission device is different from a system clock, a locally generated demand clock is generated on a board using the commercial chip, and a frame pulse mismatch is generated. By using the mapping circuit implemented in FPGA, it is possible to simply accept commercial chips without changing the entire design.

Claims (2)

A clock converter configured to receive a system clock and generate a required first clock; A frame pulse generator configured to receive the first clock and generate frame pulses; A divider for dividing the system clock and the first clock to generate a second clock; A parallel data alignment unit for sorting the input AU-3 parallel data; A data converter converting the input AU-3 parallel data into three groups according to the second clock or vice versa; A mapping unit for mapping AU-3 data to frame pulses of the system or frame pulses of the frame pulse generator; Parallel-to-serial / serial-parallel conversion means for converting parallel data in series or serial data in parallel; And A data processing circuit for an optical transmission apparatus, comprising a serial data alignment unit for arranging serial data according to a system clock and providing a clock for a commercial chip in the optical transmission apparatus and synchronizing frame pulses. The apparatus of claim 1, wherein the frame pulse generator, the divider, the parallel data alignment unit, the data conversion unit, the mapping unit, the parallel-serial / serial-parallel conversion unit, and the serial data alignment unit are implemented with the same programmable device (FPGA). And a data processing circuit of the optical transmission device.