KR19990042556A - Synchronous clock generator - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to an apparatus for generating a synchronous clock for use in a synchronous optical transmission system.

2. The technical gist of the invention to solve

An object of the present invention is to provide a synchronization clock generator that provides a system synchronization clock and a frame synchronization signal using a clock extracted from an external network synchronization clock source or a synchronization transmission mode reception signal that is an internal signal of a system.

3. Summary of the Solution of the Invention

The present invention provides an external synchronization clock receiving means for receiving an external network synchronization clock; Internal synchronous clock receiving means for receiving an internal synchronous clock; Synchronous clock generating means for generating a synchronous clock; And first and second system clock generating means for transmitting the system synchronization clock and the frame synchronization signal.

4. Important uses of the invention

The present invention is used to generate the synchronization clock and frame synchronization signals required for network synchronization in a synchronous optical transmission system.

Description

Synchronous clock generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating a synchronous clock for use in a synchronous optical transmission system, and more particularly, to an apparatus for generating and providing a synchronous clock and a frame synchronous signal required for network synchronization.

Currently, the synchronous clock generating device of the synchronous transmission technology is a technology related to the STM-1, STM-4, STM-16 signal is in use stage, but the synchronous clock generation for generating the 10Gb / s signal, which is the STM-64 level signal The device is in an empty state.

In general STM synchronization clock generators, since there are not many slave signal processing units, the high speed signal processing unit or the slave signal processing unit does not independently process the clock and frame synchronization signals, but the slave signals used in the 10Gb / s synchronous optical transmission system are conventional. The high speed signal processing unit and the dependent signal processing unit are still difficult to exist in the same position because they are relatively large compared to the dependent signal capacities processed in the STM-1, STM-4, and STM-16 systems.

Accordingly, the present invention has been made to solve the above problems, the system synchronization clock and frame synchronization using the clock extracted from the external network synchronization clock source, which is a synchronous clock source input signal or the synchronous transmission mode reception signal, which is a system internal signal. It is an object of the present invention to provide a synchronous clock generator that provides a signal, monitors an alarm for a selected clock to increase the reliability of the input synchronous clock, and performs an input synchronous clock switching when a problem occurs in the selected clock.

1 is a block diagram illustrating a configuration of an optical transmission system to which the present invention is applied.

2 is a block diagram of an embodiment of a synchronous clock generator according to the present invention;

Explanation of symbols on the main parts of the drawings

10: slave signal processor 20: high speed signal processor

30: synchronous clock generator 40: external network clock source

Synchronous clock generating apparatus of the present invention for achieving the above object, the external synchronization clock receiving means for receiving an external network synchronization clock which is a system external signal from the external synchronization clock source; Internal synchronization clock receiving means for receiving an internal synchronization clock extracted by an external slave signal processor and a high speed signal processor; Clock selecting means for selecting one of the clocks received through the external synchronous clock receiving means and the internal synchronous clock receiving means; Synchronous clock generating means for generating a synchronous clock using a clock selected from the clock selecting means; And first and second system clock generating means for receiving a synchronous clock generated from the synchronous clock generating means to generate a system synchronous clock and a frame synchronous signal and to transmit the system synchronous clock and the frame synchronous signal to the dependent signal processor and the high speed signal processor, respectively.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 and 2.

Referring to FIG. 1, the optical transmission system according to the present invention includes a slave signal processor 10, an STM-64 high speed signal processor 20, and a synchronous clock generator 30.

The slave signal processor 10 includes a plurality of STM-N slave signal processors 10-1 to 10-n for transmitting a plurality of received STM-N optical signals as low-speed electric signals. = 1, 4, 16)

The synchronous clock generator 30 includes an external synchronous clock receiver 31 for receiving an external network synchronous clock signal DS1E, which is a system external signal, from the external synchronous clock source 40, and the slave signal processor 10 or a high speed signal. Selecting one of the clocks received through the internal synchronous clock receiver 32 and the external synchronous clock receiver and the internal synchronous clock receivers 31 and 32 for receiving the internal synchronous clock extracted by the processor 20. A clock selector 33 for inputting a synchronous clock generator 34 to generate a synchronous clock using the clock selected by the clock selector 33, and a synchronous clock generated from the synchronous clock generator 34. The first and second system clock generators 35 and 36 generate a synchronous clock and a frame synchronous signal FS and transmit the synchronized clock and the frame synchronous signal FS to the slave signal processor 10 and the STM-64 high speed signal processor 20, respectively.

The operation of the optical transmission system having the structure as described above will be described in detail as follows.

The slave signal processor 10 receives a plurality of STM-N optical signals to process the overhead of the STM-N frame, demultiplexes the plurality of STM-N optical signals into low-speed signals, and converts the electrical signals to the STM through the backplane or cable. -64 is sent to the high speed signal processing unit 20. The STM-64 high speed signal processor 20 multiplexes a low-speed electric signal transmitted from the slave signal processor 10 into a 10Gb / s signal to convert an overhead insertion of the STM-64 frame and the multiplexed 10Gb / s signal into an optical signal. To print.

Subsequently, the synchronous clock generator 30 may be synchronized with the external network synchronous clock, and may also be synchronized with the synchronous STM-M system (where M = 1, 4, 16, and 64). The external network synchronization clock DS1E is received from the 40 through the external synchronization clock receiver 31, and the STM- is received through the internal synchronization clock receiver 32 and the 8KHz clock extracted from the received external network synchronization clock DS1E. One clock is selected from the 8 KHz clock signal, which is a 10 Gb / s system internal signal received from the 64 high-speed signal processor 20, through the clock selector 33, and by using the selected clock, the synchronous clock generator 34 generates a synchronous clock. Create In addition, the slave signal processor 10 and the STM-64 high speed signal processor 20 may be located at different locations, and if they are located at the same location as the synchronous clock generator 30, the slave signal processor 10 and the STM-64 high speed signal processor 20 may transmit the high speed clock. The first system clock generator 35 of the synchronous clock generator 30 transmits the system synchronous clock and the frame synchronous signals SYS_CLK1 and FS1 to a plurality of slave signal processors 10 so that they can be transmitted at a low speed clock when located at a long distance. STM-N slave signal processors 10-1 to 10-n, respectively, and the second system clock generator 36 transmits the system synchronization clock and frame synchronization signals SYS_CLK2 and FS2 to the STM-64 high speed signal processor. (20).

On the other hand, the external synchronous clock receiver 31 detects an alarm from a system external signal and transmits a system external signal frame alarm signal.

An embodiment of the synchronous clock generator of FIG. 1 will be described in detail with reference to FIG. 2.

Referring to FIG. 2, the synchronous clock generator of FIG. 1 includes a first divider 34-1 which divides an 8 KHz clock received from the clock selector 33 into 8 kHz and outputs a 1 KHz reference clock. A phase comparator 34-3 which outputs a phase comparison value by comparing the phases of the 1 KHz reference clock and the 1 KHz comparison clock transmitted from the first and second dividers 34-1 and 34-2, respectively; A / D conversion that outputs a phase comparison value of a predetermined bit (16 bits) by converting an analog phase comparison value received from the phase comparison unit 34-3 into digital according to a clock output from the division unit 34-4. Receives a phase comparison value of a predetermined bit from the unit 34-5 and the A / D converter 34-5, compares and detects the phase difference between the reference clock and the comparison clock, and outputs the synchronous clock according to the phase difference detection result. A processor unit 34-6 for outputting a synchronous clock adjustment signal of a predetermined bit (16 bits) for adjusting the signal; D / A converter 34-7 and analog sync output from D / A converter 34-7 for converting the synchronous clock adjustment signal of the predetermined bit output from -6) to an analog synchronous clock adjustment signal. The synchronous clock output section 34-8 for outputting the synchronous clock according to the clock adjustment signal and the synchronous clock generated from the synchronous clock output section 34-8 are divided so that the 1 KHz comparison clock is subjected to the phase comparison section 34-3. The second divider 34-2 and the synchronous clock generated from the synchronous clock output 3434 are divided to output the divided synchronous clocks to the A / D converter 34-5. It is provided with three division parts 34-4.

The first and second system clock generators of the synchronous clock generator of FIG. 1 include a fourth divider 35-1 for dividing the synchronous clock output from the synchronous clock generator 34 and the synchronous clock generator 34. A fifth divider 35-2 for dividing the synchronous clock output from the second divider; and a sixth divider 35-3 for dividing the synchronous clock output from the fifth divider 35-2. According to the system clock selection signal output from the processor unit 34-6, the clocks transmitted from the fourth to sixth division units 35-1, 35-2, and 35-3 are selected, respectively, and the first and second units are selected. A system clock selector 35-4 and a system clock selector 35-4 for outputting the system synchronization clocks SYS_CLK1 and SYS_CLK2 to the slave signal processor 10 and the STM-64 high speed signal processor 20, respectively. Subordinate signal processing of the first and second frame synchronization signals FS1 and FS2 by receiving the first and second system synchronization clocks SYS_CLK1 and SYS_CLK2 outputted from the respective signals. And a 10 and STM-64 high-speed signal processing section 20, the first and the second frame synchronization signal generation unit (35-6, 35-7) for outputting a.

The operation of the synchronization clock generator of FIG. 1 having the structure as described above will be described in detail as follows.

The synchronous clock generator 34 compares the reference clock output from the first divider 34-1 and the second divider 34-2 using the phase comparator 34-3 to generate the synchronous clock. In the present invention, in order to compare the reference clock with the comparison clock at 1 KHz, the 8 KHz clock selected by the selected clock selector 33 is divided into eight by the first divider 34-1. A 1 kHz reference clock is generated, and a 155 MHz synchronous clock outputted from the synchronous clock output unit 34-8 is divided by 19940 X 8 using the second divider 34-2 to generate a 1 kHz comparison clock.

In addition, since the phase comparison value compared through the phase comparison unit 34-3 should be a digital value, the third division unit 34-4 outputs the 155.52 MHz synchronous clock output from the synchronous clock output unit 34-8. 4 divided by 4 to output the 38.88 MHz clock to the A / D converter 34-5, and then the A / D converter 34-5 is connected to the 38.88 MHz clock output from the third divider 34-4. Accordingly, the phase comparison value output from the phase comparison unit 34-3 is converted, and the 16-bit phase shift value is transmitted to the processor unit 34-6.

Subsequently, the processor unit 34-6 compares the rising edges of the comparison clock and the reference clock divided at 1 KHz to compensate for the detected phase difference. When the synchronization clock is fast, the 16-bit read signal LEAD or the synchronization clock is slow. The 16-bit lag signal LAG is output, and the read signal or lag signal thus output is converted into an analog value through the D / A converter 34-7 and transferred to the synchronous clock output unit 34-8. . When the read signal is transmitted, the synchronous clock output unit 34-8 slows the output speed of the output synchronous clock. On the contrary, the synchronous clock output unit 34-8 outputs the synchronous clock output when the lag signal is transmitted. Speed up

By using the 155.52 MHz synchronous clock output from the synchronous clock generator 34, the first and second system clock generators 35 and 36 generate 77.76 MHz, 51.84 MHz, and 38.88 MHz system clocks and frame signals FS required for the system. Create The 77.76 MHz system clock is divided into two 155.52 MHz clocks using the fifth divider 35-2, and the 51.84 MHz system clock divides the 155.52 MHz clock into three divisions through the fourth divider 35-1. The 38.88 MHz system clock is a clock obtained by dividing the 77.76 MHz clock into two by using the sixth divider 35-3. The clock required by the slave processor 10 and the STM-M high-speed processor 20 is provided. After determining the selection system clock at initial startup, the system clock selection unit 35-4 determines the selection system clock according to the 3: 2 system clock selection signal output from the processor 34-6.

The first frame synchronizing signal generator 35-6 uses the system clock selected by the system clock selector 35-4 to convert the system synchronizing clock SYS_CLK1 and the first frame synchronizing signal FS1 into a slave signal processor ( 10), and the second frame synchronization signal generator 35-7 also uses the system clock selected by the system clock selector 35-4 and the system synchronization clock SYS_CLK2 and the second frame synchronization signal ( FS2) is sent to the STM-64 high speed signal processing unit 20. As described above, in the present invention, by using the system clocks SYS_CLK1 and SYS_CLK2 and the first and second frame synchronization signals FS1 and FS2, the 10Gb / s optical transmission system of the present invention can synchronize with an external synchronization network. Will be.

In order to synchronize the other synchronous STM-M (M = 1, 4, 16, 64) system and the 10Gb / s optical transmission system of the present invention, the STM-M reception signal of the 10Gb / s optical transmission system is used as a synchronous clock source. The 8KHz clock extracted from or an external network synchronization clock DS1E output from the external network synchronizer clock source 40 may be used. According to the type of the synchronous clock source, the external synchronous clock receiver 31 and the internal synchronous clock receiver 32 are configured. The internal synchronous clock receiver 32 is an STM-N slave signal processor 10 that receives a 10 Gb / s signal as a receiver that receives an 8 KHz clock extracted from the slave signal processor 10 or the STM-64 high speed signal processor 20. And STM-64 high speed signal processing unit 20, but if the slave processing unit 10 processes the STM-N signal in units of 2.5Gb / s signal, four and STM-64 high speed signal processing unit 20 L is required. L is 1 for high-speed signal processing, but 2 L is required for a branch-coupled system with two-wire bidirectional line switching ring network. In addition, when the synchronous clock source is used as an external synchronous clock, the external synchronous clock receiver 31 receives the external network synchronous clock DS1E from the external synchronous clock source 40, extracts an 8 KHz clock from the signal, and outputs the output. A synchronous clock and frame synchronous signal can be generated from one clock.

The external synchronous clock receiver 31 and the internal synchronous clock receiver 32 monitor the presence or absence of an alarm for the selected clock in order to increase the reliability of the synchronous clock input to the synchronous clock generator. If there is a problem in the received 8KHz clock, the internal synchronous clock receiver 32 generates an internal clock alarm signal and transmits it to the processor 34-6. In addition, the external synchronous clock receiver 31 detects an alarm from the external network synchronous clock DS1E and transmits an external network synchronous clock frame alert signal to the processor 34-6 to receive the alarm. Among the synchronous clock sources, the primary clock source and the secondary clock source can be selected, and the best clock source can be selected.

The reference clock selector 37 uses an 8 KHz clock extracted from an external network synchronizer clock or an STM-M received signal as an input reference clock source. The selection of the reference clock selects the priority of the input reference clock source available at initial startup of the device. After the determination, it is determined by the processor unit 34-6. If two reference clock sources are selected, the first clock source and the second clock source may be generated. As the clock selector 23 selects one best clock among the two selected synchronous clock sources and transmits the same to the synchronous clock generator 34, the present invention reduces the production cost by simplifying the synchronous clock generator 34. Can be.

As described above, the synchronous clock generator according to the present invention performs the monitoring of the selected input external synchronous clock or the internal clock of the 10 Gb / s system and the switching of the input clock when the alarm occurs, thereby generating the clock and frame synchronization. It has the effect of increasing the reliability of the signal.

Claims (3)

External synchronizing clock receiving means for receiving an external network synchronizing clock which is a system external signal from an external synchronizing clock source; Internal synchronization clock receiving means for receiving an internal synchronization clock extracted by an external slave signal processor and a high speed signal processor; Clock selecting means for selecting one of the clocks received through the external synchronous clock receiving means and the internal synchronous clock receiving means; Synchronous clock generating means for generating a synchronous clock using a clock selected from the clock selecting means; And First and second system clock generating means for receiving a synchronous clock generated from the synchronous clock generating means to generate a system synchronous clock and a frame synchronous signal and to transmit the system synchronous clock and the frame synchronous signal to the slave signal processor and the high speed signal processor, respectively; Synchronous clock generation device comprising a. The method of claim 1, The synchronous clock generating means, First dividing means for dividing a clock received from the clock selecting means and outputting a reference clock; Phase comparison means for outputting a phase comparison value by comparing a phase of a reference clock and a comparison clock respectively transmitted from the first and second division means; A / D conversion means for converting a phase comparison value received from the phase comparison means into digital according to a clock output from the third division means and outputting a phase comparison value of a predetermined bit; Receive the phase comparison value of the predetermined bit from the A / D conversion means to compare and detect the phase difference between the reference clock and the comparison clock, and adjust the synchronization clock of the predetermined bit to adjust the output speed of the synchronization clock according to the phase difference detection result. Processor means for outputting a signal; D / A conversion means for converting the synchronous clock adjustment signal of the predetermined bit output from the processor means into an analog synchronous clock adjustment signal; Synchronous clock output means for outputting a synchronous clock in accordance with the analog synchronous clock adjustment signal output from the D / A converting means; The second dividing means for dividing the synchronous clock generated from the synchronous clock output means and outputting the divided comparison clock to the phase comparator; And The third division means for dividing the synchronous clock generated from the synchronous clock output section and outputting the divided synchronous clock to the A / D converter; Synchronous clock generation device comprising a. The method according to claim 1 or 2, The first and second system clock generating means, Fourth dividing means for dividing the synchronous clock output from the synchronous clock generating means into three; Fifth dividing means for dividing the synchronous clock output from the synchronous clock generating means into two; Sixth dividing means for dividing the synchronous clock output from the fifth dividing means into two; Select clocks transmitted from the fourth to sixth division means in accordance with a system clock selection signal output from the synchronization clock generator to output first and second system synchronization clocks to the dependent signal processor and the high speed signal processor, respectively. System clock selecting means for performing; First and second frame synchronization signals for receiving the first and second system synchronization clocks output from the system clock selecting means and outputting first and second frame synchronization signals to the slave signal processor and the high speed signal processor, respectively. Generation means Synchronous clock generation device comprising a.