JP3165117B2 - Subrate asynchronous signal multiplexing method, transmitting apparatus and receiving apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, when multiplexing sub-rate asynchronous data into a zero-order group signal, adds a start bit and a stop bit for each octet of data, and then converts the speed to a bearer speed. The present invention relates to a method of multiplexing a sub-rate asynchronous signal for realizing a zero-order group signal capable of digital addition processing by time-division multiplexing a bearer signal to 64 kbit / s, and a transmitting apparatus and a receiving apparatus.

[0002]

BACKGROUND OF THE INVENTION Asynchronous data of a sub-rate (64 kbit / s or less) such as 300 bit / s or 9600 bit / s is transmitted to a zero-order group signal (DS0
: 64 kbit / s), a method of inserting a subframe synchronization pattern into 64 kbit / s data and multiplexing is common. The operation will be described below by taking a conventional general circuit configuration (FIGS. 3, 4, and 5) as an example.

[0003] An asynchronous sub-rate signal (3-a), for example, a 4800 bps signal, transmitted from the terminal device 1-1 via the serial external interface 21 is received by the serial input / output unit 22 and has a start bit, a stop bit, and a stop bit. After the bits and the parity bits are removed, only the character data is sent to the speed converter 23. (3-
b) The character data received by the speed conversion unit 23 is a sub-rate signal (480) received from the serial input / output unit 22.
It is taken out as an output of the speed conversion unit 23 as a signal of a synchronization system (for example, 8 kbps) having a bearer speed slightly faster than 0 bps), and sent to the next multiplexing unit 24. (3-c) The multiplexing unit 24 multiplexes signals of a plurality (n) of bearer speeds.
Multiplexing is performed as a zero-order group signal of 64 kbit / s, and the multiplexed 0
The next group of signals is inserted with a sub-frame pattern in the subsequent sub-frame insertion unit 25, and then transmitted to the sub-frame synchronization unit 31 of the digital addition processing device 3. (3-d) FIG. 3-d shows an example in which multiplexing is performed in the V.110 frame configuration. The subframe configuration of V.110 is shown in FIG. For simplicity of description, frame bits, fixed patterns, etc. are all represented by "F". "Dn" = "D1"
"D48" is a data bit, "SF0" to "SF9" are subframe numbers, and "b0" to "b7" are bit numbers.

[0004] The digital addition processing device 3 is supplied with zero-order group signals from a plurality of transmission devices (transmission devices 2-1 to 2-n).
After the sub-frames are synchronized, the sub-frames are sent to the digital addition processing unit 32. In the digital addition processing unit 32, after the data at the same bit position are added together (3-e), a subframe is generated by the subframe insertion unit 33 and the subframe pattern is inserted again. It is sent to the receiving device 4.

[0005] The signals 2-1 to 2-n digitally added by the digital adder 3 are received as a single serial data by the sub-frame synchronizer 41 of the receiver 4. After the subframe synchronization and the extraction of the zero-order group signal are performed, the signal is separated into a plurality of signals of the bearer speed by the separation unit 42 that follows. (3-f) The separated bearer speed signal is returned to the sub-rate signal again by the subsequent speed converter 43, and the serial input / output unit 44
Then, a start bit and a stop bit are added again as asynchronous serial data, and transmitted to the terminal device 5 via the external interface 45.

[0006]

As described above, in the conventional method of multiplexing asynchronous signals at a subrate, and in a transmitting apparatus and a receiving apparatus (for example, a multiplexing method using subframes such as X.50 and V.110). In addition, it is necessary to provide the digital addition processing device 3 with the sub-frame synchronization circuit 31 and the sub-frame insertion circuit 33, so that the circuit scale becomes large. -1 is received by the serial input / output unit 22, and after removing the start bit, stop bit, and parity bit, only the character data is transferred to the speed conversion unit 23, that is, the sub-rate signal (4800 bps). ) As a signal of a synchronous system (for example, 8 kbps) with a bearer speed slightly faster than The signal is taken out, then received by the subframe synchronization unit 41 of the receiving device 4, separated into a plurality of bearer speed signals by a separation unit 42, and the separated bearer speed signals are separated by a subsequent speed conversion unit 43. The signal is returned to a sub-rate signal again, and the serial input / output unit 44 again generates a start bit as asynchronous serial data.
Since a method in which a stop bit is added and transmission is performed to the terminal device 5 via the external interface 45 is adopted, it is necessary to provide the transmission device 2-1 and the reception device 4 with the speed conversion units 23 and 43, respectively. , Because a general serial control unit cannot be used
There are problems that the apparatus becomes expensive and the apparatus cannot be downsized.

[0007] The present invention solves the above-mentioned problems and, when multiplexing sub-rate asynchronous data into a zero-order group signal, adds a start bit and a stop bit for each octet of data, and then reduces the bearer speed. A method of multiplexing a sub-rate asynchronous signal capable of realizing a zero-order group signal capable of digital addition processing by performing speed conversion and then time-division multiplexing the bearer signal to a predetermined kbit / s, and a transmitting apparatus And a receiving device.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned object, the present invention firstly converts an asynchronous sub-rate signal sent from a terminal device via an external interface into a first serial input / output unit. After the start bit, the stop bit, and the parity bit are removed, only the character data is taken into the central processing unit via the bus, and sent out to the second serial input / output unit via the bus as it is. After the start bit and the stop bit are added again to the character data received by the serial input / output unit, the character data is taken out as a synchronization type signal of a bearer speed slightly higher than the sub-rate signal received by the second serial input / output unit, and the multiplexing unit. Signals of a plurality of bearer speeds sent from a plurality of second serial input / output units at 64 kbit / s 0
A multiplexing process is performed as a next group signal.

Second, the asynchronous sub-rate signal sent from the terminal device via the external interface is transmitted to the first
After the start bit, stop bit, and parity bit are removed, only the character data is taken into the central processing unit via the bus, and sent out to the second serial input / output unit via the bus as it is. At the same time, a start bit and a stop bit are added again to the character data received by the first serial input / output unit, and then, as a signal of a synchronization system with a bearer speed slightly faster than the sub-rate signal received by the second serial input / output unit. A multiplexing unit transmits a signal obtained by multiplexing signals of a plurality of bearer speeds transmitted from a plurality of second serial input / output units as a 64 kbit / s zero-order group signal.

Third, the multiplexed signal processed by the sub-rate asynchronous signal multiplexing method is converted into one serial data, received by the octet synchronizing section of the receiving device, and after the octet synchronization. The separation unit separates the zero-order group signal into a plurality of bearer speed signals, and sends the separated bearer speed signals to the third serial input / output unit, where the start bit and the stop bit are removed. The start bit and the stop bit are added again as asynchronous serial data at the fourth serial input / output unit via the central processing unit, and the terminal device receives the data via the external interface.

Fourth, the transmitting device includes an external interface connected to the terminal device, a first serial input / output unit for transmitting / receiving an asynchronous sub-rate signal, and a second serial input / output unit for transmitting / receiving data at a bearer speed. An output unit; a central processing unit for sending an asynchronous sub-rate signal received by the first serial input / output unit to the second serial input / output unit;
It comprises a bus connecting the first serial input / output unit, the central processing unit, and the second serial input / output unit, and a multiplexing unit for multiplexing bearer speed data into a zero-order group signal.

Fifth, an octet synchronization unit for performing octet synchronization of individual zero-order group signals from a plurality of transmission devices, and digital addition processing of data at the same bit position synchronized by the octet synchronization unit. The digital addition processing unit constitutes a digital addition processing device when transmitting a multiplexed signal. Sixth, the receiving device performs octet synchronization for octet synchronization of the zero-order group signal, a separation unit for separating octet-synchronized data into bearer speed data, and transmits and receives bearer speed data. A third serial input / output unit, a fourth serial input / output unit for transmitting / receiving an asynchronous sub-rate signal, and transmitting the bearer speed data received by the third serial input / output unit to the fourth serial input / output unit. It comprises a central processing unit, a bus connecting the third serial input / output unit, the central processing unit and the fourth serial input / output unit, and an external interface connected to a terminal device.

Seventh, the central processing unit for transferring data between the first serial input / output unit and the second serial input / output unit in the transmission device according to claim 4 is constituted by a general logic circuit. Eighth, in the receiving device according to the sixth aspect, the central processing unit that performs data transfer between the third serial input / output unit and the fourth serial input / output unit is configured by a general logic circuit. Ninth, the signal output from the second serial input / output unit in the transmitting device is configured to be supplied with a clock and synchronized. Tenthly, the multiplexing unit multiplexes a plurality of bearer speed signals sent from the second serial input / output unit as a 64 kbit / s zero-order group signal, and outputs the octet synchronization unit of the digital addition processing device. To be sent to

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for multiplexing a sub-rate asynchronous signal according to the present invention and a transmitting apparatus and a receiving apparatus employing the method will be described with reference to FIGS. The transmitting apparatus employing the method for multiplexing sub-rate asynchronous signals according to the present invention includes terminal apparatuses 1-1 to 1-n, an external interface 21, and transmitting apparatuses 2-1 to 2-n. The output signal from each transmission device is received by the reception device 4 via the digital addition processing device 3, and is finally sent to the terminal device 5 via the external interface 47.

The transmitting apparatus 2-1 transmits and receives asynchronous sub-rate signals transmitted from the terminal apparatus 1-1 via the external interface 21 to the serial input / output section 22, and transmits and receives bearer speed data. A serial input / output unit 25, a central processing unit 24 for sending an asynchronous sub-rate signal received from the serial input / output unit 22 to the serial input / output unit 25, and a serial input / output unit 22
, The central processing unit 24, the bus 23 connecting the serial input / output unit 25, and the data of the bearer speed to the 0th order group signal (64
(kbit / s).

The digital addition processing device 3 provided between the transmission devices 2-1 to 2-n and the reception device 4 includes:
The octet synchronizing unit 31 and the digital addition processing unit 32 process parallel 0th-order group signals (64 kbit / s) transmitted from each of the transmission devices 2-1 to 2-n in the digital addition processing unit 32. And the zero-order group signal of the series (6
4 kbit / s), and can be transmitted to each receiving device 4.

Further, the receiving device 4 outputs a zero-order group signal (6
Octet synchronization section 4 for octet synchronization of 4 kbit / s)
1, a separating unit 42 for separating octet-synchronized data into bearer speed data, a serial input / output unit 43 for transmitting / receiving bearer speed data, and a serial input / output unit 46 for transmitting / receiving asynchronous subrate signals. A central processing unit 45 for sending bearer speed data received from the serial input / output unit 43 to the serial input / output unit 46;
It comprises a serial input / output unit 43, a central processing unit 45, a bus 44 connecting the serial input / output unit 46, and an external interface 47 connected to the terminal device 5.

A method of multiplexing a sub-rate asynchronous signal according to the present invention and operations of a transmitting apparatus and a receiving apparatus according to the present invention will be described based on the above configuration. First, an asynchronous sub-rate signal (4-a), for example, a 9600 bps signal, transmitted from the terminal device 1-1 via the serial external interface 21 is received by the serial input / output unit 22, and a start bit, a stop bit, After the bits and parity bits are removed, only the character data is taken into the central processing unit 24 via the bus 23. (4-b) The character data captured by the central processing unit 24 is sent to the serial input / output unit 25 via the bus 23 without any processing.

The character data received by the serial input / output unit 25 is added with a start bit and a stop bit again by the serial input / output unit 25, and a sub-rate signal (9600 bps) received from the serial input / output unit 22
Synchronous signals with a slightly higher bearer speed (eg 16
(kbps) to the multiplexing unit 26. (4-c) Note that the serial input / output unit 25 is supplied with the internal clock of the transmission device 2-1, and generally outputs signals (input 1, input 2,..., Input n) therefrom. ) Are all processed in a state synchronized with the transmission device 2-1.

In the asynchronous sub-rate signal (4-a) transmitted from the terminal device 1-1, bit data is generally transmitted in bursts in character units instead of continuous data. . Therefore, while data is not transmitted, that is, between data characters, the data of the mark signal (logical "1") is continuously transmitted from the serial input / output unit 25. (4-
c) The multiplexing unit 26 multiplexes a plurality of bearer speed signals sent from the serial input / output unit 25 as a 64 kbit / s zero-order group signal, Send out.

A general multiplexing method is shown in 4-d. 4-d
In this example, four 16 kbps bearer signals are time-division multiplexed into one 64 kbit / s zero-order group signal. The signal from input 1 is the first and second bits, and the signal from input 2 is the third and fourth bits.
The signals from the respective inputs are sequentially assigned to the second bit, and so on. By the way, the octet synchronization section 31 includes a plurality of transmission devices (transmission devices 2-1 to 2).
−n), the octet synchronization of the individual signals is performed here, and the data at the same bit position are output here by the digital addition processing unit 32 at the next stage. Digital addition processing is performed. (4-e) The signals 2-1 to 2-n subjected to digital addition processing in the digital addition processing unit 32 are received as one serial data by the octet synchronization unit 41 of the receiving device 4, After the octet synchronization, the separation unit 42 separates the zeroth order signal into a plurality of bearer speed signals. (4
-F) The bearer speed signal separated as described above is sent to the serial input / output unit 43, where the start bit and the stop bit are removed. At 46, a start bit and a stop bit are added again as asynchronous serial data, and transmitted to the terminal device 5 via the external interface 47.

The central processing unit 24 and the central processing unit 4
4 is used to transfer data between the serial input / output units 22 and 25 and between the serial input / output units 42 and 45, respectively, but this is merely an example and other general logic circuits and the like are also used. It is also possible to realize the same function with

[0023]

According to the present invention, as described above, when asynchronous data is multiplexed into the zero-order group signal, the subframe synchronization signal is not used, and the start bit and the stop bit are added as the synchronous serial data. Since the octet synchronization circuit is provided in the digital addition processing device, it is not necessary to provide a subframe synchronization circuit and a subframe insertion circuit as in the conventional system.

That is, in general, the subframe synchronization circuit has a more complicated circuit configuration than the octet synchronization circuit. Also, if the digital addition processing unit is incorporated in the transmission device, the multiplexing unit and the digital addition unit are generally in a state of octet multiplexing, so that the octet synchronization circuit can be omitted.

Further, since a general serial control unit can be used as the serial input / output unit in the present invention, the cost and size of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an outline of a configuration of a transmitting apparatus and a receiving apparatus adopting a method of multiplexing a sub-rate asynchronous signal according to the present invention.

FIG. 2 is a time chart for explaining an input / output processing state of the transmitting apparatus.

FIG. 3 is a block diagram for explaining an outline of a conventional transmitting apparatus and receiving apparatus for multiplexing sub-rate asynchronous signals.

FIG. 4 is a time chart for explaining the input / output processing status of the conventional device.

FIG. FIG. 3 is an explanatory diagram illustrating an example of a 110 frame format.

[Explanation of symbols]

 1-1 to 1-n terminal device 2-1 to 2-n transmitting device 3 digital addition processing device 4 receiving device 5 terminal device 21 external interface 22 serial input / output unit 23 bus 24 central processing unit 25 serial input / output unit 26 multiplex Conversion unit 31 octet synchronization unit 32 digital addition processing unit 41 octet synchronization unit 42 separation unit 43 serial input / output unit 44 bus 45 central processing unit 46 serial input / output unit 47 external interface

Claims (10)

(57) [Claims] An asynchronous sub-rate signal transmitted from a terminal device via an external interface is transmitted to a first serial port.
After receiving the data at the input / output unit and removing the start bit, stop bit, and parity bit,
Only the data was taken into the central processing unit via the bus, sent directly to the second serial input / output unit via the bus, and a start bit and a stop bit were added again to the character data received by the first serial input / output unit . Then, the second serial input / output unit takes out the signal as a synchronous signal having a slightly higher bearer speed than the sub-rate signal received by the second serial input / output unit. Multiplexing a signal of sub-rate as a zero-order group signal of 64 kbit / s. 2. An asynchronous sub-rate signal transmitted from a terminal device via an external interface is transmitted to a first serial port.
After receiving the data at the input / output unit and removing the start bit, stop bit, and parity bit,
Only the data was taken into the central processing unit via the bus, sent directly to the second serial input / output unit via the bus, and a start bit and a stop bit were added again to the character data received by the first serial input / output unit . Then, the second serial input / output unit takes out the signal as a synchronous signal having a slightly higher bearer speed than the sub-rate signal received by the second serial input / output unit. A multiplexed signal transmission method characterized by transmitting a multiplexed signal as a 64 kbit / s zero-order group signal. 3. The multiplexed signal processed by the method for multiplexing sub-rate asynchronous signals according to claim 1 is received as octet synchronizing section of the receiving device as one serial data, and the octet synchronization is restored. After that, the separation unit separates the 0th order signal into a plurality of bearer speed signals, and sends the separated bearer speed signals to the third serial input / output unit .
After removing the start bit and the stop bit, the start bit and the stop bit are added again as asynchronous serial data at the fourth serial input / output unit via the central processing unit, and the terminal is connected via the external interface. A method for receiving a multiplexed signal, characterized in that the apparatus receives the multiplexed signal. 4. An external interface connected to a terminal device and a first serial interface for transmitting and receiving an asynchronous sub-rate signal.
Transmit and receive bearer speed data to and from the input / output unit
A second serial input-output unit, the asynchronous sub-rate signals received at a first serial input-output unit the second serial input
A central processing unit to be transmitted to the output unit, the first serial
A transmission device comprising: a bus connecting an input / output unit , a central processing unit, and a second serial input / output unit ; and a multiplexing unit that multiplexes bearer speed data into a zero-order group signal. 5. An octet synchronizing section for performing octet synchronization of individual zero-order group signals from a plurality of transmitting apparatuses according to claim 4 , and data at the same bit position synchronized by said octet synchronizing section. digitally at the time of transmission of the multiplexed signal in a digital adding unit for adding processing
A transmission device, comprising a transmission processing device. 6. An octet synchronization section for octet synchronization of the 0th order group signal, a separation section for separating octet synchronized data into bearer speed data, and a third serial for transmitting and receiving bearer speed data. A fourth serial input / output for transmitting / receiving an asynchronous sub-rate signal to / from the input / output unit
And parts, and the central processing unit for sending data of said third bearer rate received by the serial input-output unit to the fourth serial input-output unit, a central processing unit and a third serial input-output unit the
4. A receiving device comprising: a bus connecting the serial input / output unit of No. 4 and an external interface connected to a terminal device. 7. The transmitting apparatus according to claim 4, wherein
Data between the serial input / output unit and the second serial input / output unit
The central processing unit that performs the transfer consists of a predetermined logic circuit
A transmitting device, characterized in that: 8. The receiving apparatus according to claim 6, wherein
Data between the serial input / output unit and the fourth serial input / output unit
The central processing unit that performs the transfer consists of a predetermined logic circuit
A receiving device, comprising: 9. The transmitting apparatus according to claim 4 , wherein
A transmission device characterized in that a signal output from a serial input / output unit is supplied with a clock and synchronized. 10. A multiplexing unit according to claim 4 or 5 , wherein a plurality of bearer speed signals sent from the second serial input / output unit are multiplexed as 64 kbit / s zero-order group signals. And transmitting it to the octet synchronization section of the digital addition processing device.