JP2965321B2 - SOH termination circuit for SDH - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a synchronous network (SDH: Synchronous Digital Hierar).
chy), an SDH SOH termination circuit for terminating a section overhead (SOH: Section Over Head) of a transmitted synchronous multiplexed signal (STM-n signal (data having the STM-n format)).

The asynchronous transfer mode (ATM: Asynchronous Transfer
rMode) is a synchronous network that synchronizes the network, performs transmission and exchange after performing synchronous multiplexing, and functions of the SOH termination circuit include, for example, parity check of STM-n signal, Coordination, termination of alarms, and other frame signal processing.

The STM-n signal has a frame format in which the STM-1 signal is multiplexed by n (n is an arbitrary integer, but 1, 4, and 16 are currently used). By n-multiplexing, the arrangement of the SOH in the frame is the same, but the definition of the byte in the SOH is different.

[Conventional technology]

FIG. 7 is a block diagram showing a conventional configuration of the SOH termination circuit.

Here, the configuration of an SOH termination circuit that handles STM-4 signals (hereinafter, referred to as “STM-4 termination circuit”) is shown.

In the figure, an STM-4 termination circuit 60 includes a reception signal input port 61 to which an STM-4 signal is input, an output port 63 to which an SOH-terminated signal is output, and an input to which an SOH-terminated signal is input. It has a port 64, an in-device frame pulse input terminal 65 to which an in-device frame pulse used for inserting SOH data is input, and a transmission signal output port 66 to which an STM-4 signal is output.

An output port 63 is connected to the reception signal input port 61 via a frame synchronization circuit 71, a descrambler 72, an SOH data separation circuit 73, and a pointer change circuit 74. The frame pulse a output from the frame synchronization circuit 71 is connected to the SOH data separation circuit 73 and the pointer change circuit 74.

Input port 64 and internal frame pulse input terminal 65
Is connected to a transmission signal output port 66 via a scrambler 76.

An SOH processor 80 is connected to the SOH data separation circuit 73 and the SOH data insertion circuit 75.

First, the operation of receiving the STM-4 signal will be described based on the above configuration.

The data (STM-4 signal) input to the reception signal input port 61 is input to the frame synchronization circuit 71. The frame synchronization circuit 71 detects the frame synchronization pattern and outputs a frame pulse a indicating the head position of the frame.

The data that has passed through the frame synchronization circuit 71 is input to the descrambler 72, where the data is descrambled. The data output from the descrambler 72 is input to the SOH data separation circuit 73, where the position of the SOH is detected and separated according to the frame pulse a. The separated SOH data is passed to the SOH processor 80 for processing.

The data from which the SOH data is separated by the SOH data separation circuit 73 is input to the pointer change circuit 74. The pointer changing circuit 74 changes the frame phase of the input data to the frame phase in the apparatus according to the frame pulse a.
Change the pointer value of the input data. The data whose pointer value has been changed is output from the output port 63.

 Next, the transmission operation of the STM-4 signal will be described.

The data input to the input port 64 is input to the SOH data insertion circuit 75. In the SOH data insertion circuit 75, the position of the SOH data is determined based on the in-device frame pulse input from the in-device frame pulse input terminal 65, and the SOH data is inserted into the input data to obtain the STM-4 frame format. .

STM-4 frame format data (STM-4
-4 signal) is output from the transmission signal output port 66 via the scrambler 75.

With such a configuration and operation, the SOH of the STM-4 signal is
Termination processing can be performed.

[Problems to be solved by the invention]

By the way, the STM-4 signal is obtained by multiplexing the STM-1 signal by four, but since the frame format is different, for example, the STM-4 termination circuit could not perform termination processing on the SOH of the STM-1 signal. That is, in the configuration of the conventional SOH termination circuit, it is necessary to use a dedicated one corresponding to each synchronous multiplex signal.

The present invention relates to the use of STM-4 signals and STM-1 in SDH.
For SDH that can realize SOH termination processing of signals with the same circuit configuration
An object of the present invention is to provide an SOH termination circuit.

[Means for solving the problem]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 1 (1) shows a basic configuration (reception unit configuration) of the SOH termination circuit for SDH according to claim 1.

That is, data having the STM-n format (n is an integer of 1 or more) is taken in from the reception signal input port,
In the SOH termination circuit for SDH that performs a predetermined SOH termination process,
A frame synchronization circuit that establishes frame synchronization of data and outputs a corresponding frame pulse; an n expansion circuit that expands frame-synchronized data into n; input data of the n expansion circuit when n is 1; When the value is not 1, a selector for selecting one of the n-expanded data by the n-expansion circuit, and the data output from the selector and other data not connected to the selector in the n-expanded data are fetched, respectively, and N n SOH data separation circuits for extracting SOH data, and n multiplexing of each data from which the SOH data is separated, and sending to the output port n
And a multiplexing circuit.

FIG. 1 (2) shows the basic configuration (reception unit configuration) of the SDH SOH termination circuit according to the second aspect.

That is, data having the STM-n format (n is an integer of 1 or more) is taken in from the reception signal input port,
In the SOH termination circuit for SDH that performs a predetermined SOH termination process,
An n-expansion circuit that expands data into n, a first frame synchronization circuit that establishes frame synchronization of data and outputs a corresponding first frame pulse, and a frame synchronization of data that is n-expanded by the n-expansion circuit And a second frame synchronization circuit for outputting a corresponding second frame pulse;
When n is 1, the first selector selects one of the output data of the second frame synchronization circuit when n is not 1, and when n is 1, the first selector selects the first frame pulse. Is not 1, a second selector for selecting the second frame pulse, and one SOH for taking in the output of the first selector and extracting the SOH data according to the frame pulse output from the second selector
The data separation circuit and the output of the second frame synchronization circuit capture the other n-1 outputs not connected to the first selector, respectively,
N-1 SOH data separation circuits for separating SOH data;
Each SOH data separation circuit multiplexes each of the SOH data separated by n and multiplexes the data to an output port.

FIG. 1 (3) shows a basic configuration (transmission unit configuration) of the SOH termination circuit for SDH according to the third aspect.

That is, n-expansion, in which the n-multiplexed data in the in-device format from the input port and the in-device frame pulse from the in-device frame pulse input terminal are taken in, and the data is expanded to n in the SDH SOH termination circuit for performing a predetermined SOH termination process. A circuit and n pieces of SOH data insertion circuits that respectively take in data that has been expanded by the n expansion circuit and insert SOH data according to the frame pulse in the device.
An n-multiplexing circuit for n-multiplexing each data into which the SOH data has been inserted, an output data of a predetermined SOH data inserting circuit when n is 1, and data n-multiplexed by the n-multiplexing circuit when n is not 1, And a selector for transmitting the transmission signal to the transmission signal output port.

(Operation)

In the configuration of the receiving section of the SOH termination circuit for SDH according to claim 1, for the STM-n signal (here, n is 2 or more), frame synchronization is performed by a frame synchronization circuit, and further, each byte is processed by an n expansion circuit. Then, the SOH data separation circuit separates the SOH data into n data, and multiplexes the SOH data and outputs the multiplexed data, whereby the SOH termination processing can be performed.

For the STM-1 signal, the SOH termination processing can be performed by synchronizing the frame with the frame synchronization circuit, separating the SOH data by one SOH data separation circuit, and outputting the SOH data through the n multiplexing circuit. .

That is, the n expansion circuit, the STM-n signal and the STM-1
By using a selector for switching the input of the SOH data separation circuit according to the signal, the STM-n signal and the STM-1
Signal termination can be realized by the same circuit.

Note that the frame synchronization circuit uses the STM-n signal and the STM-
This is a configuration corresponding to both signals.

In the configuration of the receiving unit of the SOH termination circuit for SDH according to the second aspect, the STM-n signal (here, n is 2 or more) is subjected to n-expansion for each byte by an n-expansion circuit and then to a corresponding frame synchronization. The circuit synchronizes the frames, further separates the SOH data by n SOH data separation circuits, and multiplexes and outputs the SOH data, whereby the SOH termination processing can be performed.

For STM-1 signals, frame synchronization is performed by a corresponding frame synchronization circuit, SOH data is separated by one SOH data separation circuit, and the SOH data is output through an n-multiplexing circuit to perform SOH termination processing. Can be.

That is, it comprises an n-expansion circuit and a frame synchronization circuit corresponding to the STM-n signal, and a frame synchronization circuit corresponding to the STM-1 signal, and inputs the SOH data separation circuit according to the STM-n signal and the STM-1 signal. By using the first and second selectors for switching the frame pulse, the termination of the STM-n signal and the STM-1 signal can be realized by the same circuit.

In the transmission unit configuration of the SOH termination circuit for SDH according to claim 3, the STM-n signal (here, n is 2 or more) is expanded into n units for each byte by an n expansion circuit, and then the SOH data is transmitted. The insertion circuit inserts SOH data according to the frame pulse in the apparatus, and multiplexes and outputs the SOH data, so that SOH termination processing can be performed.

In addition, the STM-1 signal is input to one SOH data insertion circuit via an n expansion circuit, SOH data is inserted according to a frame pulse in the apparatus, and the SOH termination processing is performed by directly outputting the SOH data. Can be.

That is, by using an n expansion circuit, an n multiplexing circuit, and a selector for switching data in which SOH data is inserted in accordance with the STM-n signal and the STM-1 signal, the termination of the STM-n signal and the STM-1 signal can be performed in the same circuit. Can be realized.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing a configuration of an embodiment corresponding to claims 1 and 3.

In this embodiment, the STM-4 signal × 1 and the STM-1 signal × 1
4 shows an SOH termination circuit for realizing the termination of No. 4.

In the figure, the SOH terminating circuit 10 includes an STM-4 signal and an ST
STM-4.1 receive signal input port 11 also used for input of M-1 signal # 1, STM to which STM-1 signals # 2 to # 4 are input
-1 received signal input port 12 _{2-12 4,} input port an output port 13 that device signal is output, the transmission in the signal input
14. In-device frame pulse input terminal 65 to which in-device frame pulse is input, STM-4 signal and STM-1 signal # 1
STM-4.1 transmission signal output port 1 shared with the output of
6, STM-1 transmission signal STM-1 signal ♯2~♯4 is output the output port 17 ₂ ~17 _{4, STM-4} signal with the STM-1 signal ♯1
Has an external select terminal 19 to which a selection signal for selecting the input / output of the input terminal is input.

 First, the configuration on the receiving circuit side will be described.

The STM-4 · 1 received signal input port 11 is connected STM-4 · 1 frame sync circuit 21, the STM-1 received signal input port 12 _{2-12 4,} respectively STM-1 frame synchronization circuit 2
2 _{2-22 4} is connected. STM-4-1 frame synchronization circuit 21
The output is input via the STM-4 · 1 descrambler 23 to 4 one terminal of expansion circuit 24 and the selector 25 _1. Each output of the STM-1 frame synchronization circuit 22 _{2 to} 22 ₄
-4 selectors via descramblers 26 _{2 to} 26 ₄ respectively
Is input to one terminal of 25 ₂ to 25 _4. 4 expansion circuit 24 of 4
Deployment output is input to the other terminal of each selector 25 ₁ to 25 _4. Each output of the selector 25 ₁ to 25 ₄ each SOH data separation circuit 27 ₁ to 27 ₄ are inputted to the 4 multiplexing circuit 29 through the pointer changing circuit 28 ₁ to 28 _4, its output is sent from the output port 13 You.

Frame pulse a STM-4 · 1 frame sync circuit 21 outputs is input to the SOH data separating circuit 27 ₁ and the pointer changing circuit 28 ₁ is input to one terminal of the selector 30 _{2-30 4.} STM-1 frame synchronization circuit 22 ₂ ~
22 ₄ frame pulse b to be output, c, d is inputted to the other terminal of the selector 30 _{2-30 4} respectively. selector
30 frame pulse e (a / b) _{of 2} to 30 ₄ outputs, f (a /
c), g (a / d ) is input to the SOH data separation circuit 27 _{2-27 4} and pointer changing circuit 28 ₂ to 28 _4.

 Next, the configuration on the transmission circuit side will be described.

The input port 14 is connected to 4 expansion circuit 31, Part 4 expand output is input to the SOH data insertion circuit 321 _to 323 _4.
The internal frame pulse input to the internal frame pulse input terminal 65 is input to the SOH data insertion circuit 321 _to 323 _4. The output of the SOH data insertion circuit 32 ₁ is
And one terminal of the selector 34. Each output of SOH data insertion circuit 32 _{2-32 4} 4 multiplexing circuit 33 and ST
It is input to the M-1 scrambler 35 _{2-35 4.} 4 multiplex circuit 3
The output of 3 is input to the other terminal of the selector 34, and the output is input to the STM-4.1 scrambler 36.

The output of the STM-4 · 1 scrambler 36 is sent from the STM-4 · 1 transmission signal output port 16, the output of the STM-1 scrambler 35 _{2-35 4} each STM-1 transmission signal output port 17 It sent from _{2-17 4.}

The selection signal input from the external select terminal 19 is input to the selection control terminals of the selectors 25 _{1 to} 25 ₄ , 30 ₂ to 30 ₄ and 34.

SOH data separation circuit 27 ₁ to 27 ₄ and SOH data insertion circuit
321 _to 323 in _4, SOH processor 80 is connected.

Hereinafter, the receiving operation as the STM-4 termination circuit, the STM-
Transmission operation as a 4-terminal circuit, STM-1 terminal circuit (STM
-1 signal reception operation (SOH termination circuit), STM
A transmission operation as a -1 termination circuit will be described.

When operating as an STM-4 termination circuit,
The selection signal input to the external select terminal 19 is set to STM-4 input selection. That is, in the selectors 25 _{1 to} 25 ₄ , 4
To select the output of the expansion circuit 24, the selector 30 _{2-30 4} to select the frame pulse a (e, f, g = a), to select the output of the selector 34 4 multiplexing circuit 33.

When operating as an STM-1 termination circuit,
Select the selection signal for STM-1 input selection. That is, the selector 25 ₁ to 25 _4, to select the output of the STM-4 · 1 descrambler 23 and STM-1 descrambler 26 _{2-26 4,} the selector 30 _{2-30 4,} STM-1 frame synchronizing circuit 22 ₂
Each frame pulse b output from ~22 _4, c, to select the d (e = b, f = c, g = d), SOH selector 34
To select the output side of the data insertion circuit 32 _1.

Reception operation as STM-4 termination circuit STM-4 signal is STM-4 signal and STM-1 signalTM1
-4.1 received signal input port 11 also used as input
To the STM-4-1 frame synchronization circuit 21. STM
The -4-1 frame synchronization circuit 21 detects a frame synchronization pattern and outputs a frame pulse a indicating the head position of the frame.

The data that has passed through the STM-4-1 frame synchronization circuit 21 is input to the STM-4-1 descrambler 23, where the data is descrambled. STM-4.1 descrambler 2
The data output from 3 is input to the 4-expansion circuit 24 and is expanded into 4.

As shown in FIG. 3, the frame format of the input data of the 4-expansion circuit 24 has a structure of 1080 bytes × 9 rows, and the first 36 bytes of each row are SOH data.
This STM-4 frame format is the STM-4 frame format shown in FIG.
This is a configuration in which signals of -1 frame format (270 bytes × 9 rows, SOH data is the first 9 bytes of each row) are multiplexed by 4 for each byte. Therefore, the data expanded into 4 units for each byte by the 4 expansion circuit 24 becomes data in the STM-1 frame format.

The data expanded by byte in the 4 expansion circuit 24 is
SOH data separation circuits 27 _{1 to} 27 ₄ via 25 _{1 to} 25 ₄ respectively
Is input to Here, the SOH data separating circuit 27 _1, the selector 30 _{2-30 4} each through a SOH data separation circuit 27 _{2-27 4,} the frame pulse a output from the STM-4 · 1 frame sync circuit 21 The position of the SOH is detected and separated according to the frame pulse a. SOH data separated by each SOH data separating circuit 27 ₁ to 27 ₄ is processed is passed to SOH processor 80.

Data SOH data at each SOH data separating circuit 27 ₁ to 27 ₄ are separated are inputted to the pointer change circuit 28 ₁ to 28 _4. Each pointer change circuits 28 ₁ to 28 _4, in accordance with the frame pulse a, as in changing carrying frame phase of the input data to the device frame phase, to change the pointer value of the input data. The data whose pointer value has been changed is multiplexed four times for each byte by the four multiplexing circuit 29 and output from the output port 13 in the AU-4 × 4 format.

Transmission operation as STM-4 termination circuit AU-4 × input from input port 14 to 4 expansion circuit 31
The data of 4 is expanded to 4 for each byte. 4 development circuit
Each output of 31 are input to the SOH data insertion circuit 321 _to 323 _4. Each SOH data insertion circuit 321 _to 323 _4, to determine the position of SOH data based on the internal frame pulse input from the internal frame pulse input terminal 65, STM-1 by inserting SOH data to the input data And output the frame format.

The data in the STM-1 frame format is
The data is multiplexed by 4 in a byte multiplexing circuit 33 for each byte, converted into an STM-4 frame format,
It is input to the M-4-1 scrambler 36. Data scrambled by the STM-4.1 scrambler 36 (STM-
4) are output from the STM-4.1 transmission signal output port 16, which is also used for the output of the STM-4 signal and the STM-1 signal # 1.

Reception operation as STM-1 termination circuit The STM-1 signal is input to the STM-4.1 reception signal input port 11,
Alternatively it is inputted from any of STM-1 received signal input port 12 ₂ ~12 _{4, STM-4} signal and here STM-
The operation when inputting from the STM-4.1 reception signal input port 11, which is also used for inputting one signal # 1, will be described.

The STM-1 signal is input from the STM-4.1 received signal input port 11 to the STM-4-1 frame synchronization circuit 21. STM−
The 4.1 frame synchronization circuit 21 detects a frame synchronization pattern and outputs a frame pulse a indicating the head position of the frame.
Is output.

The data that has passed through the STM-4-1 frame synchronization circuit 21 is input to the STM-4-1 descrambler 23, where the data is descrambled. STM-4.1 descrambler 2
Data outputted from the 3 is input to the SOH data separating circuit 27 ₁ via the selector 25 _1. SOH data separation circuit 27 ₁
In the above, the position of the SOH is detected and separated according to the supplied frame pulse a. SOH data separated by SOH data separating circuit 27 ₁ is processed is passed to SOH processor 80.

Data SOH data is separated by the SOH data separating circuit 27 ₁ is input to the pointer change circuit 28 _1. The pointer modification circuit 28 _1, in accordance with the frame pulse a, as in changing carrying frame phase of the input data to the device frame phase, to change the pointer value of the input data. The data whose pointer value has been changed is converted into an AU-4 × 4 format by the 4-multiplexing circuit 29 and output from the output port 13.

Also, STM-1 received signal input port 12 ₂ to 12 ₄ STM-1 signal is input from ♯2~♯4 each STM-1 frame synchronizing circuit 22 ₂ through 22 _4, STM-1 descrambler 26 ₂ - 26
₄ through the input to the selector 25 _{2-25 4.} Selector 25 ₂
25 _4, each selected selects the output of the descrambler 26 _{2-26 4,} the frame pulse b selector 30 _{2-30 4,} each STM-1 frame sync circuit 22 _{2-22 4} outputs, c, and d and, frame pulse e, f, since it is set to output as g, it is possible to operate the SOH data separation circuit 27 _{2-27 4} and pointer changing circuit 28 ₂ to 28 ₄ independent of frame phase, similar The termination can be realized.

Transmission operation as STM-1 termination circuit AU-4 × input from input port 14 to 4-expansion circuit 31
The data of 4 is expanded to 4 for each byte. 4 development circuit
Each output of 31 are input to the SOH data insertion circuit 321 _to 323 _4. Each SOH data insertion circuit 321 _to 323 _4, to determine the position of SOH data based on the internal frame pulse input from the internal frame pulse input terminal 65, STM-1 by inserting SOH data to the input data And output the frame format.

Data which is the frame format of the STM-1 output from the SOH data insertion circuit 32 ₁ is input to the STM-4 · 1 scrambler 36. The SOH data insertion circuit 32 ₂
Similar the data output from to 32 _4, respectively STM-
It is input to the 1 scrambler 35 _{2-35 4.} STM-4 · 1 each data (STM-1 signal) scrambled by scrambler 36 and STM-1 scrambler 35 _{2-35 4} each STM-4 · 1 transmission signal output port 16 and STM-1
It is independently output from the transmission signal output port 17 _{2-17 4.}

FIG. 5 is a block diagram showing a configuration of an embodiment corresponding to claim 2.

In this embodiment, the STM-4 signal × 1 and the STM-1
An SOH termination circuit for realizing the termination of the signal × 4 will be described. The feature of the SOH termination circuit 10 'of the present embodiment is that the STM-4 which operates at a high speed in the embodiments corresponding to the first and third aspects. The one-frame synchronization circuit 21, the STM-4.1 descrambler 23 and the STM-4-1 scrambler 36 are not used.

That is, the STM-4-1 frame synchronization circuit 21 and the STM
Instead -4-1 descrambler 23, STM-1 frame sync circuit 22 _{2-22 4} equivalent STM-1 frame synchronization circuit 2
2 _1, and STM-1 descrambler 26 _{2-26 4} equivalent STM
-1 placing descrambler 26 _1. In addition, STM-4.1
Instead of scrambler 36, STM-1 scrambler 35 _{2 to} 35
₄ to place the equivalent STM-1 scramblers 35 ₁ and.

Furthermore, the difference in the configuration on the receiving circuit side is that the STM
The 4-expansion circuit 41 is connected to the -4.1 reception signal input port 11, and the 4-expansion output is input to the STM-4 frame synchronization circuit 42. The output of the STM-4 frame synchronization circuit 42 is STM-4
Through the descrambler 43 is inputted to one terminal of the selector 25 ₁ to 25 _4. The other terminal of the selector 25 ₁ to 25 _4, the output of the STM-1 descrambler 26 _{1-26 4} is input.

The frame pulse h the STM-4 frame synchronizing circuit 42 outputs is inputted to one terminal of the selector 30 ₁ to 30 _4. The other terminal of the selector 30 ₁ to 30 _4, the frame pulse i to STM-1 frame sync circuit 22 ₁ to 22 ₄ outputs,
b, c, and d are input. The selector 30 ₁ to 30 ₄ frame pulse j to output (h / i), e ' (h / b), f' (h /
c), g '(h / d) is input to the SOH data separating circuit 27 ₁ to 27 ₄ and the pointer changing circuit 28 ₁ to 28 _4.

On the other hand, the difference between the configurations on the transmission circuit side is that each SOH
The output of the data insertion circuit 321 _to 323 ₄ are connected to the STM-1 scrambler 35 _{1-35 4,} further branches to STM-
4 Input to the scrambler 45. STM-4 scrambler 45
Is input to the 4-multiplexing circuit 46. The output of the four multiplexing circuit 46 is input to one terminal of the selector 47. STM−
1 output of the scrambler ₃₅₁ is input to the other terminal of the selector 47.

The output of the selector 47 is sent from the STM-4 · 1 transmission signal output port 16, STM-1 each output of the scrambler 35 _{2-35 4} each STM-1 transmission signal output port 17 _{2-17 4}
Sent from.

The selection signal input from the external select terminal 19 is input to the selection control terminals of the selectors 25 _{1 to} 25 ₄ , 30 ₁ to 30 ₄ , and 47.

Hereinafter, the receiving operation as the STM-4 termination circuit, the STM-
Transmission operation as a 4-terminal circuit, STM-1 terminal circuit (STM
-1 signal reception operation (SOH termination circuit), STM
A transmission operation as a -1 termination circuit will be described.

When operating as an STM-4 termination circuit,
The selection signal input to the external select terminal 19 is set to STM-4 input selection. That is, in the selectors 25 _{1 to} 25 ₄ , ST
Select the output side of M-4 descrambler 43
0 ₁ - 30 to select the frame pulse h which is output from the _4, STM-4 frame synchronizing circuit 42 (j, e, f, g = h),
The selector 47 selects the output side of the 4-multiplex circuit 46.

When operating as an STM-1 termination circuit,
Select the selection signal for STM-1 input selection. That is, each frame to select the selector 25 ₁ to 25 ₄ at the output side of the STM-1 descrambler 26 _{1-26 4,} output from the selector 30 ₁ to 30 ₄ STM-1 frame sync circuit 22 _{2-22 4,} Pulses i, b, c, d are selected (j = i, e = b, f = c,
g = d), it causes the selector 47 to select the output side of the STM-1 scrambler 35 _1.

Reception operation as STM-4 termination circuit STM-4 signal is STM-4 signal and STM-1 signalTM1
-4.1 received signal input port 11 also used as input
From the STM-4 frame synchronization circuit 4 via the 4 expansion circuit 41
Entered in 2. The STM-4 frame synchronization circuit 42 detects a frame synchronization pattern and outputs a frame pulse h indicating the head position of the frame.

The data that passed through the STM-4 frame synchronization circuit 42
-4 is input to the descrambler 43 to perform descrambling processing. Data output from the STM-4 descrambler 43 via the selector 25 _to 253 ₄ are respectively input to the SOH data separating circuit 27 ₁ to 27 _4.

On the other hand, the frame pulse h via the selector 30 ₁ to 30 _4, since the input to the SOH data separating circuit 27 ₁ to 27 ₄ and the pointer changing circuit 28 ₁ to 28 _4, is to terminate similarly performed, The data is multiplexed four times for each byte by the four multiplexing circuit 29, and the AU-4
The data is output from the output port 13 in a format of × 4.

Transmission operation as STM-4 termination circuit AU-4 × 4 data input from input port 14 is
Similarly, the 4 expansion circuit 31 and each SOH data insertion circuit 32 _{1 to} 32
₄ through, SOH data is output by converting the inserted frame format of STM-1.

The data in the STM-1 frame format is S
The data is scrambled by a TM-4 scrambler 45, further multiplexed by 4 in a 4-multiplexing circuit 46 for each byte, converted into an STM-4 frame format, and
STM- shared with 4 signals and STM-1 signal # 1 output
It is output to the 4.1 transmission signal output port 16.

Reception operation STM-1 signal as STM-1 termination circuit, STM-1 received signal input port 12 ₁ to 12 ₄
However, the operation when the signal is input from the STM-4.1 reception signal input port 11, which is also used for the input of the STM-4 signal and the STM-1 signal # 1, will be described here.

STM-1 signal is input from the STM-4 · 1 received signal input port 11 to the STM-1 frame sync circuit 22 _1. STM-1
In the frame synchronizing circuit 22 _1, and it outputs the frame pulse i which indicates the head position of the frame by detecting the frame synchronization pattern.

Data which has passed through the STM-1 frame sync circuit 22 _1, ST
Descrambling process is performed is input to the M-1 descrambler 26 _1. STM-1 data output from the descrambler 26 _1, SOH data separation circuit 27 via the selector 25 ₁
Entered into ₁ . Similarly, termination processing is performed according to the frame pulse i, and the signal is converted into the AU-4 × 4 format by the 4-multiplexing circuit 29 and output from the output port 13.

The same applies to the STM-1 signals # ₂ to # ₄ input from the STM-1 reception signal input ports 122 to 124.

Transmission operation as STM-1 termination circuit AU-4 × 4 data input from input port 14 is
4 through the expansion circuit 31 and the SOH data insertion circuit 321 _to 323 _4, similarly SOH data is output in the inserted frame format of STM-1.

Each data output from the SOH data insertion circuit 321 _to 323 ₄ are respectively input to the STM-1 scrambler 35 _{1-35 4.} Data outputted from the STM-1 scrambler 35 ₁ via the selector 47, also STM-1 scrambler 35 _2-35
4 output data from the STM-4-1 transmission signal output port 16 and the STM-1 transmission signal output port 17 ₂ .
It is independently output from the 17 _4.

As described above, as shown in FIGS. 2 and 5, one SOH
The termination circuit can realize the termination of the STM-4 signal and the termination of the STM-1 signal × 4.

Here, an example of use of the SOH termination circuits 10, 10 'of the present invention is shown in FIGS.

The configuration shown in FIG. 6A is an SOH termination circuit 10 (10 ').
Are arranged independently and used as an STM-1 signal × 4 termination circuit.

The configuration shown in FIG. 6 (2) corresponds to the SOH termination circuit 10 (10 ').
Are arranged facing each other and used as an STM-1 to STM-4 synchronous multiplexing device.

The configuration shown in FIG.
Between (10 '), a cross connect 51 having a line setting function for switching as a digital multiplex line is arranged, and the STM-
This is an example used as a one-to-one STM-4 cross-connect device.

As described above, the STM-n frame format of the SDH is a format in which the STM-1 frame format is multiplexed by n for each byte. Therefore, the above-described embodiment corresponds to the case where n = 4. However, the number of input / output ports is n, the 4-expansion circuit and the 4-multiplex circuit are n-expansion circuit and n-multiplex circuit, respectively, and the frame synchronization circuit is used. , Descrambler, scrambler, SOH data separation circuit, pointer change circuit and SOH data insertion circuit by the corresponding number, the STM-n signal and STM-1
The termination of the signal xn can be realized with the same circuit configuration.

〔The invention's effect〕

As described above, the present invention provides for STM-n signals and STM-
Since SOH termination processing of one signal can be realized with the same circuit configuration, a synchronous multiplexing device and other devices can be flexibly and easily configured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention. FIG. 2 is a block diagram showing a configuration of an embodiment corresponding to claims 1 and 3. FIG. 3 is a diagram showing an STM-4 frame format. FIG. 4 is a diagram showing an STM-1 frame format. FIG. 5 is a block diagram showing a configuration of an embodiment corresponding to claim 2. FIG. 6 is a diagram showing an example of use of the present invention. FIG. 7 is a block diagram showing a conventional configuration of an SOH termination circuit. 10 SOH termination circuit, 11 STM-4-1 received signal input port, 12 STM-1 received signal input port, 13 output port, 14 input port, 16 STM-4 1 transmission signal output port, 17 ... STM-1 transmission signal output port, 21
... STM-4-1 frame synchronization circuit, 22 ... STM-1 frame synchronization circuit, 23 ... STM-4-1 descrambler, 24
... 4 expansion circuits, 25 ... selectors, 26 ... STM-1 descrambler, 27 ... SOH data separation circuit, 28 ... pointer change circuit, 29 ... 4 multiplex circuits, 30 ... selector, 31 ...
... 4 expansion circuit, 32 ... SOH data insertion circuit, 33 ... 4 multiplexing circuit, 34 ... selector, 35 ... STM-1 scrambler, 36 ... STM-4.1 scrambler, 41 ... 4 expansion Circuit, 42: STM-4 frame synchronization circuit, 43: STM-4 descrambler, 45: STM-4 scrambler, 46: 4
Multiplex circuit, 47 ... Selector, 51 ... Cross connect, 61
…… Reception signal input port, 63 …… Output port, 64 …… Input port, 65 …… Frame pulse input terminal in the device, 66…
... Transmission signal output port, 71 ... Frame synchronization circuit, 72 ...
… Descrambler, 73 …… SOH data separation circuit, 74 ……
Pointer change circuit, 75 …… SOH data insertion circuit, 76 ……
Scrambler, 80 ... SOH processor.

Claims (3)

(57) [Claims] 1. A method for receiving data having an STM-n format (n is an integer of 1 or more) from a reception signal input port,
An SDH SOH termination circuit for performing a predetermined SOH termination process, wherein a frame synchronization circuit for establishing frame synchronization of the data and outputting a corresponding frame pulse, and an n development circuit for developing the frame-synchronized data into n When n is 1, the input data of the n expansion circuit, and n is 1
If not, a selector for selecting one of the n-expanded data by the n-expansion circuit; and data output from the selector and other data not connected to the selector in the n-expanded data, respectively, An n number of SOH data separation circuits for extracting SOH data in accordance with a pulse, and an n multiplexing circuit for n-multiplexing each of the data from which the SOH data has been separated and transmitting the data to an output port. SOH termination circuit for SDH. 2. A data having an STM-n format (n is an integer of 1 or more) is taken in from a reception signal input port,
In the SOH termination circuit for SDH which performs a predetermined SOH termination process, an n development circuit for developing the data into n, a first frame synchronization circuit for establishing frame synchronization of the data and outputting a corresponding first frame pulse And a second frame synchronization circuit that establishes frame synchronization of the n-expanded data in the n-expansion circuit and outputs a corresponding second frame pulse. Output data, a first selector for selecting one of the output data of the second frame synchronization circuit when n is not 1; a first frame pulse when n is 1; A second selector for selecting a frame pulse, and taking in the output of the first selector, and SOH data in accordance with the frame pulse output from the second selector. One SOH data separation circuit to be extracted, and the other n-1 outputs not connected to the first selector at the output of the second frame synchronization circuit, respectively, are taken in accordance with the second frame pulse. N-1 SOH data separation circuits for separating SOH data, respectively; and n multiplexing circuits for multiplexing each data from which the SOH data is separated by each of the SOH data separation circuits and sending the multiplexed data to an output port. SOH termination circuit for SDH. 3. An SOH SOH termination circuit for SDH that takes in data multiplexed in an in-device format from an input port and an in-device frame pulse from an in-device frame pulse input terminal and performs predetermined SOH termination processing. An n-expansion circuit to be developed, n-numbered SOH data insertion circuits that respectively take in data that has been n-expanded by the n-expansion circuit and insert SOH data according to the in-device frame pulse, respectively, N to multiplex each data
A multiplexing circuit, and a selector for selecting output data of a predetermined SOH data insertion circuit when n is 1, and selecting data n-multiplexed by the n-multiplexing circuit when n is not 1, and sending the data to a transmission signal output port. An SOH termination circuit for SDH, characterized in that: