JPS6360636A - Synchronizing multiplex system - Google Patents

Abstract

PURPOSE:To separate an output basic signal without phase shift between multiplexed channels by identifying a specific channel number after multiplexing/ demultiplexing, comparing its number with a corresponding multiplex channel number and controlling them so as to be made coincident. CONSTITUTION:A serial/parallel conversion means 11 applies serial/parallel conversion to an input multiplex signal, outputs a parallel signal having a multiplex channel CH number having a different timing sequentially and inputs the result to a multiplex/demultiplex latch means 13. A timing signal generating means 12 generates a timing signal having any phase of the timing signal different in multiplexed CH number and repeated at a period of the input multiplexed signal. The means 13 uses the timing signal from the means 12 to latch the output of the means 11 thereby outputting a basic signal of the multiplexed CH number. A control signal identification means 14 identifies the CH number of the basic signal output of the specific CH of the means 13, detects the different between the number with the corresponding multiplexed CH number to control the phase of the timing signal of the means 12 thereby taking the correspondence between the CH number at multiplexing with the CH number after multiplexing/demultiplexing.

Description

[Detailed description of the invention] [Summary] A basic signal is created by inserting a control signal necessary for multiplexing into a frame structure of a basic signal rate, and this basic signal is multiplexed to produce a high-order multiplexed signal. In the receiving section of the synchronous multiplexing method to be formed, the multiplexing channel number of the demultiplexed specific channel is identified, and the demultiplexing method is By shifting the phase of the timing signal, channel synchronization is achieved between the basic signal during multiplexing on the transmitting side and the basic signal after demultiplexing on the receiving side.

[Industrial application field]

The present invention relates to a PCM signal multiplexing system, and particularly to a synchronous multiplexing system in which basic signals are multiplexed in an integral multiple.

In order to transmit and exchange wideband signals such as video signals,
In the conventional multiplexing system based on PCM hierarchy, the time slot of each signal in the group signal is not fixed.
It was extremely difficult to directly extract and output the desired signal from the group signal. Additionally, as services become wider in bandwidth, construction of synchronous networks using higher-order groups is being considered to reduce the effects of jitter and the like. In this situation, broadband l5DN
A synchronous multiplexing method is being considered in which several tens of Mbps is selected as the basic signal speed of the PCM hierarchy, and an integer multiple thereof is allowed as the multiplexed PCM hierarchy.

In this synchronous multiplexing method, the multiplexing hierarchy is an integer multiple of the basic signal rate, so auxiliary signals (frame synchronization signals, control signals, etc.) are not inserted in each multiplexing unit, and the control signals necessary during multiplexing are etc. are prepared in advance on the basic signal frame, and multiplexing is performed using this control signal area. This greatly simplifies the configuration of the multiplexing section, which requires high speed (just a P/S
(conversion, S/P conversion only), frame synchronization processing, and control processing of the channel switching unit that supports multiplexed channels can be performed at the basic signal speed, so a configuration suitable for high speed should be adopted. is possible. Note that channel switching here is based on the function of the high-speed multiplexing unit being simple P/S conversion.
Since only S/P conversion is required, the channel number during multiplexing and the channel number after demultiplexing do not necessarily match, so it is necessary to take channel correspondence by switching channels, so this is provided because this is the case.

However, such a configuration is not a problem when the service is provided below the basic signal rate, i.e. when it is used as a pipe, but for broadband services where it is necessary to combine and use multiple basic signal frames. Therefore, there is a possibility that a phase difference may occur on the basic signal frame after demultiplexing, and a synchronous multiplexing method that does not cause such a phase difference is desired.

[Conventional technology]

In the conventional synchronous multiplexing method, the multiplexing control signal written on the basic signal frame after demultiplexing is identified, and the channel switching section placed immediately after the demultiplexing latch circuit is selected based on the identification result. I was trying to control it and take action on the channel.

FIG. 4 shows the frame structure of the basic signal.

As shown in the figure, the frame structure consists of a control signal and an information signal (D), and the control signal is a frame synchronization signal (D).
F), a multiplex control signal (ID), a maintenance monitoring signal, etc.

FIG. 5 shows an example of the configuration of a conventional synchronous multiplexing device. On the transmitting side, the multiplexing section includes an identification signal interpolation section 11 for each channel. 12. −.

in, the respective channels CHI, CH2, .
- For each basic signal FB of CHn, a specific multiplexing channel number is written in the multiplexing control signal ID. P/
The S converter 2 performs parallel-to-serial conversion on the basic signal of each channel in which the multiplexed channel number is written to create a multiplexed signal nFB.

The control unit (CONT) 3 controls the operation timing of each unit at this time. The multiplexed signal nFB at the output of the P/S converter 2 is sent to the receiving side via the transmission path 4.

On the receiving side, the demultiplexer converts the input multiplexed signal into S
/P converter 5 performs serial/parallel conversion and sequentially separates the signals into signals SRI, SR2, -, SRn having specific timings, and latches them in latch unit 6 according to the timing signal of counter 7 to convert the speed. , basic signal CHI'', C
H2', -.

produces CHn'. At this point, the multiplexed channel number of the basic signal of each channel does not necessarily correspond to that on the transmitting side.

Frame synchronization, multiplex channel number identification section (FSYNC)
, ID DET) 8 establishes frame synchronization for the basic signal of a specific channel, for example CHn', and identifies its multiplexed channel number. Then, the switch unit 9 is controlled to sequentially change the order of the basic signals of each channel so that the identified multiplexing channel number matches the original multiplexing channel number of that channel. As a result, output signals having channel numbers CHI, CH2, -CHn that correspond to the channel numbers at the time of multiplexing on the transmitting side are obtained.

[Problem that the invention seeks to solve]

The configuration of the synchronous multiplexer shown in FIG. 6 is intended to use the basic signal as a pipe, so when combining multiple basic signal frames, the phase relationship of each channel is Since the phase relationship does not necessarily match the phase relationship before multiplexing, it is necessary to perform phase adjustment between multiple channels.

That is, for example, by combining and using three basic signals with a basic signal speed of 50 Mbps, the basic signal speed is 150 Mbps.
When transmitting signals, the following cases may occur depending on the network configuration.

1. The three combined basic signals are each transmitted through separate routes, and a frame phase difference occurs between the three basic signals due to the bus delay time difference.

2. Even if three basic signals are sent through the same multiplexed transmission path, a frame phase difference may occur between the combined basic signals depending on the demultiplexing method.

Problem 1 above can be solved by controlling the networks so that they pass through the same transmission path. However, regarding problem 2, problems arise with conventional demultiplexing methods.

FIG. 6 shows a time chart of demultiplexing in a conventional synchronous multiplexer. In FIG. 6, the multiplexed input data is the output SRI, S
In R2, . . . , SRn, outputs are sequentially delayed by one bit. The latch unit 6 latches and converts the speed according to the fixed timing signal PH1 of the counter 7, and separates it into basic signals CHI' and CH2°+-2CHn'.

Since the channel number arrangement of this basic signal output does not correspond to that on the transmitting side, the multiplexed channel number is identified and channel replacement is performed in the switch section 9 to reestablish the channel number correspondence. As shown in Figure 2, there is a possibility that a 1-bit phase difference will occur in each channel output.

Therefore, it is necessary to insert a function that can insert/remove a 1-bit delay into the output of the switch section and perform phase control between each coupled channel. Otherwise, for example, if the transmission signal is an image signal, the MSB and LSB in one byte of the output signal may be swapped due to a one-bit difference, but in such a case, the reproduced image will be completely meaningless. There was a problem that it became.

[Means for solving problems]

The present invention is an attempt to solve the problems of the prior art, and as shown in the basic structure of FIG. , a demultiplexing device using a synchronous multiplexing method that multiplexes a synchronized basic signal at a signal speed that is an integer multiple of the speed thereof, comprising a serial-to-parallel conversion means 11, a timing signal generation means 12, a demultiplexing/demultiplexing latch means 13, , and control signal identification means 14.

The serial/parallel converter 11 converts the input multiplexed signal into serial/parallel converters to generate parallel signal outputs of the number of multiplexed channels having sequentially different timings.

The timing signal generating means 12 generates a timing signal having one of the phases at sequentially different timings of the number of multiplexed channels and repeating at the period of the input multiplexed signal.

The demultiplexing/latch means 13 is connected to the timing signal generating means 1.
By latching the output of the serial/parallel converting means 11 using the timing signal No. 2, basic signal outputs corresponding to the number of multiplexed channels are generated.

The control signal identifying means 14 identifies the multiplexed channel number of the basic signal output of the specific channel of the demultiplexer/latch means 13 and distinguishes between the identified multiplexed channel number and the number of the multiplexed channel corresponding to this specific channel. Detect the difference.

By controlling the phase of the timing signal in the timing signal generating means 12 according to the detected difference between the multiplexed channel numbers, the channel numbers during multiplexing and the channel numbers after demultiplexing are made to correspond.

[For production]

The demultiplexing method of the present invention monitors the basic signal of a specific channel after demultiplexing, and after establishing frame synchronization of the basic signal, identifies the multiplexed channel number of the specific channel,
The sending side Control is performed so that the multiplexed channel number during multiplexing at the time of multiplexing corresponds to the multiplexed channel number after demultiplexing at the receiving side.

〔Example〕

FIG. 2 shows an embodiment of the present invention, illustrating the configuration of a demultiplexing section. In the figure, 21 is a shift register;
2 is a demultiplexing counter circuit, 23 is a demultiplexing latch section, and 24 is a frame synchronization section.

25 is a multiplexed channel number identification section, and 26 is a shift pulse generation section.

Further, FIG. 3 shows an operation flowchart of demultiplexing in the embodiment of FIG. 2.

The multiplexed input data is read into the shift register 21 in accordance with the clock, and outputs SRI, SR2, -, SRn sequentially shifted by one bit are generated in parallel. The demultiplexing counter circuit 22 counts the clocks and generates a timing signal that has one of phases out of sequential timings equal to the number of multiplexed channels and repeats at the period of the input multiplexed signal. .

The demultiplexing latch unit 23 includes a demultiplexing counter circuit 22
By latching and speed converting the output of the shift register 21 using the timing signal of , the basic signal output CHI of the number of multiplexed channels is obtained.

Generates CH2, ---, CHn.

The frame synchronization unit 24 monitors the basic signal output of a specific channel, for example, channel CHn, in the output of the demultiplexer/latch unit 23, and performs frame synchronization processing to synchronize frames using the frame synchronization signal F shown in FIG. (step S2 in FIG. 3), check whether frame synchronization is achieved (step S3 in FIG. 3), and repeat the process until frame synchronization is achieved.

When frame synchronization is achieved, the multiplex channel number identification unit 25 identifies the multiplex channel number of the specific channel CHn (step S4 in FIG. 3), and determines whether the identified multiplex channel number is n. See (Step S5 in Figure 3)
. When the identified multiplexing channel number is n,
Since channel synchronization has been established (step 36 in FIG. 3), the processing in the circuit of FIG. 2 ends.

On the other hand, when the identified multiplexing channel number is not n, the shift pulse generator 26 generates a shift pulse to shift the phase of the timing signal in the demultiplexing counter circuit 22 by 1 bit (step 3 in FIG. 37)
. Next, frame synchronization section 24. Multiplexed channel identification unit 25
etc., repeat the frame synchronization process and the multiplex channel number identification process, and check again whether the identified multiplex channel number is n (step S5 in Figure 3). If not, the phase of the timing signal is further shifted by 1 bit (step S7 in FIG. 3).
The same process is repeated until the identified multiplexed channel number reaches n to establish channel synchronization.

Alternatively, when the multiplexed channel number identified by the multiplexed channel identification section 25 is not n, the shift pulse generation section 26 calculates the difference between the identified multiplexed channel number and n, and the difference is equal to the difference. By shifting the phase of the timing signal in the demultiplexing counter circuit 22 by the number of bits (step 87'' in FIG. 3),
Channel synchronization may also be established.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to always correctly demultiplex the output basic signal without a phase shift from the basic signal of each channel multiplexed on the transmitting side. Even for broadband services that are used in combination, demultiplexing can be performed stably, and the device configuration in this case is simple and can be downsized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle hook configuration of the present invention, FIG. 2 is a diagram showing the configuration of a synchronization separation section in an embodiment of the invention, and FIG. 3 is an operation flowchart of demultiplexing in the embodiment of FIG. 2. 4 is a diagram showing the frame structure of the basic signal, FIG. 5 is a diagram showing an example of the configuration of a conventional synchronous multiplexer, and FIG. 6 is a time chart of synchronous separation in a conventional synchronous multiplexer. FIG. 21-Shift register 22-Demultiplexing counter circuit 23-Demultiplexing latch section 24--Frame synchronization section 25--Mux channel number identification section 26--Shift pulse generation section

Claims (1)

[Claims] Demultiplexing using a synchronous multiplexing method that has a control signal including a multiplexing channel number on a basic signal frame and multiplexes the synchronized basic signal at a signal speed that is an integral multiple of the basic signal speed. In the apparatus, a serial-to-parallel conversion means (
11), a timing signal generating means (12) for generating a timing signal having one of the phases at sequentially different timings of the number of multiplexed channels and repeating with the period of the input multiplexed signal; and the timing signal generating means (12). ) for latching the output of the serial/parallel converting means (11) to generate basic signal outputs for the number of multiplexed channels; and a specific channel of the multiplexing/demultiplexing latch means (13). control signal identifying means (14) for identifying a multiplex channel number of a basic signal output of the base signal and detecting a difference between the identified multiplex channel number and a multiplex channel number corresponding to the specific channel; . A synchronous multiplexing system, characterized in that the phase of the timing signal in the timing signal generating means (12) is controlled according to the detected difference between the multiplexed channel numbers.