JPH05175953A - Synchronization detector - Google Patents

Abstract

PURPOSE:To correct simultaneously a channel lead and a bit lead by detecting a lead quantity of a bit phase and a lead quantity of a channel phase based on a bit shift signal and a frame pattern detection signal to establish the synchronization. CONSTITUTION:When frame pattern detection circuits 31-34 output bit shift signals 1a-4a representing a bit lead upon the detection of a frame pattern having a shift bit and output simultaneously frame pattern detection signals 1b-4b representing bit shift. The bit shift signals 1a-4a are collected by a bit shift control circuit 8 and a pulse equivalent to a deviation of channel synchronization is outputted to a byte serial parallel conversion circuit 2 as a channel shift instruction 4j. Furthermore, the pulse is outputted to a bit serial parallel conversion circuit 1 as a bit shift instruction 9a in the state of out of synchronism from an AND circuit 9. The circuits 1, 2 receiving the instructions 9a, 4j implement synchronization locking to establish the synchronization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detecting device for a demultiplexer used in a synchronous multiplex transmission system, and more particularly to a device capable of immediately performing synchronization correction of frame synchronization and channel synchronization.

[0002]

2. Description of the Related Art In recent years, CCITT (International Tel
egraph and Telephone Consultative Committee: SDH (Synchronous Dictionary)
STM (Synchronous Tran) based on gitalHierarchy
sport Module: Synchronous multiplex transmission system) was recommended as a world standard. In the conventional synchronous multiplex converter corresponding to this, (1) a method of performing synchronization detection and channel detection in a high-speed processing unit (serial signal processing unit), (2) decomposing the signal into the number of channels, and then synchronizing for each channel Demultiplexing of the serial multiplex signal is performed depending on which of the detection method and the channel detection method is used.

As shown in FIG. 5, the demultiplexing section of the STM-N synchronous multiplex converter adopting the above method (1) detects the frame synchronization of the serial multiplex signal 5 and holds the synchronization. Frame sync detection / protection circuit 60,
An N channel separation circuit 61 that separates the serial multiplexed signal 5 into regular N channels and a control circuit 62 that controls these circuits 60, 61 are provided.

In the demultiplexer of this synchronous multiplex converter,
The STM-N frame synchronization detection / protection circuit 60 detects the frame pattern of the input serial STM-N signal 5 to detect the synchronization of the signal 5, and sends an initialization signal 65 based on this to the control circuit 62. Be done. The initialized control circuit 62 sends a control signal 63 to the STM-N frame synchronization detection / protection circuit 60 at a frame cycle to maintain synchronization, and also sends a control signal 64 to the N channel separation circuit 61 for serial multiplexing. The timing of separation of the signal 5 into each channel is controlled.

Through these operations, the serial multiplexed signal 5 is separated into regular N channels, but each circuit forming the demultiplexer is required to process this operation at a high speed of 600 MHz or higher.

In the control circuit 62, the control signal of the frame cycle is
Since the frame counter is required to send 63, the circuit scale increases, and the STM-N frame synchronization detection / protection circuit 60 also has a circuit scale to detect a complete frame pattern. There is no choice but to grow. However, in a high-speed processing circuit, as the circuit scale increases, the amount of heat generation increases sharply, resulting in a decrease in reliability, difficulty in integration, and an increase in the size of the device and an increase in power consumption.

In order to reduce the circuit scale, a method has been devised in which the STM-N frame synchronization detection / protection circuit 60 detects only a part of the pattern of the frame pattern to obtain the synchronization. When the same false frame pattern as some patterns occurs within a frame period, there is a possibility that it may cause false synchronization.

A method devised to avoid high-speed processing is the above-mentioned method (2), and the STM-N adopting the method is adopted.
As shown in FIG. 6, the demultiplexing unit of the synchronous multiplex converter is
A serial-to-parallel conversion circuit 1 for converting a serial STM-4 multiplex signal 5 into an 8-bit parallel STM-4 multiplex signal 6, and an 8-bit parallel STM-
Byte-serial parallel conversion circuit 2 for converting into one signal 7a, 7b, 7c, 7d, and first to fourth low-speed synchronization units provided for each channel
71, 72, 73, 74 are provided.

This low-speed synchronizing section includes a frame synchronization detection / protection circuit 81 for detecting a frame synchronization deviation,
Pattern detection and initialization signal 86 and bit shift command 88
And a frame pattern detection circuit 82 for detecting the deviation of the channel synchronization through the detection of the STM identifier, and a channel shift command 89.
And a control circuit 85 for controlling each circuit.

In the demultiplexing section of this synchronous multiplex converter,
The frame synchronization detection / protection circuit 81 checks the synchronization of the signals 7a to 7d sent separately for each channel, and when a synchronization shift is detected, a frame synchronization loss signal 87 is output. With this output, the frame pattern detection circuit 82 detects the frame pattern and sends the initialization signal to the control circuit 85.
86 is transmitted, and a bit shift command 88 is output to the bit serial parallel conversion circuit 1. Upon receipt of this command 88, the bit serial-parallel conversion circuit 1 pulls in the synchronization and removes the bit shift.

Frame synchronization is established by such a series of operations. However, the channel synchronization is not pulled even if the frame synchronization is established. Therefore, in order to execute the channel synchronization establishment, after the frame synchronization is established, in the channel synchronization detection / protection circuit 83, ST
The channel is detected by the M identifier, and the channel phase shift calculation circuit 84 outputs the channel shift command 89 to the byte-serial / parallel conversion circuit 2. The byte serial-parallel conversion circuit 2 which has received this command 89 pulls in channel synchronization to remove the channel shift. When the frame synchronization and the channel synchronization are established, the control circuit 85 causes the frame synchronization detection / protection circuit 81 and the channel synchronization detection / protection circuit 83.
The control signals 91 and 90 are sent to, and the synchronization is maintained.

As described above, in this system, channel detection by the STM identifier can be performed only after frame synchronization is established by synchronization detection. Therefore, the worst channel recovery time is τ + 1 frame,
There is a drawback that it is longer than τ in the method (1) (τ: worst frame synchronization time).

Further, in this method, channel detection becomes impossible unless the STM identifier is inserted.

As a method of forming the demultiplexing unit with a low-speed circuit, Japanese Patent Application Nos. 3-180084 and 3-18.
Although the methods of No. 0085 have been proposed, these methods have a drawback that the circuit scale increases because it is necessary to provide a frame synchronization circuit for each channel.

[0015]

SUMMARY OF THE INVENTION The present invention is intended to solve the problems of such a conventional device, and in a system for demultiplexing using a low speed circuit, a frame is used without using an STM identifier. It is an object of the present invention to provide a synchronization detection device that can simultaneously establish synchronization and channel synchronization.

[0016]

In view of the above, the present invention detects the frame synchronization and the channel synchronization of a signal that has passed through the bit serial / parallel conversion circuit and the byte serial / parallel conversion circuit to detect the bit serial / parallel conversion circuit and the byte serial / parallel circuit. In a synchronization detection device that controls the operation of a conversion circuit, a frame pattern of bit shift of each channel is detected, and a bit shift signal indicating the amount of the bit shift and a frame pattern detection signal indicating the timing of the detection are detected. A frame pattern detection circuit that outputs, a bit shift control circuit that outputs a control signal for frame synchronization correction to a bit serial parallel conversion circuit based on the bit shift signal, and a byte serial parallel based on the frame pattern detection signal A synchronization control circuit that outputs a control signal for channel synchronization correction to the conversion circuit is provided. That.

[0017]

In this synchronous control circuit, the bit shift control circuit determines the amount of bit shift from the bit shift signals output from each frame pattern detection circuit, and
The synchronization control circuit determines the amount of channel deviation from the frame pattern detection signal. Then, based on this determination, control signals for frame synchronization correction and channel synchronization correction are simultaneously output from each control circuit to the bit serial-parallel conversion circuit and the byte serial-parallel conversion circuit.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a sync detecting apparatus according to an embodiment of the present invention is a bit serial-parallel conversion circuit 1 for converting a serial STM-4 multiplex signal 5 into an 8-bit parallel STM-4 multiplex signal 6. And a byte-serial parallel conversion circuit 2 for converting the multiplexed signal 6 into 8-bit parallel STM-1 signals 7a, 7b, 7c, 7d, and STM-1 signal 7a of each channel.
Bit shift signal by detecting ~ 7d frame pattern
1a, 2a, 3a, 4a and frame pattern detection signals 1b, 2b, 3
First to fourth frame pattern detection circuits 31, 32, 33, 34 for outputting b and 4b, and each frame pattern detection circuit 31-
The bit shift control circuit 8 that outputs the bit shift instruction 9a to the bit-serial parallel conversion circuit 1 based on the bit shift signals 1a to 4a input from the 34, and the frame input from each of the frame pattern detection circuits 31 to 34・ Pattern detection signal 1b
.About.4b to provide a channel shift instruction 4j to the byte-serial / parallel conversion circuit 2 and a bit shift control circuit 8 and an AND circuit 9 to which the outputs of the synchronization control circuit 4 are input. The frame pattern detection circuits 31 to 34, the bit shift control circuit 8 and the synchronization control circuit 4 form a low speed synchronizing section.

First, the flow of signals in this synchronization detecting device will be described.

The serial STM-4 multiplexed signal 5 is sent to the 8-bit parallel STM in the bit serial-parallel conversion circuit 1.
-4 converted into a multiplex signal 6. Further, the 8-bit parallel STM-4 multiplexed signal 6 is converted into four 8-bit parallel STM-1 signals 7a to 7d by the byte serial parallel conversion circuit 2.
Is divided into four frame pattern detection circuits 31 to 34.
Sent to.

In the frame pattern detection circuits 31 to 34, S
The frame pattern of the TM-1 signal is detected. This frame pattern has the arrangement illustrated in FIG. In the synchronized state (the bit advance amount is 0), the frame pattern contains 8 normal information bits. Therefore, some information bits are missing. When the frame pattern detection circuits 31 to 34 detect a frame pattern having a bit shift, they output the bit shift signals 1a to 4a indicating the bit advance value.

At the same time, the frame pattern detection circuits 31-34
Outputs frame pattern detection signals 1b to 4b indicating the timing at which the frame pattern having the bit shift is detected.

The bit shift signals 1a-4a output by the frame pattern detection circuits 31-34 are collected in the bit shift control circuit 8. In the bit shift control circuit 8,
It is checked whether or not the values of these bit shift signals 1a to 4a match, and when the values are other than 0, a bit advance judgment signal 8b is sent to the synchronous control circuit 4 and at the same time a pulse corresponding to that value is sent. Output to the AND circuit 9.

On the other hand, in the synchronization control circuit 4, each frame
The frame pattern detection signals 1b-4b output from the pattern detection circuits 31-34 are collected. The synchronization control circuit 4 determines a channel synchronization shift based on the frame pattern detection signals 1b to 4b, and outputs a pulse corresponding to the shift amount to the byte-serial parallel conversion circuit 2 as a channel shift command 4j. Output.

The synchronization control circuit 4 detects an out-of-synchronization state (hunting state) based on the frame pattern detection signals 1b to 4b and the bit advance determination signal 8b output from the bit shift control circuit 8. Then, the hunting signal 4k is output to the AND circuit 9. Therefore, the pulse sent from the bit shift control circuit 8 from the logical product circuit 9 in the out-of-synchronization state is the bit shift command.
It is output to the bit serial-parallel conversion circuit 1 as 9a.

The bit serial / parallel conversion circuit 1 and the byte serial / parallel conversion circuit 2 which have received the bit shift instruction 9a and the channel shift instruction 4j perform a synchronous pull-in operation to establish synchronization. The established synchronization is held by the operation of the synchronization control circuit 4.

The amount of channel shift required to establish synchronization is obtained from the frame pattern detection signals 1b to 4b output by the frame pattern detection circuits 31 to 34. The reason for this will be described.

It is now assumed that the STM-4 multiplexed signal 6 is advanced by 1 bit and the channel is advanced by 1 channel as the out-of-sync state.

The first frame pattern detection circuit 31 to which the signal is sent from the byte serial / parallel conversion circuit 1 detects the "advance 1" frame pattern in FIG. 1a is output to the bit shift control circuit 8. At the same time, the first frame pattern detection circuit 31
Outputs a frame pattern detection signal 1b indicating the timing of generation of the bit shift signal 1a to the synchronization control circuit 4.

Similarly, a second frame pattern detection circuit
32, the third frame pattern detection circuit 33, and the fourth frame pattern detection circuit 34 also synchronize the frame pattern detection signals 2b to 4b indicating the timing at which the frame pattern of 1 bit advance is detected, with the synchronization control circuit. Output to 4.

At this time, when channel synchronization is established, the signals sent from the byte-serial / parallel conversion circuit 2 in the order of channel 1, channel 2, channel 3, channel 4 are:
Since the channel is advanced by one, as shown in FIG. 4A, signals 1, 2, 3, ... Are transmitted in the order of channel 4, channel 1, channel 2, channel 3. If the head of the frame is signals 1 to 4, each frame pattern detection signal 1b to
The timing of occurrence of 4b is as shown in (b) of FIG.
Only the frame pattern detection signal 4b output from the fourth frame pattern detection circuit 34 is advanced by one clock.

Similarly, when the channel is advanced by two channels, the third and fourth frame pattern detection circuits 33 and 34 are added to the frame pattern detection signal 1b of the first frame pattern detection circuit 31. The frame pattern detection signals 3b and 4b output by the CPU advance by one clock, and the number of channels is 3
When the channel is advanced, the frame pattern detection signals 2b to 4b output by the second, third and fourth frame pattern detection circuits 32, 33 and 34 are advanced by one clock.

In this way, in the synchronization control circuit 4, depending on the generation timing of the frame pattern detection signals 1b-4b,
The amount of channel shift is determined, and a pulse corresponding to this amount is issued to the byte / serial conversion circuit 2 as a channel shift instruction.

The concrete structure of the synchronization control circuit 4 is shown in FIG.
, And each frame pattern detection signal 1b
4b and an inverted signal of the bit advance determination signal 8b from the bit shift control circuit 8, a logical product circuit 43, a synchronization detection / protection unit 41 including a frame counter and a contention counter, and each frame pattern detection Channel shift determination section 42 for inputting signals 1b to 4b, and AND circuit to which each output of synchronization detection / protection section 41 and channel shift determination section 42 is input
44 and.

When the frame pattern detection signals 1b to 4b indicate the same timing and the values of the bit shift signals 1a to 4a do not match or the bit shift 0 is displayed, the logical product circuit 43 displays. Pulse detection and protection unit 41
Output to.

The synchronization detection / protection unit 41 outputs a hunting signal 4k in the hunting state. The hunting signal 4k is input to the logical product circuit 44, and also output from the synchronization control circuit 4 and input to the logical product circuit 9. In the channel shift determination unit 42, the input frame pattern detection signal
The amount of channel shift is determined from 1b to 4b, and a pulse corresponding to that amount is sent to the AND circuit 44. The AND circuit 44 is
The pulse sent when the hunting signal 4k is present is output as the channel shift instruction 4j.

Channel shift correction is performed by the byte-serial / parallel conversion circuit 2 according to the channel shift instruction 4j, and the bit shift instruction 9a output from the AND circuit 9 is performed.
When the bit shift correction is performed by the bit serial parallel conversion circuit 1 in accordance with the above, the timings of the frame pattern detection signals 1b to 4b output by the frame pattern detection circuits 31 to 34 match and the bit shift is performed. Signals 1a-4a indicate a zero bit shift. Therefore, a pulse is output from the AND circuit 43 and input to the synchronization detection / protection unit 41. The synchronization detection / protection unit 41 switches the output signal from the hunting signal to the synchronization protection signal by this signal.

When the bit advance is 2 to 7 bits and / or the channel advance is 2 or 3 channels, the synchronization pull-in is performed by the same operation.

Although the STM-4 has been described here, it is clear that the channel detection can be performed in the same manner for the STM-N (N> 2).

[0040]

As is apparent from the above description of the embodiments, in the synchronization detecting apparatus of the present invention, the frame pattern detecting circuits 31 to 34 provided for each channel and the detecting circuits 31 to 34 are provided.
Of the bit shift signals 1a to 4a that are output by
A shift control circuit 8 and a synchronization control circuit 4 for collecting the frame pattern detection signals 1b-4b output from the detection circuits 31-34.
And constitute a low-speed synchronization section, and establish the synchronization by detecting the amount of advance of the bit phase and the amount of advance of the channel phase based on the bit shift signal and the frame pattern detection signal. Therefore, in this device, the channel advance can be corrected simultaneously with the bit advance, and the worst channel recovery time can be shortened.

In order to detect the channel phase, the STM
Since it is not necessary to refer to the identifier, the practical effect is large. In addition, since the bit phase lead amount and the channel phase lead amount are determined by different circuits, the configuration of these determination circuits can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization detection device of the present invention,

FIG. 2 is a specific configuration diagram of a synchronization control circuit in the device shown in FIG.

3 is a diagram showing a frame pattern detected by a frame pattern detection circuit of the device shown in FIG.

FIG. 4 is a diagram for explaining the generation timing of a frame pattern detection signal,

FIG. 5 is a block diagram showing an example of a conventional synchronization detection device,

FIG. 6 is a block diagram showing another example of a conventional synchronization detection device.

[Explanation of symbols]

 1-bit serial-parallel conversion circuit 2-byte serial-parallel conversion circuit 31 to 34, 82 Frame pattern detection circuit 4 Synchronization control circuit 5 Serial STM-4 multiplex signal 6 Parallel STM-4 multiplex signal 8-bit shift control circuit 9, 43, 44 Logical product 41 Synchronization detection / protection unit 42 Channel shift determination unit 60, 81 Frame synchronization detection / protection circuit 61 N channel separation circuit 62, 85 Control circuit 63, 64, 90, 91 Control signal 65, 86 Initialization signal 71 to 74 Low-speed synchronization section 83 Channel synchronization detection / protection circuit 84 Channel shift calculation circuit 87 Out-of-frame signal 1a, 2a, 3a, 4a Bit shift signal 1b, 2b, 3b, 4b Frame pattern detection signal 4j, 89 channel shift Instruction 4k Hunting signal 7a to 7d Parallel STM-1 signal 8b Bit advance judgment signal 9a, 88 bit shift instruction

Claims (1)

[Claims] 1. A synchronization detection for detecting the frame synchronization and the channel synchronization of a signal that has passed through the bit serial parallel conversion circuit and the byte serial parallel conversion circuit, and controlling the operations of the bit serial parallel conversion circuit and the byte serial parallel conversion circuit. In the device, a frame pattern detection circuit that detects a frame pattern of bit deviation of each channel and outputs a bit shift signal that indicates the amount of the bit deviation and a frame pattern detection signal that indicates the timing of the detection. A bit shift control circuit that outputs a control signal for frame synchronization correction to the bit serial-parallel conversion circuit based on the bit shift signal; and a channel for the byte serial-parallel conversion circuit based on the frame pattern detection signal. And a synchronization control circuit that outputs a control signal for synchronization correction. Sync detector.