JP2736185B2 - Channel detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel detecting device provided in a decomposing section of a synchronous multiplex converter.

[0002]

2. Description of the Related Art In recent years, CCITT (International Telegraph)
and Teleph-one Consultative Committee (SDH) (Synchronous Digital Hie
(rarchy) based Synchronous Transport Modul
e: Synchronous multiplex transmission method) was recommended as a globally unified standard. In the conventional synchronous multiplex conversion device corresponding to this, (1)
The high-speed processing unit (serial signal processing unit) performs synchronization detection and channel detection, and (2) separates the signal into the number of channels, and then performs synchronization detection and channel detection for each channel. Make up.

FIG. 3 is a block diagram showing one configuration of a conventional STM-N synchronous multiplexing / conversion device decomposing unit, which is based on the method (1). As shown in FIG.
The MN synchronous multiplex conversion device disassembly unit is composed of an STM-N frame synchronization detection / protection circuit 50, an N channel disassembly circuit 51, and a control circuit 52. Here, 53 is a serial STM-N signal, 54 is STM-N frame synchronization detection /
A control signal for the protection circuit 50, 55 is an N-channel decomposition circuit
Reference numeral 56 denotes a control signal for the control circuit 51, and reference numeral 56 denotes an initialization signal for the control circuit 52.

In this synchronous multiplex conversion device disassembling section, the input of a serial STM-N signal 53 is synchronously detected by an STM-N frame synchronous detection / protection circuit 50, and an initialization signal 56 based on this detects a control circuit 52. Is initialized. The control circuit 52 is N
The timing of decomposition of the channel decomposition circuit 51 is controlled by the control signal 55, and the serial STM-
The N signal 53 is decomposed into regular N channels (four channels in FIG. 3) of STM-1 signals 101, 102, 103 and 104.

Here, the control circuit 52 outputs a control signal 54 to the STM-N frame synchronization detection / protection circuit 50 generated in a frame cycle. Therefore, the control circuit 52 requires a frame counter, and the circuit scale becomes large. Further, the STM-N frame synchronization detection / protection circuit 50
In order to detect a complete frame pattern by using the method, the circuit scale becomes large. These circuits are high-speed processing circuits of 600 MHz or more, and the amount of heat generated increases as the circuit scale increases, which causes problems in reliability and integration.

To reduce the circuit scale, STM-N
There is a method of detecting a part of the frame pattern by the frame synchronization detection / protection circuit 50, but this causes erroneous synchronization when a false frame pattern occurs in a frame cycle.

As described above, in the method (1), the circuit scale of the high-speed processing circuit becomes large, so that the power consumption increases.
There is a drawback that the device is enlarged and the reliability is reduced due to heat generation. Further, detecting a part of the frame pattern in order to reduce the circuit scale causes erroneous synchronization.

FIG. 4 is a block diagram showing one configuration of a conventional synchronous multiplexing / conversion device decomposing unit, which is based on the method (2). As shown in FIG. 4, the STM-N synchronous multiplex conversion device decomposition unit includes a bit serial / parallel conversion unit 60, a byte serial / parallel conversion unit 61, a first low speed synchronization unit 62, and a second low speed synchronization unit. 63, a third low-speed synchronizer 64, and a fourth low-speed synchronizer
Each of the low-speed synchronization sections 62, 63, 64, and 65 includes a frame synchronization detection / protection circuit 66, a frame pattern detection circuit 67, a channel synchronization detection / protection circuit 68, and a channel phase shift calculation circuit 69. And a control circuit 70. Here, 71 is a serial STM-4 multiplex signal, 72
Is an 8-bit parallel STM-4 multiplexed signal.

In the synchronous multiplex converter decomposing unit, when the frame synchronization loss signal 77 is output from the frame synchronization detection / protection circuit 66, the frame pattern is detected by the frame pattern detection circuit 67, and the control circuit 70 is initialized. By outputting the signal 78 and the bit shift command 90, the operation of establishing frame synchronization is performed. However, establishing the frame synchronization does not mean that the channel synchronization is pulled. Also, the STM identifier cannot be detected. Therefore, after the frame synchronization is established, the channel is detected by the STM identifier and the operation of establishing the channel synchronization is performed. Here, 101, 102, 103 and 104 are STM-1 signals decomposed into correct channels.

As described above, according to the method (2), the channel cannot be detected by the STM identifier until the synchronization is established by the synchronization detection. Accordingly, the worst channel recovery time is τ + 1 frame (τ: worst frame synchronization time), which is disadvantageous in that it is longer than the worst frame synchronization time τ of the method (1).

Further, when no STM identifier is inserted, channel detection becomes impossible.

[0012]

As described above, the conventional synchronous multiplexer / demultiplexer decomposing unit has a problem that it is difficult to reduce the power consumption and reduce the size of the device without using the STM identifier. is there.

An object of the present invention is to provide a channel detecting device which can be realized by a low-speed processing circuit without increasing the worst-case channel recovery time in a decomposition section of a synchronous multiplexing conversion device. It is assumed that.

[0014]

In order to solve the above-mentioned problems, the present invention provides a frame pattern detecting circuit, a frame synchronization detecting / protecting circuit and a control circuit for controlling the same as a low-speed synchronizing unit. The frame pattern position or frame specific position detected by each low-speed synchronization section detects a specific channel, for example, a channel that is one clock ahead of the frame pattern detection position or frame specific position of the low-speed synchronization section of the first channel. Channel phase detection means for detecting the amount of advance of the channel phase, and based on the output of the channel phase detection circuit.
Byte serial-to-parallel converter for shifting channel phase
It is a thing.

[0015]

According to the above arrangement, the amount of advance of the channel phase can be known by the channel phase detecting means. Therefore, by correcting the amount of advance of the channel phase based on this, it is possible to immediately establish channel synchronization.

[0016]

FIG. 1 is a block diagram showing a synchronous multiplex conversion apparatus decomposing unit according to one embodiment of the present invention, which synchronously detects a multiplex signal called STM-4.

As shown in FIG. 1, the channel detector of the synchronous multiplex converter decomposing unit includes a bit serial-to-parallel converter 1, a byte serial-to-parallel converter 2, a first low-speed synchronizer 3, and a second low-speed synchronizer 3. A channel phase detection circuit 9 is provided in addition to the low-speed synchronizer 4, the third low-speed synchronizer 5, and the fourth low-speed synchronizer 6. Here, 7 is a serial STM-4 multiplex signal,
Reference numeral 8 denotes an 8-bit parallel STM-4 multiplexed signal.

Each of the low-speed synchronization units 3, 4, 5, and 6 has a frame pattern detection circuit 10 for detecting a frame pattern having a bit shift, and a frame synchronization detection / detection unit for detecting a frame synchronization pattern and performing a synchronization / protection operation. A protection circuit 11, a control circuit 12 for controlling the operation of the frame period in the frame period detection / protection circuit, AND circuits 13 and 14, and an OR circuit 15 are provided. The channel phase detection circuit 9 determines whether the frame pattern detection position or the frame specific position detected by each of the low-speed synchronization units 3, 4, 5, and 6 is the frame pattern of the low-speed synchronization unit 3, 4, 5, and 6 of the specific channel. A channel advanced by one clock with respect to the detection position or the frame specific position is detected to detect the amount of advance of the channel phase. The frame synchronization detection / protection circuit 11 can be generally configured by a contention counter.

The operation of the synchronous multiplex converter decomposing unit will be described below. First, the flow of signals in the synchronous multiplexing converter decomposing unit will be described. The serial STM-4 multiplexed signal 7 is converted into an 8-bit parallel STM-4 multiplexed signal 8 by the bit serial / parallel converter 1. Further, the 8-bit parallel STM-4 multiplexed signal 8 is divided into four 8-bit parallel STM-1 signals 20, 35, 36, and 37 by a byte serial / parallel conversion unit 2, and the four low-speed synchronization units 3,
It is sent to 4,5,6. 8-bit parallel STM-1 signals 20, 35, 3 divided into four by byte serial / parallel conversion unit 2
The STM-1 signal 20, which is one of 6,37, is input to the first low-speed synchronization section 3. Similarly, other STM-1 signals 35, 36, and 37 are input to the second low-speed synchronizer 4, the third low-speed synchronizer 5, and the fourth low-speed synchronizer 6.

In the first low-speed synchronization section 3, the STM-1 signal 20
Is input to the frame pattern detection circuit 10 and the frame synchronization detection / protection circuit 11. Frame pattern detection circuit
10 outputs a frame pattern detection signal 21 to the AND circuit 14 and the OR circuit 15 when detecting a frame pattern having a bit shift. At this time, the frame pattern detection circuit 10 outputs the bit advance value to the AND circuit 13 as a bit phase signal 22. The AND circuit 13 detects that the frame synchronization detection / protection circuit 11 has lost frame synchronization (frame synchronization loss). When the signal 25 is at the H level, the bit phase signal 22 is output as the bit shift command 40.

The frame synchronization detection / protection circuit 11 outputs a frame synchronization loss signal 25 at the time of loss of synchronization to an AND circuit.
Output to 14. In addition, the control circuit 12 detects frame synchronization.
A control signal 23 is output to the protection circuit 11. In the control circuit 12, the frame synchronization detection / protection circuit 11 is out of frame synchronization (the out-of-frame signal 25 is at the H level).
In this case, when the pattern is detected by the frame pattern detection circuit 10, the initialization is performed by the initialization signal 24 of the AND circuit 14.

Here, the channel detection operation will be described in detail below. First, consider a state in which the frame synchronization is pulled in (the frame synchronization loss signal 25 is at the L level).

Since the frame synchronization has been established, it is assumed that the control signal 23 of the control circuit 12 is output at a frame cycle and indicates a specific position of the frame, here, the head position. Therefore, the frame position designation signal 41 output from the OR circuit 15 becomes the control signal 23 of the control circuit 12 in a state where the frame synchronization is drawn, and the frame position designation signal 41 indicates the head of the frame.

Now, the channel of the STM-4 multiplex signal 4 is 1
Assuming that the channel is advanced, as shown in FIG. 2, channel 4 (fourth low-speed synchronizer 6), channel 1 (first low-speed synchronizer 3), channel 2 (second low-speed synchronizer 4), Signals 1, 2,... In the order of channel 3 (third low-speed synchronization section 5)
・ Is sent. Assuming that the frame head is signals 1 to 4, the frame position designation signal 41, the frame position designation signal 43, the frame position designation signal 45, and the frame position designation signal 47 are generated at the timing shown in FIG. Therefore, only the frame position designation signal 47 of the fourth low-speed synchronization unit 6 is advanced by one clock with respect to the frame position designation signal 41 of the first low-speed synchronization unit 3.

Similarly, when the channel is advanced by two channels, the frame position designation signal 45 of the third low-speed synchronization unit 5 and the frame position designation signal 45 of the third low-speed synchronization unit 5 are compared with the frame position designation signal 41 of the first low-speed synchronization unit 3. 4 and the frame position designation signal 47 of the low-speed synchronization section 6 is advanced by one clock. When the channel is advanced by three channels, the frame position specifying signal 43 of the second low-speed synchronizer 4 and the frame position specifying signal 43 of the third low-speed synchronizer 5 correspond to the frame position specifying signal 41 of the first low-speed synchronizer 3. The frame position designation signal 45 of the fourth low-speed synchronizing unit 6 is advanced by one clock.

Therefore, in the channel phase detection circuit 9, the frame position designation signal 41 and the frame position designation signal 43 one clock before, the frame position designation signal 41 and the frame position designation signal 45 one clock before, and the frame position designation signal 41
Is compared with the frame position designation signal 47 one clock before, and when the logical product of the frame position designation signal 41 and the frame position designation signal 43 one clock before is 1, three channels, 2 when the logical product of the frame position specifying signal 43 is 0 and the logical product of the frame position specifying signal 41 and the frame position specifying signal 45 one clock before is 1
When only the logical product of the channel and frame position designation signal 41 and the frame position designation signal 47 one clock before is 1, the channel is advanced by one channel. Output to In the byte serial / parallel conversion unit 2, the channel shift instruction
Correct the channel advance based on 48.

Next, consider a state in which the frame synchronization is lost (the frame synchronization loss signal 25 is at the H level). The frame pattern detection circuit 10 detects a 1-bit to 7-bit bit advance frame pattern in the STM-1 signal 20. Table 1 shows the frame patterns detected by the frame pattern detection circuit 10.

[0028]

[Table 1]

When a frame pattern shown in Table 1 is detected, the frame pattern detection circuit 10 outputs a frame pattern detection signal 21 and a bit phase signal 22 indicating a bit advance value. The logical product of the bit phase signal 22 indicating the bit advance value and the out-of-frame signal 25 is obtained, and the logical product circuit 13
Outputs a bit shift instruction 40.

Thus, the bit shift command 40 is output from the first low speed synchronizing section 3. Similarly, bit shift commands 42, 44, and 46 are output from the other second low-speed synchronizer 4, third low-speed synchronizer 5, and fourth low-speed synchronizer 6. In the bit serial / parallel conversion unit 1, these bit shift commands 40, 4
Bit advance is detected based on 2,44,46.

On the other hand, the frame position designation signal 41 output from the OR circuit 15 is a frame pattern detection signal of the frame pattern detection circuit 10 when the frame synchronization is lost.
Since it is 21, the frame position designation signal 41 indicates the frame pattern detection position. Therefore, similarly to the state where the frame synchronization is pulled in, the advance of the channel phase is determined by the channel phase detection circuit 9 for the first low-speed synchronization section 3 to the fourth low-speed synchronization section 6, and the byte serial conversion section 2 Can be corrected. As a result, frame synchronization is established, a correct channel is detected, and STM-1 signals 101, 102, 103 and 104 decomposed into correct channels are output.

Here, the STM-4 multiplexed signal has been described with reference to the drawings, but it is clear that channel detection can be performed in the same manner for an STM-N (N> 2) multiplexed signal. is there.

[0033]

As described above, according to the present invention, the same number of low-speed synchronizing units as the number of channels for receiving low-speed synchronizing units having the frame pattern detecting circuit, the frame synchronizing detecting / protecting circuit, and the control circuit for controlling the same are provided. A frame pattern detection position or a frame specific position detected by the low-speed synchronization section of a specific channel detects a channel advanced by one clock with respect to the frame pattern detection position or the frame specific position of the low-speed synchronization section of a specific channel, and the By providing the channel phase detection circuit for detecting the amount of advance, the STM
The amount of advance of the channel phase can be known without referring to the identifier, and the channel synchronization can be immediately performed based on this.

[Brief description of the drawings]

FIG. 1 is a block diagram of a synchronous multiplexing converter decomposing unit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a channel of an STM-4 multiplexed signal and a frame position designation signal.

FIG. 3 is a block diagram of a conventional synchronous multiplexing conversion device disassembly unit.

FIG. 4 is a block diagram of a conventional synchronous multiplex conversion device disassembly unit.

[Explanation of symbols]

 1-bit serial-to-parallel converter 2 byte serial-to-parallel converter 3 first low-speed synchronizer 4 second low-speed synchronizer 5 third low-speed synchronizer 6 fourth low-speed synchronizer 9 channel phase detection circuit 10 frame pattern detection circuit 11 Frame synchronization detection / protection circuit 12 Control circuit

Claims (1)

(57) [Claims] A low-speed synchronizer having a frame pattern detection circuit, a frame synchronization detection / protection circuit, and a control circuit for controlling the same is provided by the number of channels to be received, and a frame pattern detected by each low-speed synchronizer is provided. A channel phase detection circuit for detecting a channel whose detection position or frame specific position is advanced by one clock with respect to the frame pattern detection position or frame specific position of the low-speed synchronization section of the specific channel and detecting the amount of advance of the channel phase. And a channel based on the output of the channel phase detection circuit.
A channel detection device provided with a byte serial / parallel conversion unit for shifting a channel phase .