JP2803050B2 - Synchronous detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detecting device for a demultiplexing device used in a synchronous multiplex transmission system, and more particularly to a device for establishing channel synchronization simultaneously with establishing frame synchronization.

[0002]

2. Description of the Related Art Recently, CCITT (International Tel)
egraph and Telephone Consultative Committee: SDH (Synchronous Diet)
STM (Synchronous Tran) based on gitalHierarchy
sport Module: synchronous multiplex transmission system) was recommended as a globally unified standard. In the conventional synchronous multiplex conversion apparatus corresponding to this, (1) a method of performing synchronization detection and channel detection in a high-speed processing unit (serial signal processing unit), (2) decomposing a signal into the number of channels, and then synchronizing for each channel The demultiplexing of the serial multiplexed signal is performed by any of the detection and channel detection methods.

As shown in FIG. 4, the demultiplexing section of the STM-N synchronous multiplex conversion apparatus adopting the method (1) detects the frame synchronization of the serial multiplexed signal 7 and maintains the synchronization. A frame synchronization detection / protection circuit 60,
An N-channel separation circuit 61 for separating the serial multiplexed signal 7 into regular N channels, and a control circuit 62 for controlling the circuits 60 and 61 are provided.

In the demultiplexing section of this synchronous multiplex conversion device,
In the STM-N frame synchronization detection / protection circuit 60, the synchronization of the signal 7 is detected through the detection of the frame pattern of the input serial STM-N signal 7, and an initialization signal 65 based on the detection is transmitted to the control circuit 62. Can be The initialized control circuit 62 sends a control signal 63 to the STM-N frame synchronization detection / protection circuit 60 at a frame cycle to maintain synchronization, and sends a control signal 64 to the N channel separation circuit 61 to perform serial multiplexing. The timing of separation of the signal 7 into each channel is controlled.

[0005] Through these operations, the serial multiplexed signal 7 is separated into the normal N channels. Each circuit constituting the demultiplexing unit is required to process this operation at a high speed of 600 MHz or more.

In the control circuit 62, a control signal of a frame cycle
Since a frame counter is required to transmit 63, the circuit scale increases, and the circuit scale also increases in the STM-N frame synchronization detection / protection circuit 60 in order to detect a complete frame pattern. I have to grow. However, in a high-speed processing circuit, when the circuit scale is enlarged, the amount of heat generated increases rapidly, reliability is reduced, and integration becomes difficult, resulting in an adverse effect such as an increase in the size of the device and an increase in power consumption.

In order to reduce the circuit size, a method has been devised in which the STM-N frame synchronization detection / protection circuit 60 detects only a part of the frame pattern to obtain synchronization. When the same false frame pattern as some patterns occurs within a frame period, it may cause erroneous synchronization.

The method devised in order to avoid the high-speed processing is the above-mentioned method (2), and the STM-N adopting the method is adopted.
As shown in FIG. 5, the demultiplexing unit of the synchronous multiplex conversion device includes:
A bit serial / parallel conversion circuit 1 for converting the serial STM-4 multiplexed signal 7 into an 8-bit parallel STM-4 multiplexed signal 8;
A byte serial / parallel conversion circuit 2 for converting the signals into one signal 23, 24, 25, 26, and first to fourth low-speed synchronization sections 3, 4, 5, and 6 provided for each channel are provided.

The low-speed synchronization section includes a frame synchronization detection / protection circuit 33 for detecting a frame synchronization deviation,
Detect pattern and initialize signal 20 and bit shift command 3a
, A channel synchronization detection / protection circuit 34 for detecting a shift in channel synchronization through detection of an STM identifier, and a channel shift command 3b.
And a control circuit 37 for controlling each circuit.

In the demultiplexing section of the synchronous multiplex conversion device,
A frame synchronization detection / protection circuit 33 checks the frame synchronization of the signals 23 to 26 which are separately transmitted for each channel, and outputs a frame synchronization loss signal 15 when a synchronization deviation is detected. When this output is present, the frame pattern detection circuit 30
Detects the frame pattern, sends the initialization signal 20 to the control circuit 37, and outputs the bit shift command 3a to the bit serial / parallel conversion circuit 1. The bit serial / parallel conversion circuit 1 receiving this command 3a performs synchronization pull-in to remove a bit shift.

[0011] Through such a series of operations, frame synchronization is established. However, the establishment of frame synchronization does not necessarily lead to the channel synchronization. Therefore, in order to execute channel synchronization establishment, after frame synchronization is established, the channel synchronization detection / protection circuit 34
Channel detection is performed using the M identifier, and a channel shift command 3b is output from the channel phase shift calculation circuit 35 to the byte serial / parallel conversion circuit 2. In the byte serial / parallel conversion circuit 2 receiving the command 3b, the channel synchronization is performed to eliminate the channel deviation. When the frame synchronization and the channel synchronization are established, the control circuit 37 sends control signals 18 and 19 to the frame synchronization detection and protection circuit 33, the channel synchronization detection and protection circuit 19 and the channel phase shift calculation circuit 35.
17 is sent to maintain synchronization.

[0012]

As described above, the method of (2) for performing synchronization detection and channel detection for each channel after decomposing the serial multiplex signal into the number of channels is as follows.
Although it has the advantage that high-speed processing is not required and the device can be downsized, on the other hand, unless the frame synchronization is established by synchronization detection, the STM
Since the channel cannot be detected by the identifier, the worst channel recovery time is τ + 1 frame (however,
τ: worst frame synchronization time), which is longer than the recovery time τ of the method (1).

The present invention solves this problem.
It is an object of the present invention to provide a synchronization detecting device capable of realizing the establishment of channel synchronization simultaneously with the establishment of frame synchronization in a method of performing demultiplexing using a low-speed circuit.

[0014]

Therefore, according to the present invention, a frame synchronization and a channel synchronization of a signal passing through a bit serial / parallel conversion circuit and a byte serial / parallel conversion circuit are detected, and the bit serial / parallel conversion circuit and the byte serial / parallel conversion circuit are detected. In a synchronization detection device for controlling the operation of a parallel conversion circuit, a first frame for detecting a frame pattern of a bit shift of an N-channel signal when the byte-serial / parallel conversion circuit divides an input signal into N-channel signals. A pattern detection circuit, a second frame pattern detection circuit for detecting a frame pattern of a bit shift of each channel signal, and a channel phase shift based on a detection signal of the first frame pattern detection circuit. N low-speed synchronization units including a channel phase shift calculation circuit that outputs a channel shift instruction to a byte serial / parallel conversion circuit Only to have.

[0015]

Therefore, since an N-channel signal is always input to one of the N low-speed synchronizers of the synchronization detecting device, the first frame pattern detection circuit of the low-speed synchronizer to which the N-channel signal has been input. Detects a bit shift of the N-channel signal and outputs a detection signal to a channel phase shift calculating circuit. The channel phase shift calculation circuit recognizes that the N-channel signal is being output to the low-speed synchronization section, and calculates the difference between the channel number of the signal that should be output and the channel number, thereby calculating the channel phase shift. . In this way, the detection of the bit shift and the detection of the channel phase shift are performed in parallel, and their corrections are performed simultaneously.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the embodiment of the present invention,
A bit serial / parallel conversion circuit 1 for converting a serial STM-4 multiplex signal 7 into an 8-bit parallel STM-4 multiplex signal 8 as shown in FIG. A byte serial / parallel conversion circuit 2 for converting the multiplexed signal 8 into 8-bit parallel STM-1 signals 23, 24, 25, 26, and first to fourth low-speed synchronizers 3 for detecting frame synchronization and channel synchronization. , 4, 5, and 6.

Each of the low-speed synchronizing units 3 to 6 detects a frame pattern having a bit shift and outputs detection signals 11 and 13 and bit phase signals 12 and 14 (signals representing bit advance values). 2 frame pattern detection circuits 31, 32
And a frame synchronization detection / protection circuit 33 that outputs a frame synchronization loss signal 15 when a frame synchronization pattern is detected and the frame synchronization is lost.
The channel synchronization protection operation is performed by detecting the STM identifier of the TM-1 signal and performing a channel synchronization protection operation.
And an STM identifier or first frame pattern detection circuit
A channel phase shift calculating circuit 35 for calculating the advance value of the channel phase based on the detection signal 11 and outputting the channel shift instruction 3b; a channel phase shift calculating circuit 35; a frame synchronization detecting / protecting circuit 33; A control circuit that controls the operation of the frame period in the detection / protection circuit 34
37 and the frame synchronization detection / protection circuit 33 outputs the frame synchronization loss signal 15, the bit synchronization based on the bit phase signals 12 and 14 of the frame pattern detection circuits 31 and 32.
A bit phase shift judging circuit 36 for outputting the shift instruction 3a,
A logical sum circuit 38 for calculating the logical sum of the detection signals 11 and 13 by the first and second frame pattern detection circuits 31 and 32, and the output of the logical sum circuit 38 and the frame synchronization loss signal 15 of the frame synchronization detection / protection circuit 33 And an AND circuit 39 for obtaining the logical product of the two.

Incidentally, the frame synchronization detection / protection circuit 33 and the channel synchronization detection / protection circuit 34 can be generally constituted by a contention counter.

First, the flow of signals in the synchronization detecting device will be described.

The serial STM-4 multiplexed signal 7 is converted into an 8-bit parallel STM
-4 multiplexed signal 8. Further, the 8-bit parallel STM-4 multiplexed signal 8 is converted into four 8-bit parallel STM-1 signals 23, 2 by the byte serial / parallel conversion circuit 2.
Divided into 4, 25, 26
5 and 6 are distributed.

STM-1 signal sent to low-speed synchronization section 3
23 is a first frame pattern detection circuit 31, a second frame pattern detection circuit 32, a frame synchronization detection / protection circuit 33,
It is input to a channel synchronization detection / protection circuit 34 and a channel phase shift calculation circuit 35.

When the frame synchronization of the STM-1 signal 23 is established, the frame synchronization detection / protection circuit 33 that detects the frame synchronization pattern continues the synchronization protection operation.

When the frame synchronization is lost, the frame synchronization detection / protection circuit 33 in which the frame synchronization pattern cannot be detected outputs the frame synchronization loss signal 15 (high level) to the AND circuit 39 and the bit phase shift determination circuit 36. In addition, the first or second frame pattern detection circuits 31 and 32 that have detected a frame pattern with a bit shift are
The detection signals 11 and 13 are sent to the OR circuit 38 and the bit phase signals 12 and
14 are output to the bit phase shift judging circuit 36, respectively.

As a result, both the output of the OR circuit 38 and the frame synchronization loss signal 15 become high level, and the AND circuit 39 outputs the initialization signal 20 to the control circuit 37. The control circuit 37 is given an initial value in the operation control of the frame period by the initialization signal 20. Also,
The bit phase shift judging circuit 36 is a bit serial / parallel conversion circuit 1
And outputs a bit shift instruction 3a to instruct the correction of the bit advance amount detected by the frame pattern detection circuits 31 and 32.

On the other hand, with respect to channel synchronization, a channel synchronization detection / protection circuit 34 detects an STM identifier and performs a channel synchronization protection operation. When a channel phase shift occurs, the channel synchronization detection / protection circuit 34 outputs the channel shift signal 16 to activate the calculation operation of the channel phase shift calculation circuit 35. As will be described later, the channel phase shift calculating circuit 35 is based on the detection signal 11 output from the first frame pattern detection circuit 31 when the channel shift and the frame synchronization shift occur simultaneously in the STM-1 signal 23. Further, when only the channel shift occurs, the advance value of the channel phase is detected by detecting the STM identifier of the STM-1 signal 23, and the channel shift instruction 3b is sent to the byte serial / parallel conversion circuit 2. And outputs a command to correct the channel advance amount.

The channel shift instruction 3b has a bit
The correction of the advance of the channel phase, which is output in parallel with the shift instruction 3a and is performed by the byte-serial / parallel conversion circuit 2, is performed simultaneously with the correction of the bit advance by the bit-serial / parallel conversion circuit 1.

Next, the detection operation of the first and second frame pattern detection circuits 31 and 34 and the operation of channel detection based thereon will be described.

First and second frame pattern detection circuits
31 and 32 detect the frame pattern of the STM-1 signal 23.

In the STM-1 signal, the frame synchronization pattern is set to "F6F6F628282" according to the worldwide standard.
8 ”(hexadecimal notation. In hexadecimal notation, 10,
11, 12, 13, 14, and 15 are A, B,
C, D, E, and F). For example, if a 1-bit shift occurs in this frame synchronization pattern, “1111” “0110” of “F6F6 #”
“1111” “0110”} is “1“ 1110 ”
“1101” “1110” “110 °” and “1E
DE # "is detected by the first and second frame pattern detection circuits 31 and 32.

FIG. 2 shows a frame pattern that is one bit ahead in STM-4. The signal in FIG.
The bit signal shown as channel 1 is the low-speed synchronization unit 1
The bit signal shown as channel 2 is sent to the low-speed synchronization unit 2 by the byte-serial / parallel conversion circuit 2 in the form
It is distributed to the low-speed synchronization units 3 to 6.

The first frame pattern detection circuit 31 and the second frame pattern detection circuit 32 of each of the low-speed synchronization sections 3 to 6
The frame pattern indicating the bit advance of the transmitted STM-1 signal is detected. This frame pattern is shown in FIG.
As shown in (1), detection is made in different patterns according to the bit advance amount. Therefore, from this pattern, it is possible to determine whether the bit advance amount is 2 to 7 bits.

The first frame pattern detection circuit 31 and the second frame pattern detection circuit 32 differ from each other in the length of the frame pattern to be detected. The second frame pattern detection circuit 32 outputs a detection signal 13 and a bit phase signal 14 indicating a bit advance value when detecting a frame pattern described in the B (second) column of FIG.
The pattern detection circuit 31 detects the detection signal 11 and the bit only when detecting the frame pattern in the A (first) column (that is, the frame pattern in which the 8-bit frame pattern is added before and after the frame pattern in the B column). The phase signal 12 is output.

In the case of the STM-4 signal shown in FIG. 2 as an example, the frame pattern in column A of FIG. It is. Therefore, the frame pattern in column A appears only in the STM-1 signal of channel 4, and in the STM-1 signals of channels 1, 2 and 3,
The frame pattern in column B of FIG. 3 appears, but the frame pattern in column A does not appear.

That is, when converting a serial STM-N (N> 2) signal to an 8 × N-bit parallel signal, the ST
MN channel number (STM identifier value: hereinafter "#"
When the signal of # 1 is input with a bit advance of 1 to 7 bits, the signals of # 1 to # N-1 are
The frame pattern in column B of FIG. 3 appears, but the frame pattern in column A does not appear, and the frame pattern in column A of FIG. 3 appears for the signal #N (of course, the frame pattern in column B appears).
Patterns have also appeared).

Therefore, when the STM-N signal has a bit advance and a channel phase advance, the first frame pattern detection circuit of the low-speed synchronizing section (assumed to be 3) to which the #N signal of the STM-N is input. 31 outputs the detection signal 11, but the first frame pattern detection circuits 31 of the other low-speed synchronizing sections 4, 5, and 6 do not output the detection signal 11.

The detection signal 11 output from the first frame pattern detection circuit 31 is input to a channel phase shift calculation circuit 35 of the low-speed synchronization section 3, and the channel phase shift calculation circuit 35
The low-speed synchronizer 3 recognizes that #N has been received. Therefore, the channel phase shift calculation circuit 35 calculates the advance value of the channel phase by comparing with the channel number (the value of the STM identifier) set in the low-speed synchronization section 3. In general, for STM-N, the advance value of the channel phase is obtained by the following equation.

Channel phase advance value = N- (set channel number) When this is applied to the STM-4 signal of FIG. 2, when the signal of channel 4 is input to the fourth low-speed synchronization section 6, Is the first frame of the fourth low-speed synchronization section 6
The pattern detection circuit 31 detects the frame pattern in the column A corresponding to 1 of “advance” in FIG. 3 and outputs the detection signal 11 to the channel phase shift calculation circuit 35. The channel phase shift calculation circuit 35 that has received the detection signal 11 calculates the advance value of the channel phase as 4-4 = 0. That is, in this case, although the bit advance occurs, the channel phase shift does not occur.

When the signal of the channel 4 is input to the third low-speed synchronizing section 5, the first frame pattern detecting circuit 31 of the third low-speed synchronizing section 5 detects the frame pattern in column A of FIG. Will do. At this time, the advance value of the channel phase is calculated as 4-3 =
The channel phase shift calculation circuit 35 outputs a channel shift command 5b to the byte serial / parallel conversion circuit 2 to instruct the byte serial / parallel conversion circuit 2 to pull back the channel phase by one.

As described above, when a bit advance occurs in the STM-N signal, the first of the low-speed synchronizing units 3 to 5
The frame pattern detection circuit 31 detects the frame
The pattern is detected and the detection signal 11 is output. Based on the detected signal, the channel phase shift calculation circuit 35 calculates the advance value of the channel phase, and outputs the channel shift commands 3b to 6b to the byte serial / parallel conversion circuit 2. The channel synchronization is immediately performed.

On the other hand, when the bit synchronization is achieved but the channel synchronization is lost, the channel synchronization detection / protection circuit 34 that has detected the loss of channel synchronization is sent to the channel phase shift calculation circuit 35 by the channel out-of-channel signal. Outputs 16. However, since the bit is not shifted, the control circuit 37 does not output from the AND circuit 39 and continues to send the normal control signal 17 to the channel phase shift calculating circuit 35.

In such a state, the channel phase shift calculating circuit 35 outputs the S
The STM identifier is detected from the TM-1 signal 23, the advance value of the channel phase is calculated by comparing the STM identifier with the channel number set in the low-speed synchronization section 3, and the channel shift instruction 3b is output to the byte serial / parallel conversion circuit 2. Then, the channel synchronization is pulled in.

[0042]

As is clear from the above description of the embodiment, since the synchronization detecting device of the present invention is constituted by using the low-speed synchronizing section, the power consumption is small and the device can be miniaturized. It is. In addition, since this device can correct the shift of the channel phase simultaneously with the correction of the bit advance, the synchronization recovery time is short and the practical value is extremely large.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization detection device according to the present invention;

FIG. 2 is a diagram showing a frame pattern advanced by one bit in an STM-4 signal;

FIG. 3 is a diagram showing a frame pattern detected by a frame pattern detection circuit according to the embodiment;

FIG. 4 is a block diagram showing an example of a conventional synchronization detecting device.

FIG. 5 is a block diagram showing another conventional synchronization detecting device.

[Explanation of symbols]

 3a to 6a Bit shift instruction 3b to 6b Channel shift instruction 1-bit serial / parallel converter 2 byte serial / parallel converter 3-5 Low-speed synchronization unit 7 Serial STM-4 multiplexed signal 8 Parallel STM-4 multiplexed signal 11, 13 Detection Signal 12, 14-bit phase signal 15 Frame loss signal 16 Channel loss signal 17, 18, 19, 63, 64 Control signal 20, 65 Initialization signal 23 to 26 Parallel STM-1 signal 30 Frame pattern detection circuit 31 Frame pattern detection circuit 32 Second frame pattern detection circuit 33 Frame synchronization detection protection circuit 34 Channel synchronization detection protection circuit 35 Channel phase shift calculation circuit 36 Bit phase shift determination circuit 37, 62 Control circuit 38 OR circuit 39 Logical product circuit 60 STM-N frame synchronization detection / protection circuit 61 N-channel separation circuit

Claims (1)

(57) [Claims] 1. A synchronization detector for detecting frame synchronization and channel synchronization of a signal passed through a bit serial / parallel conversion circuit and a byte serial / parallel conversion circuit, and controlling the operations of the bit serial / parallel conversion circuit and the byte serial / parallel conversion circuit. In the apparatus, when the byte serial / parallel conversion circuit divides an input signal into a signal having the number of channels N, a first frame pattern detection circuit for detecting a frame pattern of a bit shift of an N channel signal; A second frame pattern detection circuit for detecting a frame pattern with a bit shift of the following, and calculating a channel phase shift based on a detection signal of the first frame pattern detection circuit, N low-speed synchronizers including a channel phase shift calculating circuit for outputting a channel shift instruction are provided. Detection device.