JPH0451730A - Stm-n frame synchronizing system - Google Patents

Abstract

PURPOSE:To easily and simply attain frame synchronization without considerable dependency on number of multiplexing and need of channel ID information by demultiplexing and expanding an STM-N-frame format form transmission data from an optional bit location into N-series in the unit of bytes and monitoring any output signal series STM-1. CONSTITUTION:An STM-N-frame format form transmission data 1 is subjected to demultiplex and expansion by N-channel data for each 8-bit at an 8-bit demultiplex section 2 to be N-series of output signal series STM-1 (31-3N). A delimiter between frame synchronization patterns A1, A2 is detected while the output signal series STM-1 (31-3N) passes through a frame synchronization collation section 4, and aligner 5 applies bit location shift correction and rearrangement control to each of the N-series of output signal series STM-1 (31-3N) based on the detection. Thus, the N-series of output signal series STM-1 (STM-11-STN-1N) are easily obtained from the aligner 5.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention applies to the STM-N frame synchronization method for STM-N frame format multiplexed transmission data using synchronous multiplexing recommended in CCITY G, 707-G, 709. Accordingly, by detecting two types of frame synchronization pattern rotation cut positions from STM-N frame format multiplexed transmission data, frame synchronization can be achieved easily and without greatly depending on the number of multiplexes. -N frame synchronization method.

[Prior art] Does CCITT G, 707-G709 recommend a worldwide unified digital synchronous hierarchy (SDI) network node interface?
In the H structure, using STM-1 as a basic frame, a higher order group signal STM-N (N: integer) is constructed by synchronous multiplexing. By the way, ST according to the prior art
Regarding the M-N frame synchronization method, for example,
5DN frame synchronization control system" (IEICE technical research report 0QE89-79-80 (Kokiko Electronics, November 20, 1989, pages 19-24) is known. In this case, frame synchronization patterns are detected for each of the N lines separated and developed in STM-1, and synchronization phase control is performed based on these results.

On the other hand, "A Study of Frame Synchronization Control Methods in F-Byte Multiplex High-Speed Transmission Systems" (IEICE Spring National Conference, 1
989) Proceedings B-433), the output signal sequence S is separated and expanded into N sequences by the separation unit (DMUX).
Byte multiplex synchronization based on a frame synchronization pattern from any one of TM-1 should be ensured first, and then channel synchronization based on channel ID information should be ensured.
Separation and development in the separation unit (DMUX) is controlled.

[Problems to be Solved by the Invention] However, in the case of the above-mentioned conventional technology, a frame synchronization pattern is detected in each STM-1 obtained by separation expansion, or eight types of frame synchronization pattern bits ( Separation and expansion at the separation section is controlled based on the channel ID information (consisting of 48 bits) and channel ID information. When used for applications that require high reliability, such as relaying between stations, a certain effect can be expected, but especially in the former case, the number of multiplexes N
The scale of the logic circuit for the frame synchronization circuit largely depends on the value of .

An object of the present invention is to provide an STM-N frame synchronization method that does not depend greatly on the number of multiplexes and also makes it possible to synchronize frames simply and without the need for channel ID information.

[Means for Solving the Problems] The above purpose is to separate and expand STM-N frame format transmission data into N series in byte units from that position by using an arbitrary bit position as a byte unit delimiter position on the separate expansion. However, by monitoring any one output signal sequence in byte units among the separated and expanded N output signal sequences STM-1, the byte unit frame included in that signal sequence can be determined. Synchronization pattern A
After detecting the byte unit break position in data transmission from the bit position misalignment state of each lA2,
By comparing the bit states at predetermined bit positions according to the bit position deviation amount between the N output signal series 87M-1, the delimiting position between the frame synchronization patterns At and A2 is detected, and the delimiting position is calculated from this delimiting position. STM
This is achieved by obtaining N output signal sequences STM-1 in a frame synchronized state based on the frame head position of the -N frame format transmission data.

[Function] STM-N frame format transmission data includes:
From the beginning of the frame, start with the frame synchronization pattern AI (
The bit pattern is expressed in hexadecimal and “F6”) is 3XN
After the byte continues, the frame synchronization pattern A2 (its bit pattern is "28" in hexadecimal notation) continues for 3×N bytes, and so on, and the frame synchronization pattern is inserted. Therefore, the STM-N frame format transmission data containing these two types of frame synchronization bit patterns is separated into N sequences in bytes from that position by using an arbitrary bit position as a byte-by-byte delimiter position in the separation expansion. If it is expanded, frame synchronization patterns A1 and A2 with bit positions shifted will appear in each of the separated and expanded N output signal sequences 87M-1, but any one output signal sequence S
By monitoring TM-1, the byte unit delimiter position on the transmitted data can be detected from the bit position shift. After the byte unit delimiter position on the transmission data is detected, N series of bit states are output at a predetermined position according to the amount of bit position deviation from the end position of the frame synchronization pattern Al in the bit position deviation state. By comparing the signal sequences 87M-1, the delimiting position between frame synchronization patterns AI and A2 and the output signal sequence STM-1 including this delimiting position are detected. From this delimiting position, it is immediately required that the frame start position is 3XN bytes before the delimiting position, so based on the frame start position,
N-sequence output signal sequence STM-1 in frame synchronization state
can be easily obtained.

Specifically, based on the frame start position of the STM-N frame format transmission data, the byte unit delimiter position on the separated expansion for the transmission data is updated for each of the N series output signal sequences 87M-1 that are separated and expanded. By controlling and separating and expanding at a new byte unit delimiting position, an N-series output signal sequence STM-1 in a frame synchronized state is obtained. Alternatively, based on the frame start position of the STM-N frame format transmission data, bit position shift correction and rearrangement are performed for each of the N series output signal series 87M-1 separated and expanded at arbitrary byte unit delimiting positions. Then, the N-sequence output signal sequence STM-1 in a frame-synchronized state can be easily obtained.

[Example] The present invention will be explained below with reference to FIGS. 1 to 13.

First, a separation unit (DMUX) including various circuits according to the present invention as peripheral circuits will be described. FIG. 1 shows an example of the configuration.

As shown, STM-N'7 as external input data
Frame format transmission data 1 is separated and expanded as serial data by an 8-bit separation unit 2 every 8 bits, that is, for N channels in byte units, to generate N output signal sequences STM-1 ( 3, to 3□) are obtained, but these N series output signal series STM-1 (3
1 to 3N) are passed through the frame synchronization matching section 4, the delimiting position between the frame synchronization patterns A1 and A2 is detected, and based on this, the aligner 5 outputs the N series output signal series STM-1 (31 to 3%). By performing bit position shift correction and rearrangement control for each, N-sequence output signal sequences STM-1 (STM=1. to STM-IN) in a frame synchronized state can be easily obtained from the aligner 5. It has become something that can be done.

Here, to explain the STM-N frame format transmission data 1, the transmission format is the second
As shown in the figure. As shown, the frame is 125
It has a cycle of μsec, and is configured to contain 2430XN bytes of various data. At the beginning of the frame, there is a frame synchronization pattern AI (3XN bytes) and A2 (3XN bytes) for frame synchronization.
XN bytes) are inserted in the order shown, followed by channel identification (ID) numbers C1, ~C1, N
Bytes have been inserted.

Now, returning to FIG. 1 again for explanation, the frame synchronization matching unit 4 is a part directly related to the present invention, and as shown in the figure, it is a part of the output signal series STM-1 (31 to 3.). A first frame synchronization detection circuit 6 provided corresponding to one of the output signal series STM-1 (3, to 3.), a second frame synchronization detection circuit 7 provided in common to the output signal series STM-1 (3, to 3.), and an output signal series ST
Latch circuit 81 provided for M-1 (3, to 3N)
~8N.

In this example, the first frame synchronization detection circuit 6 is provided in the output signal series STM-H3,).
The frame synchronization detection circuit 6 outputs a signal sequence STM-
Frame synchronization patterns A1, A appearing in 1(3,)
2 are now being monitored. More specifically, in the first frame synchronization detection circuit 6, while the output signal series STM1 (3N) from the 8-bit separation unit 2 is passed through in the through mode, the output signal series STM
-1 (3N) 8 bits are frame synchronization pattern A1.
It is detected which of eight types of bit shift states each of A2 corresponds to.

FIG. 3 shows an example of separation and development of frame synchronization patterns A1 and A2 included at the beginning of the frame. The symbol in the figure indicates the byte unit delimitation position on the separation expansion in the 8-bit separation unit 2.
This byte unit delimiter position is indicated by a vertical solid line in the separated expansion state. The vertical broken lines in the figure also indicate the byte unit delimitation positions in data transmission, and the vertical thick solid lines indicate the delimitation positions between the frame synchronization patterns At and A2 (which are also the dashed line display positions), respectively. It can be seen that the byte unit delimiter position above is shifted by several bits from that in data transmission. This amount of deviation is the output signal sequence S that is separated and expanded as it is.
This value is common to each of TM-1 (3, to 3N). Here, in each of the output signal series STM-1 (3, to 3.),
The frame synchronization pattern AI with the same bit shift state appears at least twice, and the same situation holds true for the frame synchronization pattern A2. Therefore, frame synchronization pattern A in a bit misaligned state
By continuously detecting lA2 at the frame period, it is possible to easily know the amount of bit shift between the byte unit delimiting position on separation expansion and the byte unit delimiting position on data transmission.

That is, once each of the frame synchronization patterns A1 and A2 is detected at least twice in the initial state or hunting state, a backward protection operation is entered and it is determined whether or not the frame synchronization patterns A1 and A2 continuously exist in the frame period. is designed to be detected. This is because the data may contain a pseudo frame synchronization pattern. Continuous detection of frame synchronization patterns A1 and A2 in a frame period for a predetermined number of times indicates that the frame synchronization patterns are frame synchronization patterns, and furthermore, the bit position shift state of the frame synchronization patterns A1 and A2 indicates that the bytes in data transmission This means that it can be detected as a state in which the unit break position has been determined. Therefore, in general, byte unit delimiter positions in data transmission are at least consecutive for each of frame synchronization patterns A1 and A2 in a bit position shift state with forward protection operation in each frame period. Detection is performed for the first time by performing two detections consecutively in a frame period for the number of backward protection stages. Therefore, during detection by backward protection, the bit state at a predetermined bit position corresponding to the amount of bit position deviation from the end position of the frame synchronization pattern A1 in the bit position deviation state is detected by the latch circuit 8.
~8N to the second frame synchronization detection circuit 7 as the extracted bit signal 11, and by comparing between the N output signal series STM-4 (3, ~3,),
The break position between frame synchronization patterns A1 and A2 and the output signal sequence including the break position can be detected.

FIG. 4 shows a specific example of the separated and expanded four output signal sequences STM-1 (3, to 34) when the value of N is 4, and the delimiting positions between frame synchronization patterns A1 and A2. It is shown to include.

If the output signal sequence STM-1(3,) is to be monitored,
The frame synchronization pattern A1 within range B is rotated by 2 bits to the left, and the bit position from the end position of the frame synchronization pattern AI (this position is also the byte unit delimiter position on the separation expansion) By comparing the bit states at predetermined bit positions corresponding to the amount of deviation between the output signal series STM-1 (3° to 34), the delimiting position between frame synchronization patterns A1 and A2 can be known. The bit shift amount to the left is k(
It is an integer value from 0 to 7, in this example 2), and if the possible values of l are 1.2.4 to 7, then 8- + 1 value (
If the value is 9 or more, 8 is subtracted.) The bit state at the bit position defined by 8 is obtained as the extracted bit signal 11. In this example, the values 2 to 5.7.8 are obtained by adding +1 to 8-, but the bits indicated by these values from the end position of the byte division on the output from the 8-bit separator 2 The bit state at position is clearly the output signal sequence STM 1(3*
~34) do not match, and among those bit positions,
By detecting a bit mismatch at any bit position, the position of the break between frame synchronization patterns A1 and A2 can be known.

From this delimiter position, the frame start position can be determined as 3×N bytes before. Immediately after the delimiter position between frame synchronization patterns A1 and A2 is detected, a signal 9 indicating that the number of backward protection stages has been reached is sent to the first frame synchronization detection circuit 6.
If so, the second frame synchronization detection circuit 7 notifies the aligner 5 of the signal 10 including the frame head position, but based on this, the aligner 5 outputs the N series of output signal series STM-1 (3, to 3N). For each, N output signal sequences S T M 1 (31-3.) For each,
By performing bit position shift and rearrangement control, the aligner 5 outputs an N-series output signal sequence STM-1 (STM-1, ~STM-1,
) can be easily obtained.

FIG. 5 also shows the configuration of the separation unit <DMUX) in another example which includes various circuits according to the present invention as peripheral circuits. The differences from what is shown in Figure 1 are as follows.
Latch circuit 8 on the rear side of aligner 5. -8H and a rear frame synchronization detection circuit 12, which has the functions of the second frame synchronization detection circuit 7, and -12tt are provided. Based on the amount of bit position deviation between the byte unit delimiter position on data transmission from the first frame synchronization detection circuit 6, the aligner control circuit 13 determines the byte unit delimiter position on data transmission for separation expansion. By controlling the aligner 5 to make them match, the aligner 5 outputs an N-series output signal sequence STM with the bit position shift corrected.
-1 (3, ~3.) is obtained. Thereafter, for each of the N output signal sequences STM-1 (31 to 3N) whose bit position shifts have been corrected, the rear frame synchronization detection circuit 12. By performing rearrangement control under the control of ~12N, the aligner 5 outputs the N-series output signal sequence STM-1 (S
TM-1, ~STM-IN) can be obtained.

Although the present invention has been described in detail above, if an aligner is not particularly provided, the 8-bit separation unit may be directly controlled. N-series output signal sequence 87M separated and expanded based on the frame head position detected by the present invention
-1 If the byte unit delimiter position on the separate expansion for transmission data is updated and controlled for each,
By separating and expanding the STM-N frame format transmission data l at a new byte-unit delimiting position, the 8-bit separation unit can obtain an N-series output signal sequence STM-1 in a frame synchronized state. It is something that can be done.

Next, the processing according to the present invention for the STM-N frame format transmission data 1 when the value of N is 4 will be described in more detail as follows.

That is, FIG. 6 shows the manner in which frame synchronization patterns At and A2 are transmitted on frames in the case of STM-4. As shown, data X in the previous frame
This is followed by 12 consecutive frame synchronization patterns A1.
bytes (Al#l to A1#12), and following this, the frame synchronization pattern A2 is 12 bytes (A2
#l to A2#12), and subsequently, a channel identification (ID) number of 4 bytes (C111 to C1#4) is inserted. However, channel identification (ID
) number is unnecessary in the frame synchronization method according to the present invention.

Now, frame synchronization pattern A1. A2 is transmitted in a byte-multiplexed state, and the mark indicates the actual byte unit delimiting position in data transmission. However, in the 8-bit separation unit, the frame synchronization pattern A1
, the frame has 4 channels a without being aware of A2.
Separate expansion is performed in byte units to obtain -d minutes, and the mark indicates the byte unit break position in the separated expansion "2" as an example. Various data in the frame are separated and expanded in byte units at the ↑ position, but Fig. 7 shows the separated and expanded data corresponding to channels a to d as serial numbers, and Fig. 8 shows them as serial numbers. This shows the data more specifically.

That is, in FIG. 7, the numbers shown in [ ] indicate the serial numbers attached to the byte unit data shown in FIG. This indicates that the data is compatible with a. In the present invention, frame synchronization can be achieved by focusing on the separated expanded data corresponding to any one of the separated expanded data corresponding to channels a to d.

Here, as shown in FIG. 9, if we focus on the separated and expanded data corresponding to channel d, for example, the frame synchronization pattern A1 included in these byte unit separated and expanded data is the frame synchronization pattern A1 itself as it is. The probability of being included in the state is 178, and generally it is included as a bit-missing state. Since there are seven types of bit shift states in total, there are eight types of states in which frame synchronization pattern A1 can exist. The existence of the frame synchronization pattern Al in the byte-by-byte separated expanded data is known by detecting the frame synchronization pattern Al in any bit-shifted state.

FIG. 10 shows a comparison of separated and expanded data corresponding to channels d and b. In this case, in the separated expanded data corresponding to channel b, there is a separation position between frame synchronization patterns A1 and A2 (indicated by a broken line in the vertical direction). ), but the number of times frame synchronization patterns A1 and A2 are detected differs depending on whether or not the separation position between frame synchronization patterns A1 and A2 is included in the separated and expanded data. In the separated expanded data corresponding to channel d that does not include the delimiter position between frame synchronous patterns A1 and A2, each frame synchronous pattern AlA2 is detected three times in a row, but in the separated expanded data corresponding to channel b, the frame synchronous patterns A1 and A2 Each is detected only twice. Therefore, regardless of which channel the separated expanded data is focused on, each of the frame synchronization patterns A1 and A2 will be detected at least twice in succession. By utilizing this fact, it can be confirmed that such frame synchronization patterns A1 and A2 are regular frame synchronization patterns A1 and A2, based on the fact that the detection manner of such frame synchronization patterns A1 and A2 is carried out in the number of backward protection stages at the frame period. Furthermore, the bit shift between the byte unit delimiter position and the byte unit delimiter position during data transmission can be known. In this example, frame synchronization patterns A1 and A2 are both detected as being shifted by 2 bits to the left, so the byte unit delimiter position in data transmission is 2 bits earlier than that in separate expansion. , or 6-bit I・later.

As described above, the byte-by-byte delimiter position in data transmission can be definitely known.

However, the frame synchronization pattern on the frame ^
1. Although the location of A2 is roughly known, the frame head location remains unknown. In the present invention, the leading position is frame synchronization pattern A1. This can be determined based on the A2 section delimiter position.

If the delimiter position is known, the frame start position can be immediately known as 12 bytes earlier. FIG. 11 shows the data shown in FIG. 8 by focusing on its continuity and showing the connection relationship. As can be seen, after the last frame synchronization pattern A1 on channel d, the serial number [1
3] to [16], the bit states are not necessarily the same depending on the bit position.
From the bit state at such a bit position, the separated expanded data, ie, the channel, in which the delimiter position between frame synchronization patterns A1 and A2 exists can be known. Since the delimiting position between the frame synchronization patterns A1 and A2 is also the byte unit delimiting position in data transmission, the delimiting position between the frame synchronization patterns A1 and A2 on the channel can be known. After all, the data shown in FIG. 11 is roughly divided into sets corresponding to frame synchronization patterns A1 and A2, as shown in FIG. If bit position shift correction and rearrangement are performed on the separated expanded data corresponding to the expanded position or channel me d, separated expanded data in a frame synchronized state can be obtained corresponding to channels a to d. 1st
FIG. 3 shows channel mill d-corresponding separation expansion data from the aligner in the case where bit position shift correction and rearrangement are performed in the aligner, but no particular explanation is required for this.

[Effect of the invention] As explained above, according to the present invention, S'['M−N
There is an effect that frame synchronization can be easily achieved for frame format transmission data without greatly depending on the number of multiplexes and without channel ID information.

[Brief explanation of the drawing]

FIG. 1 and FIG. 5 are diagrams each showing an example of the configuration of a separation section that is equipped with various circuits according to the present invention as peripheral circuits, and FIG. 2 is a diagram showing the configuration of an STM-N frame format transmission data. 3 is a diagram showing an example of a separated development state for the frame synchronization patterns A1 and A2 included at the beginning of the frame, and FIG. 4 is a diagram showing the transmission format when the value of N is 4. In the case of
FIG. 6, FIG. 7, and FIG. 8 are diagrams showing specific examples of the separated and developed four-series output signal sequence STM-1, including the delimiter positions between frame synchronization patterns A1 and A2. Figures 9, 10, 11, 12, and 13 are
FIG. 3 is a diagram for explaining in detail the frame synchronization principle according to the present invention for STM-4. 2... 8-bit separation section 4... Frame synchronization checking section 5... Aligner 6... First frame synchronization detection circuit 7... Second frame synchronization detection circuit 81 to 8N... Latch circuit 121~12N...Rear frame synchronization circuit 13...
Aligner control circuit Fig. 1 2 gshi-J aid 4' frame nke 11 tot part 57 fire 6:1 ltyv-mu anti-I-slide 1pu 0% 7, easy Z7V-mu 11th period ellipse ■Rei 81~8N 7) + [il trunk

Claims (1)

[Claims] 1. CCITTG. 707~G. The STM-N frame format transmission data related to the synchronous multiplex transmission method recommended in G.709 is separated and expanded into N sequences in byte units from the arbitrary bit position as the byte unit delimiter position on the separation expansion. In addition, by monitoring any one output signal sequence among the N separated and expanded output signal sequences STM-1 in units of bytes based on the byte unit break position on the separated expansion, the signal sequence is Byte-by-byte frame synchronization patterns A1 and A included in
2. After detecting the byte-by-byte delimiting position in data transmission from each bit position misalignment state, a predetermined bit position corresponding to the above-mentioned bit position shift amount from the end position of frame synchronization pattern A1 in the bit position misalignment state is detected. By comparing the bit states of N output signal sequences STM-1, the break position between frame synchronization patterns A1 and A2 is detected, and the frame start of the STM-N frame format transmission data determined from the break position is detected. An STM-N frame synchronization method that obtains N output signal sequences STM-1 in a frame synchronization state based on the position. 2. The byte unit delimiter position in data transmission is STM
- At least two consecutive detections of each of the frame synchronization patterns A1 and A2 in a bit misaligned state with forward protection operation in every N frame format cycles, consecutively in STM-N frame format cycles. 2. The STM-N frame synchronization method according to claim 1, wherein the STM-N frame synchronization method is detected for the first time by performing the same number of backward protection stages. 3. Based on the frame start position of the STM-N frame format transmission data, the byte unit delimiter position on the separated expansion of the transmission data is updated and controlled for each of the N series of output signal sequences STM-1 that are separated and expanded. In addition, by separating and expanding at a new byte unit delimiting position, N-series output signal sequences STM-1 in a frame synchronized state can be obtained.
2. The STM-N frame synchronization method according to any one of 2. 4. Based on the frame start position of the STM-N frame format transmission data, bit position shift correction and rearrangement are performed for each of the N series output signal series STM-1 separated and expanded at arbitrary byte unit delimiting positions. , N output signal sequences STM-1 in a frame synchronized state are obtained.
The STM-N frame synchronization method according to any one of the above.