JP2944322B2 - Data multiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data multiplexer, and more particularly, to a data multiplexer having a frame synchronization circuit.

[0002]

2. Description of the Related Art A data multiplexing apparatus transmits a frame synchronization signal in addition to a data signal, and performs multiplexing based on the frame synchronization signal. An operation of detecting the frame synchronization signal arranged at a specific position in the frame on the receiving side of the data multiplexing apparatus and synchronizing the frame on the receiving side is called frame synchronization. The state in which the bit position of the frame synchronization signal is correctly detected is the frame synchronization state, the state in which the bit position is not correctly detected is the frame synchronization loss state, the transition from the frame synchronization loss state to the frame synchronization state is the frame synchronization recovery step, and the time required for the process. Is called a frame synchronization return time.

The main requirements to be considered in designing a frame synchronization scheme are as follows. 1) The frame synchronization recovery time is short. 2) Loss of synchronization due to disturbances such as transmission errors during frame synchronization is unlikely to occur. 3) In the process of restoring frame synchronization, a frame synchronization state is not established at an incorrect position.

Conventionally, this type of data multiplexing apparatus has a configuration shown in FIG. FIG. 3 is a block diagram of a conventional example. On the transmitting side, the transmission main data signal 201, the synchronization pattern 203 for frame synchronization generated from the synchronization pattern generator 23, and the transmission
The multiplex unit 21 multiplexes the multiplexed signal 204 and sends out the multiplexed signal 204 to the line. On the receiving side, the multiplexed signal 208 received by the DMUX unit 22 is separated into each signal before multiplexing. At this time, the detector 24 detects frame synchronization loss based on the separated synchronization pattern.
5, the frame synchronization is restored to the DMUX unit.
The control data signal is a control signal for performing remote control of the partner device.

FIG. 4 shows a data format of a multiplexed signal of the data multiplexing apparatus shown in FIG. The bit width of each signal is fixed, the bit width of one frame is m bits,
If n bits are assigned to the control data signal and the synchronization pattern, the data bits of the main signal are m-2
It has n bits.

[0006]

The frame synchronization signal is 1
The greater the number of bits per frame, the shorter the time for erroneous detection of frame synchronization and the recovery time of out-of-synchronization, thereby improving the reliability of data transmission. However, the number of bits of the main data signal is reduced by that amount, resulting in poor data transmission efficiency. . On the other hand, when the number of bits of the frame synchronization signal is small, the data transmission efficiency is improved, but it takes time to detect erroneous synchronization or recover from loss of synchronization. Error detection of synchronization can be solved by increasing the number of protection stages, but the recovery time upon loss of synchronization is not shortened.

That is, since the bit width of the frame synchronization signal is fixed, there is a problem that the two requirements of data transmission efficiency and a short recovery time upon loss of synchronization cannot be simultaneously satisfied.

[0008]

A data multiplexing apparatus according to the present invention comprises a 1-bit synchronization pattern generator for generating a 1-bit width synchronization pattern and a n-bit (n is an integer of 2 or more) bit width synchronization pattern. An n-bit synchronous pattern generator to be generated;
A selector for selecting one of the output signals of the bit synchronization pattern generator; and an output signal of the selector and m (m is n
A MUX unit for multiplexing and transmitting the main data signal of -n-1 bits and the output signal of the 1-bit synchronization pattern generator, and receiving each multiplexed multiplexed signal and each signal before multiplexing. A DMUX unit for separating the
A first detector for detecting a synchronization state of the 1-bit width synchronization pattern separated by the unit, a second detector for detecting a synchronization state of the separated n-bit width synchronization pattern, A control unit that outputs the switching signal when the frame synchronization loss is determined from the output signal of the second detector and switches the output of the selector.

In particular, the control unit is configured to control the switching signal to output the control data signal when the selector outputs the control data signal when there is no output signal from the second detector and the output signal from the first detector indicates a synchronous state. When the output signal of the first detector indicates an out-of-synchronization state or when the output signal of the second detector is present, the selector outputs the n-bit width synchronization pattern. Is output.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the present invention. First, the function of the transmitting side will be described. The synchronization pattern generator 1 is a 1-bit pseudo-random pattern generation circuit, which monitors whether or not frame synchronization has been established.
03 is generated. The synchronization pattern generator 2 is a pseudo random pattern generation circuit having the same n-bit width as the control data signal 102, and generates a synchronization pattern 105. Main data signal 101 and control data signal 102 selected by selector 3 or synchronization pattern 105 and synchronization pattern 10
3 and multiplexed by the MUX unit and output as a multiplexed signal 104.

Next, the receiving section will be described. Multiplexed signal 1
Reference numeral 10 denotes a signal which is separated into signals before multiplexing by the DMUX unit 9 and output as a main data signal 106. The 1-bit synchronization pattern is compared with a predetermined synchronization pattern by the detector 6 and compared. The detection signal 108 is output to the control unit 5 and the resynchronization unit 8. The detector 7 compares the n-bit synchronization pattern signal with a predetermined synchronization pattern and outputs the result as a detection signal 109 to the control unit 5 and the resynchronization unit 8.

When receiving a control data signal instead of the n-bit synchronization pattern signal, the DMUX unit 9 outputs a control data signal 107. The control unit 5 determines the presence / absence of loss of synchronization from the input detection signals 108 and 109, and switches the selector according to the switching signal 110. Further, the re-periodizing unit 8 uses the detection signal 108 or 109 to
The UX unit 9 is resynchronized.

Next, the procedure for synchronizing the control units will be described. When the frame synchronization with the partner station is completely established and in a synchronized state, the frame synchronization signal transmits and receives only a 1-bit synchronization pattern. Therefore, the selector 3 selects and sends the control data signal 102. When the detector 6 detects an out-of-synchronization state from this state, the control unit 5 inverts the switching signal 110 based on the detection signal 108, and
The selector 3 selects and transmits the n-bit synchronization pattern 105.

At the partner station, an n-bit synchronization pattern signal is detected by the detector 7, and the control unit 5
Inverts the switching signal 110, and the selector 3 sends an n-bit synchronization pattern 105. As a result, even in the own station, the detector 1 detects an n-bit synchronization pattern, and the resynchronization unit 8 performs resynchronization based on the detection signal 109.
In this case, resynchronization is performed using an n-bit synchronization pattern, so that the synchronization recovery time is short. After synchronization recovery, both stations control unit 5
The switching signal 110 returns to the original state, and the selector 3 selects and sends the control data signal 105 again. Although the control data signal cannot be transmitted while the n-bit synchronization pattern is transmitted, it is a short time and does not cause a great problem.

Next, the data format of the multiplexed signal will be described. In FIG. 2A, if one frame is m bits in the data format at the time of synchronization recovery, it is allocated to a frame synchronization signal of n + 1 bits and a main data signal of mn-1 bits. In FIG. 2B, if the data format at the time of synchronization establishment is m bits per frame, it is allocated to a 1-bit synchronization signal, n-bit control channel data, and a mn-1 bit main data signal.

[0017]

As described above, according to the present invention, the bit width of the signal for frame synchronization is changed between the case where the signal is out of synchronization and the case where the signal is synchronized, and the bit width is increased only when the signal is lost. Therefore, the frame synchronization recovery time can be shortened, and the transmission efficiency is not reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a data format of a signal in FIG. 1;

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a data format of a signal in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronous pattern generator 2 Synchronous pattern generator 3 Selector 4 MUX part 5 Control part 6,7 Detector 9 DMUX part 101,106 Main data signal 102,107 Control data signal 104,110 Multiplex signal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-280528 (JP, A) JP-A-57-30436 (JP, A) JP-A-61-210735 (JP, A) JP-A-1- 160226 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H04J 3/00-3/26 H04L 7/08

Claims (2)

(57) [Claims] 1. A method for generating a synchronization pattern having a width of 1 bit.
A bit synchronization pattern generator and n (n is an integer of 2 or more)
An n-bit synchronization pattern generator for generating a bit width synchronization pattern, a selector for selecting one of an n-bit control data signal and an output signal of the n-bit synchronization pattern generator by a switching signal, and an output of the selector Signal and m
(M is an integer equal to or greater than n) A MUX unit for multiplexing and transmitting the (n-1) -bit main data signal and the output signal of the 1-bit synchronization pattern generator, and receiving and multiplexing the multiplexed multiplexed signal. A DMUX unit for separating each of the previous signals, a first detector for detecting the synchronization state of the 1-bit width synchronization pattern separated by the DMUX unit, and a synchronization state of the separated n-bit width synchronization pattern. A second detector for detecting, and a control unit for outputting the switching signal when the frame synchronization loss is determined from the output signal of the first or second detector and switching the output of the selector. Data multiplexing device. 2. The switching signal, wherein the selector outputs the control data signal when there is no output signal of the second detector and the output signal of the first detector indicates a synchronization state. When the output signal of the first detector indicates an out-of-synchronization state or when the output signal of the second detector is present, the selector outputs the n-bit width synchronization pattern. 2. The data multiplexing device according to claim 1, wherein