JPH08163069A - Multiplex converter - Google Patents

Abstract

PURPOSE: To prevent an error in recovery data signal caused by insertion of a synchronization pattern and deterioration in the quality of the signal in the multiplex converter comprising a transmission section applying asynchronous sampling to plural data signals and inserting a synchronization pattern to generate a multiplex signal and a reception section detecting the synchronization pattern to recover plural data signals. CONSTITUTION: A transmission section is provided with a transmitter side distortion reduction circuit 1 that inserts an inverted synchronization pattern when a detection position by a data signal change point detection circuit 8 and a selected position of a synchronization pattern insertion selection circuit 6 are coincident and that inserts a noninverted synchronization pattern when dissident. A reception section is provided with a receiver side distortion reduction circuit 11 that inserts one-preceding bit data to an inserted position of the synchronization pattern as they are when the synchronization patterns are coincident and that inserts inverted one-preceding bit data to the inserted position of the synchronization pattern when part of the synchronization pattern is inverted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex conversion apparatus for asynchronously sampling a plurality of data signals and taking them into the apparatus for multiplexing.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing the configuration of a conventional multiplex conversion apparatus, wherein FIG. 3A is a block diagram on the transmission side, and FIG. 3B is a block diagram on the reception side.

In FIG. 3A, a plurality of sampling circuits 102 provided on the transmission side are circuits for asynchronously sampling a plurality of input data signals with a sample clock having a higher frequency than the data signals. The multiplexing unit 103 is a circuit that time-division multiplexes a plurality of sampling signals sampled by the sampling circuit 102. Transmission side synchronization pattern generation circuit 10
Reference numeral 4 denotes a circuit for generating a synchronization pattern to be inserted on the transmission side, and the timing generation circuit 105 is a circuit for generating timing for inserting each bit constituting the synchronization pattern one bit at a time for each frame. The synchronization pattern insertion selection circuit 106 is a circuit that inserts a synchronization pattern into the multiplexed signal under the control of the timing generation circuit 105.

In FIG. 3B, a receiving side synchronization pattern generating circuit 115 is a circuit for generating a receiving side synchronizing pattern, and generates the same pattern as the transmitting side. The synchronization pattern detection circuit 114 is a circuit for detecting the synchronization pattern of the multiplexed signal from the synchronization pattern generated by the reception-side synchronization pattern generation circuit 115, and the separation circuit 113 synchronizes with the detected synchronization pattern and performs multiplexing. This is a circuit for separating a signal into a plurality of received data. The decoding circuit 112 performs a process of reproducing a data signal from each of the separated received data.

In the above configuration, for example, when there are nine data signals on the transmission side and each data signal is sampled in 8-bit units, each sampling signal sampled by the sampling circuit 102 is multiplexed by the multiplexer 103. The time division multiplexed signal has 72 bits as one frame. Subsequently, the transmission-side synchronization pattern generation circuit 10
4, the timing generation circuit 105 and the synchronization pattern insertion selection circuit 6 crush the first 1 bit (frame bit) in each frame and insert the synchronization pattern. This synchronization pattern is, for example, 12 frames, that is, 12
It is composed of an arbitrary bit string having bits, and the receiving side recognizes the synchronization pattern by detecting the repetition of this arbitrary bit string.

Next, on the receiving side, the input multiplexed signal has a synchronizing pattern detected by the receiving side synchronizing pattern generating circuit 115, the synchronizing pattern detecting circuit 114, and the sample clock sent from the transmitting side. In synchronization with the above, the separation circuit 113 separates the received data into nine pieces. Each of the separated received data is reproduced by the decoding circuit 112 into a data signal.

[0007]

However, in the above-described conventional multiplex conversion apparatus, one of the plurality of reception data separated by the separation circuit on the receiving side is output with the synchronization pattern other than the data inserted. It had been. Therefore, in the terminal that receives this data signal, it becomes impossible to correctly recognize the change point of the data signal, especially when the change point of the data signal and the insertion position of the synchronization pattern match.
There has been a problem that an error due to sampling is increased to cause jitter and the like, and the quality of a transmitted signal is degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and it is intended to prevent an error in a reproduced data signal caused by insertion of a synchronization pattern, thereby improving signal quality. It is an object of the present invention to provide a multiplex conversion device without deterioration.

[0009]

In order to achieve the above object, in the multiplex conversion apparatus of the present invention, a plurality of data signals are asynchronously sampled, respectively, and a synchronization pattern for identifying each frame is inserted to obtain a multiplexed signal. In the multiplex conversion device configured by a transmitting unit that generates a received signal and a receiving unit that detects a synchronization pattern from the received multiplexed signal and separates the received data into a plurality of received data, the transmitting unit includes: When the detection position of the change point of the data signal and the insertion position of the synchronization pattern match, the synchronization pattern is inverted and inserted, and the detection position of the change point of the data signal and the insertion position of the synchronization pattern are When they do not match, it has a distortion reducing circuit on the transmission side that inserts the synchronization pattern as it is, and the reception unit receives the synchronization pattern previously inserted in the reception data. When the same sync pattern as that of the transmitter generated by the receiver matches, the same data as the previous bit data is inserted at the position where the sync pattern was inserted, and a part of the sync pattern is It is characterized in that it has a receiving side distortion reduction circuit for inserting the data obtained by inverting the previous bit data at the position where the synchronization pattern was inserted when the data is inverted.

At this time, the transmission side distortion reduction circuit compares the transmission side delay circuit for delaying the asynchronously sampled data signal by 1 bit, the output signal of the transmission side delay circuit and the asynchronously sampled data signal. Then, a change point detection circuit for detecting a change point of the data signal, a transmission side inverter circuit for inverting the synchronization pattern, and an output of the change point detection circuit to output the synchronization pattern or the transmission side inverter circuit. And a sync pattern polarity selection circuit that selects one of the outputs, and the reception-side distortion reduction circuit includes a sync pattern inverter circuit that generates an inverted signal of the sync pattern, an output of the sync pattern inverter circuit, and a multiplexed signal. From the coincidence detection circuit that detects the inverted bit in the sync pattern from A separation control circuit for generating a timing for separating the multiplexed signal into a plurality of reception data based on the output result and the output of the coincidence detection circuit, and a receiving side for detecting the bit data immediately before the position where the synchronization pattern was inserted. A delay circuit, a reception-side inverter circuit that inverts the output of the reception-side delay circuit, and an output of the separation control circuit cause either the output of the reception-side delay circuit or the output of the reception-side inverter circuit to have a synchronization pattern. It may be constituted by a data insertion selection circuit which is inserted at the position where the data was inserted.

[0011]

The multiplex conversion apparatus configured as described above, on the transmitting side, inverts the data of the corresponding bit in the synchronization pattern when the detection position of the change point of the data signal coincides with the synchronization pattern insertion position. If the detected position of the change point of the data signal does not coincide with the insertion position of the synchronization pattern, the data of the corresponding bit is inserted according to the synchronization pattern as it is to synchronize with the detection position of the change point of the data signal. Information on whether the pattern insertion position matches or does not match is sent. On the receiving side, if the synchronization patterns match, the same data as the bit data immediately before the received data is inserted at the position where the synchronization pattern was inserted, and some bits of the synchronization pattern are inverted. If so, the bit data immediately before the received data is inverted and inserted at the position where the corresponding sync pattern was inserted, whereby the bit data at the sync pattern insertion position is reproduced.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a multiplex conversion apparatus according to the present invention. FIG. 1A is a block diagram on the transmission side, and FIG. 1B is a block diagram on the reception side. FIG. 2 is a timing chart showing the operation of the multiplex conversion device of FIG.

The multiplexer of the present embodiment has a structure in which a transmitter distortion reduction circuit 1 is added to the transmitter side and a receiver distortion reduction circuit 11 is added to the receiver of the multiplexer described in the prior art. There is.

In FIG. 1A, a sampling circuit 2 on the transmitting side is a circuit for asynchronously sampling a plurality of input data signals DT with a sample clock SC having a higher frequency than the data signal. The multiplexing unit 3 is a circuit for time-division multiplexing a plurality of sampling signals SS sampled by the sampling circuit 2. The transmission-side synchronization pattern generation circuit 4 is a circuit for generating a synchronization pattern to be inserted on the transmission side, and the timing generation circuit 5 is a circuit for generating timing for inserting each bit constituting the synchronization pattern one bit at a time for each frame. It is. The synchronization pattern insertion selection circuit 6 inserts a synchronization pattern into the multiplexed signal TD under the control of the timing generation circuit 5.

Also, one of the plurality of sampling signals SS
The first is a sync pattern insertion signal FS in which a sync pattern is inserted. The synchronization pattern insertion signal FS includes a transmission side delay circuit 7 for generating data delayed by one bit from the synchronization pattern insertion signal FS, and a synchronization pattern insertion signal F
A change point detection circuit 8 for detecting a change point of data of the synchronization pattern insertion signal FS from S and the output of the transmission side delay circuit 7
A transmission-side inverter circuit 9 for inverting the output of the synchronization pattern generated by the transmission-side synchronization pattern generation circuit 4, and a synchronization pattern polarity selection circuit 10 for selecting the polarity of the synchronization pattern to be inserted at the synchronization pattern insertion position F. The transmission-side distortion reduction circuit 1 is connected.

In FIG. 1B, a reception-side synchronization pattern generation circuit 15 is a circuit for generating a synchronization pattern on the reception side, and generates the same pattern as that on the transmission side. The synchronization pattern detection circuit 14 includes a reception-side synchronization pattern generation circuit 15.
Is a circuit for detecting a synchronization pattern of the multiplexed signal TD from the synchronization pattern generated in the step (a), and a separation circuit 13 for separating the multiplexed signal TD into a plurality of reception data in synchronization with the detected synchronization pattern. Circuit. The decoding circuit 12 performs a process of reproducing a data signal from each of the separated received data.

The multiplexed signal TD is synchronized by comparing the output of the sync pattern inverter circuit 16 with the output of the sync pattern inverter circuit 16 and the multiplexed signal TD. A coincidence detection circuit 17 for detecting inverted bits in the pattern,
A separation control circuit 18 that passes a separation signal to the separation circuit 13 based on the output results of the synchronization pattern detection circuit 14 and the coincidence detection circuit 17, and one of the bit positions F where the synchronization pattern is inserted.
Receiving-side delay circuit 1 for detecting data signal before bit
9, a reception inverter circuit 20 for inverting the output of the reception delay circuit 19, and a data insertion selection circuit 2 for selecting the polarity of the insertion data by a control signal from the separation control circuit 18.
1 is connected to the reception side distortion reduction circuit 11, and the synchronization pattern insertion data FSZ in which the synchronization pattern is inserted is one of the plurality of reception data separated by the separation circuit 13. It is input to the decoding circuit 12 via the reduction circuit 11. Then, a reproduction data signal DTZ is output from the output of the decoding circuit 12.

In such a configuration, as shown in FIG. 2, on the transmitting side, the data signal DT is applied to the sample clock S.
A plurality of sampling signals SS are obtained by C. In the synchronization pattern insertion signal FS into which the synchronization pattern is inserted among the plurality of sampling signals SS, the synchronization pattern is inserted by crushing the first bit of each frame.
This sync pattern is selected by the sync pattern polarity selection circuit 6 for each bit forming the sync pattern, based on the output result of the change point detection circuit 8 whether the sync pattern is inverted and inserted, or is inserted as it is. And then inserted. Here, if the synchronization pattern insertion position F does not match the change point detection position of the data signal, the synchronization pattern is inserted as it is. If the synchronization pattern insertion position F matches the change point detection position, the corresponding synchronization pattern is inserted. Bit data is inverted and inserted. Then, each sampling signal SS including the synchronization pattern insertion signal FS is time-division multiplexed,
The multiplexed signal TD is transmitted.

Next, on the receiving side, the received multiplexed signal TD is received.
Is separated into a plurality of reception data by the separation circuit 13, and the following processing is performed on the synchronization pattern insertion data FSZ in which the synchronization pattern is inserted.

First, when the receiving-side distortion detecting circuit 11 detects that each bit constituting the synchronizing pattern matches the synchronizing pattern generated by the receiving-side synchronizing pattern generating circuit 15, the synchronizing pattern insertion position F indicates a change in the data signal. It is determined that the position does not match the detection position of the point. That is, when the synchronization pattern insertion data FSZ shown in FIG. 2 is a, c, d, the control signal from the separation control circuit 18 causes the receiving side delay circuit 19 to operate.
The output (one bit before) is selected and inserted at the sync pattern insertion position F to reproduce the data signal.

On the other hand, when it is detected that some of the bits forming the sync pattern are inverted, the sync pattern insertion position F of the inverted bit is coincident with the change point detection position of the data signal DT. Judgment, output of the receiving side inverter circuit 20 (data obtained by inverting the data of one bit before)
At the synchronization pattern insertion position F. When it is determined that a part of the synchronization pattern is inverted,
That is, when the sync pattern insertion data FSZ shown in FIG. 2 is b, the data signal is reproduced by inserting the inverted data of the previous bit data at the sync pattern insertion position F.

In this way, the fact that the change point of the data signal cannot be recognized on the receiving side due to the insertion of the synchronization pattern is resolved, so that the bit data at the position where the synchronization pattern was inserted is correctly reproduced. be able to.

As described above, the multiplex conversion apparatus of the present invention reproduces a synchronization pattern provided by crushing specific bits in each frame to separate multiplexed signals into original data. It is possible to reduce the error of the reproduced data signal caused by the insertion,
The reliability of the reproduced data is improved.

On the receiving side that receives a multiplexed signal, a partially inverted synchronization pattern is detected. However, when synchronization is established, even if one synchronization pattern mismatch (polarity inversion) is detected, the number of times of mismatch detection is constant. As long as the value does not exceed the value (the number of protection stages), it is not determined that the state is out of synchronization. At this time, if the cycle of the data signal and the sync pattern insertion cycle do not match, the sync pattern insertion position and the detection position of the change point of the data signal do not match, so that the inverted sync pattern does not continue. Therefore, a problem such as loss of synchronization due to inversion of a part of the synchronization pattern does not occur.

[0026]

Since the present invention is constructed as described above, it has the following effects.

On the transmitting side, when the detected position of the data signal change point coincides with the synchronization pattern insertion position, the data of the corresponding bit in the synchronization pattern is inverted and inserted, and the detection position of the data signal change point is detected. If the synchronization pattern insertion position does not match the synchronization pattern insertion position, the data of the corresponding bit is inserted according to the synchronization pattern as it is, and the detection position of the change point of the data signal and the synchronization pattern insertion position match or match. Can send information on whether there is any.

At this time, if the synchronization patterns match on the receiving side, the same bit data as the immediately preceding bit data of the received data is inserted at the position where the synchronization pattern was inserted, and some bits of the synchronization pattern are inserted. Is inverted, the bit data immediately before the received data is inverted and inserted at the sync pattern insertion position, whereby the bit data at the position where the sync pattern was inserted is reproduced. Therefore, the error of the reproduced data signal caused by inserting the synchronization pattern can be reduced, and the reliability of the reproduced data is improved because there is no signal quality deterioration.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a multiplex conversion device of the present invention;
FIG. 2A is a block diagram on the transmitting side, and FIG. 2B is a block diagram on the receiving side.

FIG. 2 is a timing chart showing the operation of the multiplex conversion device of FIG.

3A and 3B are diagrams showing a configuration of a conventional multiplex conversion apparatus, wherein FIG. 3A is a block diagram on a transmission side, and FIG. 3B is a block diagram on a reception side.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transmission-side distortion reduction circuit 2 Sampling circuit 3 Multiplexer 4 Transmission-side synchronization pattern generation circuit 5 Timing generation circuit 6 Synchronization pattern insertion selection circuit 7 Transmission-side delay circuit 8 Change point detection circuit 9 Transmission-side inverter circuit 10 Synchronization pattern polarity selection Circuit 11 Receiving-side distortion reduction circuit 12 Decoding circuit 13 Separating circuit 14 Synchronous pattern detecting circuit 15 Receiving-side synchronous pattern generating circuit 16 Synchronous pattern inverter circuit 17 Match detecting circuit 18 Separation control circuit 19 Receiving-side delay circuit 20 Receiving-side inverter circuit 21 Data insertion selection circuit DT data signal SC sample clock SS sampling signal FS synchronization pattern insertion signal TD multiplexed signal FSZ synchronization pattern insertion data DTZ playback data signal

Claims (2)

[Claims] 1. A transmission unit for asynchronously sampling a plurality of data signals, inserting a synchronization pattern for identifying each frame to generate a multiplexed signal, and detecting the synchronization pattern from the received multiplexed signal. In the multiplex conversion device including a reception unit that separates the received data into a plurality of received data and reproduces each data signal, the transmission unit includes a detection position of a change point of the data signal and an insertion position of the synchronization pattern. Has a transmitting side distortion reduction circuit that inverts and inserts the synchronization pattern when the values match and when the detection position of the change point of the data signal does not match the insertion position of the synchronization pattern, inserts the synchronization pattern as it is. In the receiving unit, the synchronization pattern inserted in the reception data matches the same synchronization pattern as the transmitting unit generated in the receiving unit. When the sync pattern is inserted, the same bit data as the previous bit data is inserted, and when a part of the sync pattern is inverted, one bit is inserted at the position where the sync pattern was inserted. A multiplex converter having a receiving side distortion reduction circuit for inserting data in which the previous bit data is inverted. 2. The multiplex conversion apparatus according to claim 1, wherein the transmission-side distortion reduction circuit delays the asynchronously sampled data signal by 1 bit, an output signal of the transmission-side delay circuit, and the output signal of the transmission-side delay circuit. A change point detection circuit that detects a change point of the data signal by comparing with a data signal that has been asynchronously sampled, a transmission side inverter circuit that inverts the synchronization pattern, and an output of the change point detection circuit, A sync pattern polarity selection circuit that selects either the output of the pattern or the output of the transmission side inverter circuit, and the reception side distortion reduction circuit is a sync pattern inverter circuit that generates an inverted signal of the sync pattern; Detect the inverted bit in the sync pattern from the output of the pattern inverter circuit and the multiplexed signal A coincidence detection circuit, a demultiplexing control circuit that generates a timing for demultiplexing a multiplexed signal into a plurality of received data based on the detection result of the synchronization pattern and the output of the coincidence detection circuit, and The receiving side delay circuit that detects the previous bit data, the receiving side inverter circuit that inverts the output of the receiving side delay circuit, and the output of the receiving side delay circuit or the receiving side by the output of the separation control circuit. A multiplex conversion device comprising: a data insertion selection circuit for inserting any one of the outputs of the inverter circuit at a position where a synchronization pattern was inserted.