JPH06216893A - Serial data transmission circuit - Google Patents

Abstract

PURPOSE:To send data accurately even when a delay or the like takes place by giving information for a transmission delay to a common phase signal and a common clock signal and informing the result on a receiver side, allowing the receiver side to reproduce parallel data from the signals and giving retiming to the parallel data. CONSTITUTION:A clock supply circuit section 3 generates a common phase signal 4 and a common clock 5 and supplies them to a transmission circuit section 1 and a reception circuit section 2. The transmission circuit section 1 uses a frequency divider circuit 11 to perform 1/N frequency division to the common clock 5 based on the common phase signal 4 and a processing circuit 6 processes the low speed data signal in N-parallel by using a 1/N clock as a timing signal. Furthermore, a parallel serial conversion circuit 8 applies N:1 parallel serial conversion to N-sets of low speed parallel data signal based on the common clock, and the transmission circuit section 1 sends data to the reception circuit section 2 based on the common phase signal and the common clock signal. The reception circuit section 2 reproduces the parallel data based on the sent phase signal and clock signal and conduct retiming the parallel data by using 1/N clock being an output of a frequency divider circuit 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high speed digital data transmission.

[0002]

2. Description of the Related Art Conventionally, in order to correctly match the phase of transmitted data, the data is reproduced with a slight shift in timing, and the phase on the timing side on the side of correct reproduction is selected to be correct. FIG. 16 shows, for example, JP-A-3-48.
545 is a serial data transmission circuit to which the in-device serial data reception circuit shown in 545 is applied. In the figure, 1 is a transmission circuit unit, 2 is a reception circuit unit, 3 is a clock supply circuit unit, and 5 is a common clock generated by 3. 6 is a processing circuit, 7 is N parallel low-speed data signal lines, 8 is 7 to N to 1
A parallel-serial conversion circuit for performing parallel-serial conversion, 10 is a common clock line supplied from 3, 11 is a reference of 9 and 10 is 1
/ N is a frequency dividing circuit, 12 is a 1 / N clock line divided by 1 / N by 11, and 13 is a data signal line transmitted from 1 to 2. Reference numeral 16 is a serial-parallel conversion circuit for converting the received data signal into 1-to-N serial-parallel conversion, 17 is an N-parallel low-speed data signal line subjected to 1-to-N serial-parallel conversion in 16, and 19 is a common clock line supplied from 3. Reference numeral 46 is a 1 / N clock line synchronized with the low speed data signal output from 16, reference numeral 52 is a serial data receiving circuit in the apparatus, and reference numeral 53 is a data line for carrying data retimed by the serial data receiving circuit.

Next, the operation will be described. The clock supply circuit unit 3 generates a common clock and supplies it from the line 5 to the transmission circuit unit 1 and the reception circuit unit 2. In the transmission circuit unit 1, the common clock supplied from the clock supply circuit unit 1
The dividing circuit 11 for dividing / N divides by 1 / N. In the processing circuit 6, 1 / N divided by 1 / N in the frequency dividing circuit 11
Using the clock as a timing signal, N parallel low speed data signals are processed. Further, the parallel-serial conversion circuit 8 is
The N parallel low-speed data signals processed by the processing circuit 6 are subjected to N to 1 parallel serial conversion. In this way, the transmission circuit unit 1
Common clock line 1 supplied from the clock supply circuit unit 3
A data signal transmitted from the transmission circuit unit 1 to the reception circuit unit 2 is generated with reference to the clock of 0, and is transmitted to the reception circuit unit 2 via the line 13.

The receiving circuit section 2 receives the signal on the data signal line 13 transmitted from the transmitting circuit section 1 to the receiving circuit section 2. At this time, the in-apparatus serial data receiving circuit 52 retimed the received data signal with the positive-phase clock of the common clock supplied from the clock supply circuit section 3 and with the negative-phase clock. Automatically select data in any safe phase of the data. The serial-parallel conversion circuit 16 performs a 1-to-N serial-parallel conversion on the data 53 retimed by the in-device serial data receiving circuit 52 to generate an N-parallel low-speed data signal and a 1 / N clock synchronized therewith.

[0005]

Since the conventional serial data transmission circuit is constructed as described above, a circuit which operates at high speed is required, and the delay variation / fluctuation of the clock distribution system and the data transmission system is 1 Beyond the clock,
There is a problem that the selected clock of the retimed data changes between the positive phase and the negative phase, and the data cannot be transmitted normally.

The present invention has been made to solve the above problems. Even if the delay variation / fluctuation of the clock distribution system and the data transmission system is 1 clock or more, but within N clocks, a simple circuit is used. The purpose is to transmit data to.

[0007]

In the serial data transmission apparatus according to the present invention, first, a serial-to-serial conversion circuit for generating serial data from a common phase signal and a common clock is provided on the transmission side, and the serial data, phase signal, Send the clock separately. At the receiving side, a serial-parallel conversion circuit that reproduces the received parallel data by using a common phase signal including a delay on the transmitting side that is sent separately from the data and the clock, and 1 / from the common phase signal and the clock The frequency division circuit that divides the frequency by N and the parallel data of the output of the serial-parallel conversion circuit is converted into 1
A parallel data is obtained by providing a reception retiming circuit for retiming with / N clock. In the serial data transmission device according to the second aspect of the present invention, the transmission side is provided with the parallel-serial conversion circuit that generates serial data from the common clock, and separately transmits the serial data including the phase signal and the clock. On the receiving side, a phase synchronization flag detection circuit that detects the common phase signal sent in the data and generates the phase signal, a common clock including the delay on the sending side sent separately from the data, and the above A serial-parallel conversion circuit that reproduces the parallel data received using the detected phase signal, a frequency dividing circuit that performs 1 / N frequency division from a common phase signal and a clock, and parallel data output from the serial-parallel conversion circuit, The reception retiming circuit for retiming with 1 / N clock of the frequency divider circuit is provided to obtain parallel data. A serial data transmission device according to claim 3 of the present invention includes a phase synchronization flag detection circuit that detects a common phase signal sent from the transmission side to the reception side in the data and generates the phase signal, and the transmission side. , A timing detection circuit for detecting a common clock transmitted in the data from the data, a serial-parallel conversion circuit for reproducing parallel data received by using the detected phase signal and the detected clock, and a common phase Parallel data is provided with a frequency dividing circuit for dividing the signal and the clock by 1 / N and a reception retiming circuit for retiming the parallel data output from the serial-parallel conversion circuit with 1 / N clock of the frequency dividing circuit output. To get.

[0008]

The serial data transmission circuit according to the present invention is
In the transmission circuit, serial data is generated from the common phase signal and the clock, and transmitted including the delay of the transmission circuit and the transmission path. In the receiving circuit, the parallel data is reproduced from the phase signal and the clock transmitted from the transmitting side, and the parallel data is further converted by the common phase signal received from the common clock supply unit and the 1 / N clock divided from the clock. Retimed. Even if delays and fluctuations occur in the transmitter circuit and the transmitter circuit, parallel data can be obtained by correctly retiming within the N clocks of the common clock.

[0009]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of this embodiment. In the figure, a transmitter circuit unit 1, a receiver circuit unit 2, a clock supply circuit unit 3, a common phase signal line 4, a common clock line 5, a processing circuit 6, a low-speed data signal line 7, a parallel-serial conversion circuit 8, a common phase signal line. 9, common clock line 10, frequency dividing circuit 11, 1 /
The N clock line 12, the data signal line 13, the serial-parallel conversion circuit 16 for performing serial-parallel conversion to N, and the low-speed data signal line 17 are the same as the conventional ones. As a novel part, 14 is a phase signal line transmitted from the transmission circuit unit 1 to the reception circuit unit 2, 15 is a clock line transmitted from the transmission circuit unit 1 to the reception circuit unit 2, and 18 is a clock supply line. The common phase clock line supplied from the circuit unit 3 and the common phase clock line 19 supplied from the clock supply circuit unit 3. Reference numeral 20 is a frequency dividing circuit that divides the clock by 1 / N with the common phase as a reference.
Reference numeral 21 denotes a clock line on which the 1 / N clock divided by 1 / N is applied by the frequency dividing circuit 20, and 22 is a reconfigurable circuit composed of a simple circuit such as a flip-flop for retiming the low speed data signal at the 1 / N clock. It is a timing circuit.

FIG. 2 is a waveform chart for explaining the operation of the serial data transmission circuit of FIG. In the figure, 23 is a common phase signal output from the clock supply circuit unit 2, 2
Reference numeral 4 denotes a common clock output from the clock supply circuit unit 3, 25 denotes a common phase signal input to the transmission circuit unit 1, 2
Reference numeral 6 is a common clock input to the transmission circuit unit 1. Two
Reference numeral 7 is a data signal output from the transmission circuit unit 1, 28 is a phase signal output from the transmission circuit unit 1, and 29 is a clock output from the transmission circuit unit 1. 30 is the receiving circuit unit 2
Is a phase signal input to the receiving circuit unit 2, and 32 is a clock input to the receiving circuit unit 2. Reference numeral 33 is a data signal N parallelized by the serial-parallel conversion circuit of the receiving circuit unit 2, 34 is a common phase signal input to the receiving circuit unit 2, 35 is a common clock input to the receiving circuit unit 2, and 36 is a receiving signal. It is a 1 / N clock divided by 1 / N in the circuit unit 2. Further, 37 is a delay in transmitting a signal from the clock supply circuit section 33 to the transmission circuit section 1,
38 is a delay in transmitting a signal in the transmission circuit unit 1, 3
Reference numeral 9 is a delay in transmitting a signal from the transmission circuit unit 1 to the reception circuit unit 2, 40 is a delay in transmitting N parallelized data in the reception circuit unit 2, and 41 is a clock from the clock supply circuit unit 3. A delay in transmitting a signal to the receiving circuit unit 2, 42
Is a delay when transmitting the 1 / N clock divided by 1 / N in the receiving circuit unit 2.

Next, the operation and signals between components will be described with reference to FIG. The clock supply circuit unit 3 generates the common phase signal 4 and the common clock 5 and supplies them to the transmission circuit unit 1 and the reception circuit unit 2. The transmission circuit section 1 divides the clock of the common clock line 10 supplied from the clock supply circuit section 3 by 1 / N with the signal on the common phase signal line 9 as a reference, and divides it by 1 / N. Go around. The processing circuit 6 is 1 /
Using N clocks as timing signals, N parallel low speed data signals are processed. In addition, the parallel-serial conversion circuit 8
Converts the N parallel low-speed data signals processed in the processing circuit 6 into N to 1 parallel-serial conversion with reference to the common phase signal and the common clock. The transmitter circuit unit 1 puts signals on the data signal line 13, the phase signal line 14, and the clock line 15, which are transmitted from the transmitter circuit unit 1 to the receiver circuit unit 2 on the basis of the common phase signal and the common clock, and receives them. It is transmitted to the circuit unit 2. The reception circuit unit 2 includes a data signal line 13, a phase signal line 14, which are transmitted from the transmission circuit unit 1 to the reception circuit unit 2.
Each signal on the clock line 15 is received. Serial-parallel conversion circuit 1
Reference numeral 6 performs 1-to-N serial-parallel conversion from the received data signal with reference to the phase signal and the clock to generate an N-parallel low-speed data signal. Further, the frequency dividing circuit 20 divides the clock of the common clock line 18 by 1 / N based on the signal of the common phase signal line 19 to generate a clock on the 1 / N clock line 21. The retiming circuit retimes the N parallel low-speed data signals generated by the serial-parallel conversion circuit 16 with the 1 / N clock generated by the frequency dividing circuit 20.

Further, the operation of each part will be described with reference to the waveform diagram of FIG. In the example of FIG. 2, the common phase signal is N ×
It shall be issued every M clocks. The common phase signal 23 on the phase signal line 4 output from the clock supply circuit 3
Then, the common clock 24 on the common clock line 5 is transmitted from the clock supply circuit unit 3 to the transmission circuit unit 1. The common phase signal 25 on the common phase signal line 9 and the common clock 26 on the common phase signal line 10 input to the transmission circuit unit 1 are transmitted from the clock supply circuit unit 3 to the transmission circuit unit 1,
For example, it is delayed by delay 1. The delay at that time is the delay 37 when the signal is transmitted from the clock supply circuit unit 3 to the transmission circuit unit 1. The transmission circuit unit 1 generates data with the input common phase signal 25 and common clock 26 as a reference. The data signal 27, the phase signal 28, and the clock 29 output from the transmission circuit unit 1 are delayed by the delay 2 due to the transmission of the signal within the transmission circuit unit 1 and the passage of the element. The delay at that time is the delay 38 when the signal is transmitted in the transmission circuit unit 1.

Data signal 3 input to the receiving circuit section 2
The 0, the phase signal 31, and the clock 32 are delayed by the delay 3 with the transmission on the data line 13, the phase signal line 14, and the clock line 15 from the transmission circuit unit 1 to the reception circuit unit 2. The delay at that time is the delay 39 when the signal is transmitted from the transmission circuit unit 1 to the reception circuit unit 2. In the receiving circuit unit 2,
The data signal 30 input to the receiving circuit unit 2 becomes a data signal 33 that is N-parallelized by the serial-parallel conversion circuit 16 of the receiving circuit unit 2 with the input phase signal 31 and clock 32 as a reference. The transmission of the signal in the section 2 and the passage of the element are delayed by the delay 4. The delay at that time is the delay 4 when the signal is transmitted in the receiving circuit unit 2.
It is 0. The common phase signal 23 and the common clock 24 output from the clock supply circuit unit 3 are transmitted from the clock supply circuit unit 3 to the reception circuit unit 2. The common phase signal 34 and the common clock 35 input to the receiving circuit unit 2 are delayed by a delay of 5 due to transmission from the clock supply circuit unit 3 to the receiving circuit unit 2.
Only delayed. The delay at that time is the clock supply circuit unit 3
A delay 41 when a signal is transmitted from the receiver to the receiving circuit unit 2. In the receiving circuit unit 2, the input common phase signal 3
With reference to 4, the input common clock 35 is 1 /
1 / N clock 36 divided by 1 / N by the N divider circuit 36
Is delayed by a delay 6 due to the transmission of signals in the reception circuit unit 2 and the passage of elements. The delay in that case is the receiving circuit unit 2
This is a delay 42 when transmitting a 1 / N clock divided by 1 / N.

The signal delay is (delay 1 + delay 2 + delay 3)
+ Delay 4-delay 5-delay 6), and retiming can be performed if the total variation / fluctuation is within N clocks. That is, even if the retiming circuit 22 is composed of a simple circuit such as a flip-flop, the serial-parallel conversion circuit 1
The data signal 33 N parallelized by 6 can be retimed by the 1 / N clock 36 divided by 1 / N, and is not affected by delay variations and fluctuations. As shown in FIG. 2, there is a margin N times that of one clock.

Example 2. Next, an example in which the present invention is applied when there are a plurality of transmission circuits will be described. FIG. 3 is a block diagram of the embodiment. Signals between operations and configurations will be described with reference to FIG. In FIG. 3, one transmission circuit section 1 a of the transmission circuit section that is redundantly configured in a double manner is provided with the clock supply circuit section 3.
From the transmission circuit unit 1a to the reception circuit unit 2 on the basis of the common phase signal and the common clock supplied from the data signal line 1
3a, the phase signal line 14a, and the clock line 15a are loaded with signals and transmitted to the receiving circuit unit 2. The other transmission circuit unit 1
b is a data signal line 13b, a phase signal line 14b, and a phase signal line 14b from the transmission circuit unit 1b to the reception circuit unit 2 with reference to the common phase signal and the common clock supplied from the clock supply circuit unit 3.
A signal is placed on the clock line 15b and transmitted to the receiving circuit unit 2. The reception circuit unit 2 receives a data signal, a phase signal, and a clock from one transmission circuit unit 1a of the transmission circuit unit that is doubly redundant. The serial-parallel conversion circuit 16a uses the received data on the data signal line 13a in a 1: N ratio based on the phase of the phase signal line 14a and the clock of the clock line 15a.
Serial-parallel conversion is performed to generate N parallel low-speed data signals, which are output to the signal line 17a. Also, it receives a data signal, a phase signal, and a clock from the other transmission circuit unit 1b. The serial-parallel conversion circuit 16b performs a 1: N serial-parallel conversion of the received data on the data signal line 13b based on the phase of the phase signal line 14b and the clock of the clock line 15b to generate an N-parallel low-speed data signal. And outputs to the signal line 17b. The selection circuit 43 selects one of the data on the N parallel low-speed data signal lines 17a and 17b from the transmission circuit section which is doubly redundant, and is generated by the frequency dividing circuit 20 in the retiming circuit. Further, since the retiming is performed with the 1 / N clock, it is possible to switch between the two signals from the transmission circuit section which is doubly redundantly configured without any interruption.

Further, the timing-based operation will be described with reference to FIGS. 4 and 5. The common phase signal 23 and the common clock 24 in the clock supply circuit unit 3 are transmitted from the clock supply circuit unit 3 to the transmission circuit units 1a and 2a which are doubly redundantly configured. The common phase signal 25a and the common clock 26a input to the transmission circuit unit 1a are supplied to the clock supply circuit unit 3
From the transmission circuit unit 1a to the transmission circuit unit 1a is delayed by the delay 1a. The delay at that time is the delay 37a when the signal is transmitted from the clock supply circuit unit 3 to the transmission circuit unit 1a. The transmission circuit unit 1a generates data based on the input common phase signal 25a and common clock 26a. The data signal 27a and the phase signal 2 output from the transmission circuit unit 1a
8a and the clock 29a are delayed by a delay 2a due to transmission of a signal in the transmission circuit unit 1a and passage of an element. The delay at that time is the delay 38a when the signal is transmitted in the transmission circuit unit 1a. The data signal 30a, the phase signal 31a, and the clock 32a input to the receiving circuit unit 2 are delayed by the delay 3a as they are transmitted from the transmitting circuit unit 1a to the receiving circuit unit 2. The delay at that time is the delay 39a when the signal is transmitted from the transmission circuit unit 1a to the reception circuit unit 2. In the receiving circuit unit 2, the data signal 30a input to the receiving circuit unit 2 is the input phase signal 31a and clock 32.
With reference to a, the serial-parallel conversion circuit 16a of the receiving circuit unit 2
As a result, the data signal 33a is N-parallelized, and is further delayed by the delay 4a due to the transmission of the signal in the receiving circuit unit 2 and the passage of the element. The delay at that time is the delay 40a when the signal is transmitted in the receiving circuit unit 2.

Next, the signal from the other transmission circuit will be described with reference to FIG. The common phase signal 25b and the common clock 26b input to the transmission circuit 1b are the clock supply circuit unit 3
From the transmission circuit unit 1b to the transmission circuit unit 1b is delayed by the delay 1b. The delay at that time is the delay 37b in FIG. The transmission circuit unit 1b generates data based on the input common phase signal 25b and common clock 26b. The data signal 27b and the phase signal 28 output from the transmission circuit unit 1b
b, the clock 29b is delayed by the delay 2b due to the transmission of the signal in the transmission circuit unit 1 and the passage of the element. The delay at that time is the delay 38b in FIG. The data signal 30b, the phase signal 31b, and the clock 32b input to the receiving circuit unit 2 are delayed by the delay 3b as they are transmitted from the transmitting circuit unit 1b to the receiving circuit unit 2. The delay at that time is the delay 39b in FIG. In the receiving circuit unit 2, the receiving circuit unit 2
The data signal 30b input to the above becomes a data signal 33b which is N-parallelized by the serial-parallel conversion circuit 16b of the receiving circuit unit 2 on the basis of the input phase signal 31b and clock 32b, and further in the receiving circuit unit 2. Signal transmission,
And the passage of the element causes a delay of 4b. The delay at that time is the delay 40b in FIG.

The common phase signal 23 and the common clock 24 output from the clock supply circuit section 3 are also transmitted from the clock supply circuit section 3 to the reception circuit section 2. The common phase signal 34 and the common clock 35 input to the receiving circuit unit 2 are delayed by the delay 5 with the transmission from the clock supply circuit unit 3 to the receiving circuit unit 2. The delay at that time is the delay 41 in FIG. The 1 / N clock 36, which is 1 / N-divided by the 1 / N frequency dividing circuit 20 in the receiving circuit unit 2, is delayed by a delay 6 by transmission of a signal in the receiving circuit unit 2 and passage of an element. The delay at that time is the delay 42 in FIG. 4 and 5A
The timing of the display represents the total delay. As described above, even when the transmission circuit unit is doubly redundantly configured, the delay of each signal is (delay 1a + delay 2a + delay 3a).
+ Delay 4a−delay 5−delay 6) and (delay 1b + delay 2b + delay 3b + delay 4b−delay 5−delay 6),
If this total variation / fluctuation is within N clocks,
After selecting a signal in the selection circuit 43, retiming can be performed. Even in the retiming circuit 22 composed of a simple circuit such as a flip-flop, the data signal 33 which is N-parallelized by the serial-parallel conversion circuit of the receiving circuit unit 2 is divided by 1 / N by the 1 / N clock 36. It can be retimed and is not affected by delay variations and fluctuations. Therefore,
It is possible to switch two signals from the transmission circuit section that is doubly redundantly configured without interruption.

Example 3. Another embodiment of the present invention will be described. FIG. 6 is a block diagram of the embodiment. Signals between operations and configurations will be described with reference to FIG. The gist of the present embodiment is that instead of generating the phase signal in the transmission circuit unit 1 of the first embodiment and transmitting it to the reception circuit unit 2, the transmission circuit unit 1 creates and transmits a phase synchronization flag. That is, the phase synchronization flag insertion circuit 44 inserts the phase synchronization flag in the data signal transmitted from the transmission circuit unit 1 to the reception circuit unit 2 and transmits the data signal.

In the receiving circuit section 2, the data on the data signal line 13 received by the serial-parallel conversion circuit 16 is transferred to the clock line 15.
Instead of the clock and the phase of the phase signal line 14, the 1: N serial / parallel conversion is performed with the phase synchronization flag detected by the phase synchronization flag detection circuit 45 as a reference. By generating the N parallel low-speed data signals 17, the same function as that of the first embodiment can be obtained.

The operation of this will be described with reference to the timing chart of FIG. The common phase signal 25 and the common clock 26 input to the transmission circuit unit 1 are the clock supply circuit unit 3
From the transmission circuit unit 1 to the transmission circuit unit 1 is delayed by delay 1.
The delay at that time is the delay 37 in FIG. Transmission circuit unit 1
Generates data based on the common phase signal 25 and the common clock 26. Then, the data signal 27 and the clock 29 output from the transmission circuit unit 1 are delayed by the delay 2 due to the transmission of the signal in the transmission circuit unit 1 and the passage of the element. The delay at that time is the delay 38 in FIG. The data signal 30 and the clock 32 input to the receiving circuit unit 2 are delayed by the delay 3 with the transmission from the transmitting circuit unit 1 to the receiving circuit unit 2. The delay at that time is the delay 39 in FIG. The data signal 30 input to the reception circuit unit 2 is subjected to serial-parallel conversion of the reception circuit unit 2 with reference to the phase signal 46 generated by the phase synchronization flag detection circuit 45 and the clock 32 input to the reception circuit unit 2. The data signal 33 is N-parallelized by the circuit 16. This data signal is delayed by the delay 4 due to the transmission of the signal within the receiving circuit unit 2 and the passage of the element. The delay at that time is the delay 40 in FIG. 7.

The common phase signal 23 and the common clock 24 output from the clock supply circuit section 3 are transmitted from the clock supply circuit section 3 to the reception circuit section 2 and the common phase signal 34,
It becomes the common clock 35. These signals are delayed by the delay 5 with the transmission from the clock supply circuit unit 3 to the reception circuit unit 2. The delay at that time is the delay 41 in FIG. 1 / N divided by the 1 / N divider 20 in the receiving circuit 2
The N clock 36 is delayed by a delay 6 in transmission of a signal in the reception circuit unit 2 and passage of an element. The delay at that time is the delay 42 in FIG. 7. The signal delay is (delay 1+
Delay 2 + delay 3 + delay 4−delay 5−delay 6), and if the total variation / fluctuation is within N clocks, retiming is possible. Even in the retiming circuit 22 composed of a simple circuit such as a flip-flop, the data signal 33 N-parallelized by the serial-parallel conversion circuit of the receiving circuit unit 2
Can be retimed with the 1 / N clock 36, and is not affected by delay variations and fluctuations.

Example 4. An example in which the circuit of the third embodiment is applied to a plurality of transmission circuits will be described. FIG. 8 is a block diagram of this embodiment. The operation and signals between the configurations will be described with reference to FIG. In the figure, a transmission circuit unit A having a dual redundant configuration
And B. One of the transmission circuit units 1a generates signals on the data signal line 13a and the clock line 15a to be transmitted based on the common phase signal and the common clock supplied from the clock supply circuit unit 3, and the reception circuit unit 2 receives the signals. Send.
Similarly, the transmission circuit unit 1b also generates signals on the data signal line 13b and the clock line 15b transmitted from the transmission circuit unit 1b to the reception circuit unit 2 and transmits the signals to the reception circuit unit 2. The receiving circuit unit 2 receives signals from the data signal line 13a and the clock 15a line from the one transmitting circuit unit 1a, and the serial / parallel conversion circuit 16a receives the phase synchronization flag detecting circuit 45.
1-to-N serial-parallel conversion is performed on the basis of the phase synchronization flag detected at a to generate a signal on the N-parallel low-speed data signal line 17a. Similarly, the data signal and the clock are received from the transmission circuit unit 1b, and the serial-parallel conversion circuit 16b performs 1-to-N serial-parallel conversion using the phase synchronization flag as a reference to generate an N-parallel low-speed data signal. The selection circuit 43 includes the N parallel low-speed data signal lines 17 from the transmission circuit section that are doubly redundant.
One of the signals a and 17b is selected and retiming is performed by the 1 / N clock generated by the frequency dividing circuit 20 in the retiming circuit. Signals can be switched without interruption.

The operation of this will be described with reference to the timing charts of FIGS. 9 and 10. The common phase signal 25a and the common clock 26a input to one of the transmission circuit units 1a are
The transmission from the clock supply circuit unit 3 to the transmission circuit unit 1a is delayed by the delay 1a. The delay at that time is the delay 37a in FIG. The transmission circuit unit 1a uses the common phase signal 25
a, data is generated based on the common clock 26a. The data signal 27a and the clock 29a output from the transmission circuit unit 1a are delayed by the delay 2a due to the transmission of the signal in the transmission circuit unit 1 and the passage of the element. The delay at that time is the delay 38a in FIG. The data signal 30a and the clock 32a input to the receiving circuit unit 2 are delayed by the delay 3a as they are transmitted from the transmitting circuit unit 1a to the receiving circuit unit 2. The delay at that time is the delay 39a in FIG. Receiver circuit section 2
The data signal 30a inputted to the data signal 33 is N parallelized by the serial / parallel conversion circuit 16a of the receiving circuit unit 2.
a. These signals are delayed by the delay 4a due to the transmission of signals in the receiving circuit unit 2 and the passage of the elements. The delay at that time is the delay 40a in FIG.

On the other hand, the common phase signal 25b and the common clock 26b input to the transmission circuit unit 1b are delayed by the delay 1b as they are transmitted from the clock supply circuit unit 3 to the transmission circuit unit 1b. The delay at that time is the delay 37b in FIG. The transmission circuit unit 1b generates data similarly to the transmission circuit unit 1a. At this time, the data signal 27b and the phase signal 28
b, the clock 29b is delayed by the delay 2b due to the transmission of the signal in the transmission circuit unit 1 and the passage of the element. The delay at that time is the delay 38b in FIG. Similarly, the data signal 30b and the clock 32b input to the receiving circuit unit 2 are delayed by the delay 3b along with the transmission. The delay in that case,
This is the delay 39b in FIG. The data signal 30b input to the receiving circuit unit 2 is the serial-parallel conversion circuit 1 of the receiving circuit unit 2.
The data signal 33b is N parallelized by 6b. These are delayed by the delay 4b due to the transmission of signals in the reception circuit unit 2 and the passage of elements. The delay at that time is the delay 40b in FIG.

The common phase signal 34 and the common clock 35 input from the clock supply circuit unit 3 to the reception circuit unit 2 are delayed by the transmission from the clock supply circuit unit 3 to the reception circuit unit 2 with a delay of 5.
Only delayed. The delay at that time is the delay 41 in FIG. The 1 / N clock 36, which is 1 / N-divided by the 1 / N frequency dividing circuit 20 in the receiving circuit unit 2, is delayed by a delay 6 by transmission of a signal in the receiving circuit unit 2 and passage of an element. The delay at that time is the delay 42 in FIG. The B display timings in FIGS. 9 and 10 represent the total delay. As described above, even when the transmission circuit unit is doubly redundantly configured, the delay of each signal is (delay 1a + delay 2a + delay 3a).
+ Delay 4a-delay 5-delay 6) and (delay 1b + delay 2)
b + delay 3b + delay 4b−delay 5−delay 6), and if the total variation / fluctuation is within N clocks, retiming can be performed even after the selection circuit 43 selects a signal. Even in the retiming circuit 22 configured by a simple circuit such as a flip-flop, the N-parallelized data signal 33
Can be retimed with the 1 / N clock 36, and is not affected by delay variations and fluctuations. Thus 2
It is possible to switch two signals from the redundantly configured transmission circuit section without interruption.

Example 5. The purpose of the present embodiment to be described below is to generate the clock in the transmission circuit unit 1 of the third embodiment and transmit the data on the data signal line 13 in the transmission circuit unit 2 instead of transmitting the clock to the reception circuit unit 2. Then, the clock is extracted by the timing extraction circuit 47, and thereafter, the same operation as that of the third embodiment is performed. FIG. 11 is a block diagram of this embodiment. A timing detection circuit 47 is added as a newer configuration than the third embodiment.

The operation will be described with reference to the timing chart of FIG. The common phase signal 25 input to the transmission circuit unit 1,
The common clock 26 is delayed by delay 1 with the transmission from the clock supply circuit unit 3 to the transmission circuit unit 1. The delay at that time is the delay 37 in FIG. The transmission circuit unit 1 generates data based on the common phase signal 25 and the common clock 26. The data signal 27 output from the transmission circuit unit 1 is
The transmission of the signal in the transmission circuit unit 1 and the passage of the element delay the signal by a delay 2. The delay at that time is the delay 38 in FIG.
Is. The data signal 30 and the clock 32 input to the receiving circuit unit 2 are delayed by the delay 3 with the transmission from the transmitting circuit unit 1 to the receiving circuit unit 2. The delay at that time is the delay 39 in FIG. The data signal 30 input to the receiving circuit unit 2 is based on the phase signal 46 generated by the phase synchronization flag detecting circuit 45 and the phase signal 48 generated by the timing extracting circuit 47, and is serial-parallel to the receiving circuit unit 2. The data signal 33 is N-parallelized by the conversion circuit 16. This data signal is delayed by the delay 4 due to the transmission of the signal within the receiving circuit unit 2 and the passage of the element. The delay at that time is the delay 40 in FIG.

The common phase signal 23 and the common clock 24 output from the clock supply circuit section 3 are transmitted from the clock supply circuit section 3 to the reception circuit section 2, and the common phase signal 34,
It becomes the common clock 35. At that time, a delay of 5 is delayed along with the transmission from the clock supply circuit unit 3 to the reception circuit unit 2. The delay at that time is the delay 41 in FIG. 1 / N divided by the 1 / N divider 20 in the receiving circuit 2
The N clock 36 is delayed by a delay 6 in transmission of a signal in the reception circuit unit 2 and passage of an element. The delay at that time is the delay 42 in FIG. The signal delay is (delay 1
+ Delay 2 + delay 3 + delay 4-delay 5-delay 6),
If this total variation / fluctuation is within N clocks,
Can be retimed. That is, even in the retiming circuit 22 composed of a simple circuit such as a flip-flop, the data signal 33 N parallelized by the serial / parallel conversion circuit of the receiving circuit unit 2 can be retimed by the 1 / N clock 36,
It is not affected by delay variations and fluctuations.

Example 6. An example in which the circuit of the fifth embodiment is applied to a plurality of transmission circuits will be described. Example 4 and Example 5
Can be thought of as a combination. A configuration diagram of an embodiment of the present invention is shown below in FIG. In the figure, clock lines 14a, 14 are provided in transmission circuit sections 1a, 1b that are redundantly configured in a dual manner.
Instead of generating the clock in b and transmitting it to the receiving circuit unit 2, the receiving circuit unit 2 uses the timing extracting circuit 47 to generate a clock from the data on the data signal lines 13a and 13b received from the transmitting circuit units 1a and 1b. After the extraction, the same operation as that of the fourth embodiment is performed.

Next, the operation will be described with reference to the timing charts of FIGS. The common phase signal 25a and the common clock 26a input to the transmission circuit unit 1a are delayed 1a due to transmission from the clock supply circuit unit 3 to the transmission circuit unit 1a.
Only delayed. In the transmission circuit unit 1a, the transmission circuit unit 1
common phase signal 25a and common clock 26 input to a
Data is generated based on a. The data signal 27a and the clock 29a output from the transmission circuit unit 1a are delayed by the delay 2a due to the transmission of the signal in the transmission circuit unit 1 and the passage of the element. Data signal 30 input to the receiving circuit unit 2
a and the clock 32a are delayed by the delay 3a with the transmission from the transmission circuit unit 1a to the reception circuit unit 2. Receiver circuit section 2
The data signal 30a input to the data is data parallelized by the serial-parallel conversion circuit 16a based on the phase signal 46a generated by the phase synchronization flag detection circuit 45a and the clock 48a extracted by the timing detection circuit 47. It becomes the signal 33a. At this time, the signal is transmitted in the receiving circuit unit 2 and the signal is passed through the element, so that the signal is delayed by the delay 4a.

On the other hand, the common phase signal 25b and the common clock 26b input to the transmission circuit unit 1b are delayed by the delay 1b with the transmission from the clock supply circuit unit 3 to the transmission circuit unit 1b. The transmission circuit unit 1b generates data similarly to the transmission circuit unit 1a. At this time, the data signal 27b and the phase signal 2
8b and the clock 29b are delayed by the delay 2b due to transmission in the transmission circuit unit 1 and passage of the element. Receiver circuit section 2
Similarly, the data signal 30b and the clock 32b input to (1) are delayed by the delay 3b as they are transmitted. The data signal 30b input to the receiving circuit unit 2 is the serial-parallel conversion circuit 16b.
Thus, the data signal 33b is N-parallelized. These are delayed by the delay 4b due to the transmission of signals in the reception circuit unit 2 and the passage of elements.

The common phase signal 34 and the common clock 35 input from the clock supply circuit unit 3 to the reception circuit unit 2 are delayed by the transmission of 5 from the clock supply circuit unit 3 to the reception circuit unit 2.
Only delayed. The clock 36 divided by 1 / N by the 1 / N divider circuit 20 is delayed by a delay 6 due to transmission of a signal within the reception circuit unit 2 and passage of an element. As described above, even when the transmission circuit unit is doubly redundantly configured, the delay of each signal is (delay 1a + delay 2a + delay 3a +).
Delay 4a−delay 5−delay 6) and (delay 1b + delay 2)
b + delay 3b + delay 4b−delay 5−delay 6), and if the total variation / fluctuation is within N clocks, retiming can be performed even after the selection circuit 43 selects a signal.

Example 7. In the above embodiment, the clock is 1 /
The example in which the frequency dividing circuit for dividing the frequency by N is provided in the receiving circuit has been described. Even if this frequency dividing circuit is provided not in the receiving circuit but in the clock common circuit section that generates a common clock with the common phase signal and then the 1 / N divided clock is sent to the receiving circuit, the same effect is obtained. can get.

Example 8. In the above-described embodiment, when N parallel data is serially converted and serial data is transmitted, a phase signal is output every N clock × M blocks. Alternatively, the phase signal may be output every N clocks.

[0036]

As described above, according to the present invention, the common phase signal and clock are transmitted to the receiving side by including the transmitting side and the transmission delay, and the receiving side parallelizes the phase signal and clock from the transmitting side. Since data is reproduced and frequency is divided using another common phase signal and clock for retiming, correct data can be reproduced even if there is a large difference in delay between the transmission / data transmission system and the clock distribution system. .

[Brief description of drawings]

FIG. 1 is a configuration diagram of a serial data transmission circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram of the serial data transmission circuit of FIG.

FIG. 3 is a configuration diagram of a serial data transmission circuit which is another embodiment of the present invention.

4 is a timing diagram of the serial data transmission circuit of FIG.

5 is a timing diagram of the serial data transmission circuit of FIG.

FIG. 6 is a configuration diagram of a serial data transmission circuit which is still another embodiment of the present invention.

7 is a timing diagram of the serial data transmission circuit of FIG.

FIG. 8 is a configuration diagram of a serial data transmission circuit which is still another embodiment of the present invention.

9 is a timing diagram of the serial data transmission circuit of FIG.

10 is a timing diagram of the serial data transmission circuit of FIG.

FIG. 11 is a configuration diagram of a serial data transmission circuit which is still another embodiment of the present invention.

12 is a timing diagram of the serial data transmission circuit of FIG.

FIG. 13 is a configuration diagram of a serial data transmission circuit which is still another embodiment of the present invention.

14 is a timing diagram of the serial data transmission circuit of FIG.

15 is a timing diagram of the serial data transmission circuit of FIG.

FIG. 16 is a configuration diagram of a conventional serial data transmission circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 transmission circuit section 2 reception circuit section 3 clock supply circuit section 8 parallel-serial conversion circuit 16, 16a, 16b serial-parallel conversion circuit 20 frequency dividing circuit 22 retiming circuit 43 selection circuit 44 phase synchronization flag insertion circuit 45, 45a, 45b phase Sync flag detection circuit 47, 47a, 47b Timing detection circuit

Claims (3)

[Claims] 1. A serial-parallel conversion circuit for reproducing parallel data received by using a common phase signal including a delay on the transmission side and a clock transmitted separately from the data on the transmission side, and a common phase signal. A serial data transmission circuit including a frequency dividing circuit for dividing the clock by 1 / N and a reception retiming circuit for retiming the parallel data output from the serial-parallel conversion circuit with 1 / N clock of the frequency dividing circuit output. . 2. A phase synchronization flag detection circuit for generating a phase signal by detecting a common phase signal included in data sent from the transmitting side, and a delay on the transmitting side sent separately from the data. Serial-parallel conversion circuit that reproduces parallel data received using a common clock and the detected phase signal, a frequency dividing circuit that divides the common phase signal and clock by 1 / N, and the serial-parallel conversion circuit output Serial data transmission circuit provided with a reception retiming circuit for retiming the parallel data of 1) with the 1 / N clock of the frequency divider circuit output. 3. A phase synchronization flag detection circuit for detecting a common phase signal sent from the transmitting side in the data and generating the phase signal, and a common clock sent from the sending side to be included in the data. , A serial-parallel conversion circuit that reproduces parallel data received using the detected phase signal and the detected clock, and a 1 / N frequency division component from the common phase signal and clock. A serial data transmission circuit comprising a frequency divider circuit and a reception retiming circuit for retiming parallel data output from the serial-parallel conversion circuit with 1 / N clock of the frequency divider circuit output.