JP2654609B2 - Multiplex converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex conversion apparatus for asynchronously sampling a plurality of data signals and taking them into the apparatus for multiplexing.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing the configuration of a conventional multiplex conversion apparatus, wherein FIG. 3A is a block diagram on the transmission side, and FIG. 3B is a block diagram on the reception side.

In FIG. 3A, a plurality of sampling circuits 102 provided on the transmission side are circuits for asynchronously sampling a plurality of input data signals with a sample clock having a higher frequency than the data signals. The multiplexing unit 103 is a circuit for time-division multiplexing a plurality of sampling signals sampled by the sampling circuit 102. Transmission side synchronization pattern generation circuit 10
Reference numeral 4 denotes a circuit for generating a synchronization pattern to be inserted on the transmission side, and the timing generation circuit 105 is a circuit for generating timing for inserting each bit constituting the synchronization pattern one bit at a time for each frame. The synchronization pattern insertion selection circuit 106 is a circuit for inserting a synchronization pattern into the multiplexed signal under the control of the timing generation circuit 105.

In FIG. 3B, a receiving-side synchronization pattern generating circuit 115 is a circuit that generates a synchronization pattern on the receiving side, and generates the same pattern as that on the transmitting side. The synchronization pattern detection circuit 114 is a circuit for detecting the synchronization pattern of the multiplexed signal from the synchronization pattern generated by the reception-side synchronization pattern generation circuit 115, and the separation circuit 113 synchronizes with the detected synchronization pattern and performs multiplexing. This is a circuit for separating a signal into a plurality of received data. The decoding circuit 112 performs a process of reproducing a data signal from each of the separated received data.

In the above configuration, for example, when there are nine data signals on the transmitting side and each data signal is sampled in 8-bit units, each sampling signal sampled by the sampling circuit 102 is Is a time-division multiplexed signal with 72 bits as one frame. Subsequently, the transmission-side synchronization pattern generation circuit 10
4, the timing generation circuit 105 and the synchronization pattern insertion selection circuit 106 crush the first bit (frame bit) in each frame and insert a synchronization pattern.
The synchronization pattern is composed of, for example, 12 frames, that is, an arbitrary bit string of 12 bits. The receiving side detects the repetition of the arbitrary bit string and recognizes the synchronization pattern.

Next, on the receiving side, the input multiplexed signal is detected in synchronization pattern by the receiving side synchronization pattern generation circuit 115, the synchronization pattern detection circuit 114, and the sample clock sent from the transmission side, and the synchronization pattern is detected. The data is separated into nine pieces of received data by the separation circuit 113 in synchronization with. Each of the separated received data is reproduced by the decoding circuit 112 into a data signal.

[0007]

However, in the above-described conventional multiplex conversion apparatus, one of the plurality of reception data separated by the separation circuit on the receiving side is output with the synchronization pattern other than the data inserted. It had been. Therefore, in the terminal receiving this data signal, it becomes impossible to correctly recognize the change point of the data signal, especially when the change point of the data signal matches the insertion position of the synchronization pattern.
There has been a problem that an error due to sampling is increased to cause jitter and the like, and the quality of a transmitted signal is degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and it is intended to prevent an error in a reproduced data signal caused by insertion of a synchronization pattern, thereby improving signal quality. It is an object of the present invention to provide a multiplex conversion device without deterioration.

[0009]

In order to achieve the above object, a multiplex conversion device according to the present invention comprises an asynchronous support for a plurality of data signals .
A transmitting unit that performs sampling, inserts a synchronization pattern for identifying each frame, and generates a multiplexed signal, and detects a synchronization pattern from the received multiplexed signal and separates the synchronization pattern into a plurality of received data. in multiplex conversion unit constituted by a receiving section for reproducing the signal, and the transmission unit, when the detected position of the change point of the data signal and the insertion position of the synchronization pattern matches inverts the synchronization pattern inserting, when the detected position of the change point of the data signal and the insertion position of the synchronization pattern does not match the previous
Serial have as a sender distortion reducing circuit for inserting a synchronization pattern, the receiving unit is generated by the receiving portion and the
For the same synchronization pattern as the transmitting unit,
When inserted synchronization pattern matches, the position where the sync pattern has been inserted, the synchronizing pattern inserted
The same data as the bit data immediately before the position of the received data that has been inserted is inserted, and the transmission generated by the reception unit is performed.
Inserted into the received data for the same synchronization pattern as the
When some bits of the synchronized pattern are inverted
At the position where the inverted bit was inserted ,
Characterized by having a reception-side distortion reduction circuit for inserting the inverted data of the bit data immediately before the said position of the received data pattern has been inserted.

At this time, the transmission side distortion reduction circuit compares the output signal of the transmission side delay circuit with the data signal subjected to the asynchronous sampling by delaying the asynchronously sampled data signal by one bit. A change point detection circuit that detects a change point of the data signal, a transmission-side inverter circuit that inverts a synchronization pattern generated by a transmission unit, and a detection result of the change point detection circuit, Synchronous pattern or the transmitting inverter circuit
In anda sync pattern polarity selection circuit for selecting one of the synchronization is inverted pattern, the receiving distortion reduction circuit includes a synchronization pattern inverter circuit for inverting the synchronization pattern generated by the receiving unit, the synchronization pattern Compare the output of the inverter circuit with the multiplexed signal and insert it into the received data
A coincidence detection circuit for detecting an inverted bit of the synchronization pattern in which the detection result of the inserted synchronization pattern in the received data, and the detection result of said coincidence detection circuit, before
Separation for separating the serial multiplexed signal into a plurality of received data
The separation control circuit that generates the signal and the synchronization pattern
Which do in the received data, the reception side delay circuit for detecting an immediately preceding bit data of the position where the sync pattern has been inserted, was detected at the receiving delay circuit Bittode
A receiving-side inverter circuit for inverting the over data, by the control signal output from the separation control circuit, one of bit data obtained by inverting a bit data or the receiving side inverter circuit, detected by the receiving delay circuit one
Write and a data insertion selection circuit to be inserted to a position where the sync pattern has been inserted, may have.

[0011]

The multiplex conversion apparatus configured as described above, on the transmitting side, inverts the data of the corresponding bit in the synchronization pattern when the detection position of the change point of the data signal coincides with the synchronization pattern insertion position. If the detected position of the change point of the data signal does not coincide with the insertion position of the synchronization pattern, the data of the corresponding bit is inserted according to the synchronization pattern as it is to synchronize with the detection position of the change point of the data signal. Information on whether the pattern insertion position matches or does not match is sent. On the receiving side, if the synchronization pattern matches, the same data as the bit data immediately before the received data is inserted at the position where the synchronization pattern was inserted, and some bits of the synchronization pattern are inverted. In this case, the bit data at the synchronization pattern insertion position is reproduced by inverting the bit data immediately before the received data and inserting it at the position where the corresponding synchronization pattern was inserted.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a multiplex conversion apparatus according to the present invention. FIG. 1A is a block diagram on the transmission side, and FIG. 1B is a block diagram on the reception side. FIG. 2 is a timing chart showing the operation of the multiplex conversion device of FIG.

The multiplex conversion apparatus of this embodiment has a configuration in which a transmission-side distortion reduction circuit 1 is added to the transmission side of the multiplex conversion apparatus described in the conventional example, and a reception-side distortion reduction circuit 11 is added to the reception side. I have.

In FIG. 1A, a sampling circuit 2 on the transmitting side is a circuit for asynchronously sampling a plurality of input data signals DT with a sample clock SC having a higher frequency than the data signal. The multiplexing unit 3 is a circuit for time-division multiplexing a plurality of sampling signals SS sampled by the sampling circuit 2. The transmission-side synchronization pattern generation circuit 4 is a circuit for generating a synchronization pattern to be inserted on the transmission side, and the timing generation circuit 5 is a circuit for generating timing for inserting each bit constituting the synchronization pattern one bit at a time for each frame. It is. The synchronization pattern insertion selection circuit 6 inserts a synchronization pattern into the multiplexed signal TD under the control of the timing generation circuit 5.

Further, one of the plurality of sampling signals SS
One is a synchronization pattern insertion signal FS into which a synchronization pattern is inserted. The synchronization pattern insertion signal FS includes a transmission side delay circuit 7 for generating data delayed by one bit from the synchronization pattern insertion signal FS, and a synchronization pattern insertion signal F
A change point detection circuit 8 for detecting a change point of data of the synchronization pattern insertion signal FS from S and the output of the transmission side delay circuit 7
A transmission-side inverter circuit 9 for inverting the output of the synchronization pattern generated by the transmission-side synchronization pattern generation circuit 4, and a synchronization pattern polarity selection circuit 10 for selecting the polarity of the synchronization pattern to be inserted at the synchronization pattern insertion position F. The transmission-side distortion reduction circuit 1 is connected.

In FIG. 1B, a reception-side synchronization pattern generation circuit 15 is a circuit for generating a synchronization pattern on the reception side, and generates the same pattern as that on the transmission side. The synchronization pattern detection circuit 14 includes a reception-side synchronization pattern generation circuit 15.
Is a circuit for detecting a synchronization pattern of the multiplexed signal TD from the synchronization pattern generated in the step (a), and a separation circuit 13 for separating the multiplexed signal TD into a plurality of reception data in synchronization with the detected synchronization pattern. Circuit. The decoding circuit 12 performs a process of reproducing a data signal from each of the separated received data.

Further, the multiplexed signal TD is compared with a synchronous pattern inverter circuit 16 for inverting the output generated by the receiving side synchronous pattern generating circuit 15, and the output of the synchronous pattern inverter circuit 16 is compared with the multiplexed signal TD to synchronize. A match detection circuit 17 for detecting an inverted bit in the pattern;
A separation control circuit 18 that passes a separation signal to the separation circuit 13 based on the output results of the synchronization pattern detection circuit 14 and the coincidence detection circuit 17, and one of the bit positions F where the synchronization pattern is inserted.
Receiving-side delay circuit 1 for detecting data signal before bit
9, a reception inverter circuit 20 for inverting the output of the reception delay circuit 19, and a data insertion selection circuit 2 for selecting the polarity of the insertion data by a control signal from the separation control circuit 18.
1 is connected to the reception-side distortion reduction circuit 11 and the synchronization pattern insertion data FSZ in which the synchronization pattern is inserted is one of the plurality of reception data separated by the separation circuit 13. The signal is input to the decoding circuit 12 via the reduction circuit 11. Then, a reproduction data signal DTZ is output from the output of the decoding circuit 12.

In such a configuration, as shown in FIG. 2, on the transmitting side, the data signal DT is applied to the sample clock S.
By C, a plurality of sampling signals SS are generated. In the synchronization pattern insertion signal FS into which the synchronization pattern is inserted among the plurality of sampling signals SS, the synchronization pattern is inserted by crushing the first bit of each frame.
This synchronization pattern is selected by the synchronization pattern polarity selection circuit 6 for each bit constituting the synchronization pattern, based on the output result of the change point detection circuit 8 whether the synchronization pattern is inverted and inserted or inserted as it is. And inserted. Here, if the synchronization pattern insertion position F does not match the change point detection position of the data signal, the synchronization pattern is inserted as it is. If the synchronization pattern insertion position F matches the change point detection position, the corresponding synchronization pattern is inserted. Bit data is inverted and inserted. Then, each sampling signal SS including the synchronization pattern insertion signal FS is time-division multiplexed,
The multiplexed signal TD is transmitted.

Next, on the receiving side, the received multiplexed signal TD
Is separated into a plurality of pieces of reception data by the separation circuit 13, and the following processing is performed on the synchronization pattern insertion data FSZ in which the synchronization pattern is inserted.

First, when the receiving-side distortion detecting circuit 11 detects that each bit constituting the synchronizing pattern matches the synchronizing pattern generated by the receiving-side synchronizing pattern generating circuit 15, the synchronizing pattern insertion position F indicates a change in the data signal. It is determined that the position does not match the detection position of the point. That is, when the synchronization pattern insertion data FSZ shown in FIG. 2 is a, c, and d, the control signal from the separation control circuit 18 is
Selects the output of the (1-bit preceding data), to reproduce the data signal is inserted into the sync pattern insertion position F.

On the other hand, when it is detected that some of the bits forming the synchronization pattern are inverted, it is determined that the synchronization pattern insertion position F of the inverted bit matches the change point detection position of the data signal DT. Judgment, output of receiving-side inverter circuit 20 (data obtained by inverting data of one bit before)
At the synchronization pattern insertion position F. When it is determined that a part of the synchronization pattern is inverted,
That is, when the synchronization pattern insertion data FSZ shown in FIG. 2 is b, the data signal is reproduced by inserting data obtained by inverting the previous bit data into the synchronization pattern insertion position F.

Thus, the synchronization pattern is inserted.
That reason, problems which could not be recognized at the receiving side the changing point of the data signal is resolved, it is possible to reproduce the bit data of the position where the sync pattern has been inserted correctly.

As described above, the multiplex conversion apparatus of the present invention reproduces a synchronization pattern provided by crushing specific bits in each frame to separate multiplexed signals into original data. It is possible to reduce the error of the reproduced data signal caused by the insertion,
The reliability of the reproduced data is improved.

On the receiving side that receives a multiplexed signal, a partially inverted synchronization pattern is detected. However, when synchronization is established, even if one synchronization pattern mismatch (polarity inversion) is detected, the number of times of mismatch detection is constant. As long as the value does not exceed the value (the number of protection stages), it is not determined that the state is out of synchronization. At this time, if the period of the data signal does not match the synchronization pattern insertion period, the synchronization pattern insertion position does not match the detection position of the change point of the data signal, so that the inverted synchronization pattern does not continue. Therefore, a problem such as loss of synchronization due to inversion of a part of the synchronization pattern does not occur.

[0026]

Since the present invention is configured as described above, the following effects can be obtained.

On the transmitting side, when the detected position of the data signal change point coincides with the synchronization pattern insertion position, the data of the corresponding bit in the synchronization pattern is inverted and inserted, and the detection position of the data signal change point is detected. If the synchronization pattern insertion position does not match the synchronization pattern insertion position, the data of the corresponding bit is inserted according to the synchronization pattern as it is, and the detection position of the change point of the data signal and the synchronization pattern insertion position match or match. Can send information on whether there is any.

At this time, if the synchronization pattern matches on the receiving side, the same data as the bit data immediately before the received data is inserted at the position where the synchronization pattern was inserted, and some bits of the synchronization pattern are inverted. and if that by inserting a position synchronization pattern by inverting the bit data immediately before has been inserted in the received data, bit data of the position where the sync pattern has been inserted is reproduced.
Therefore, the error of the reproduced data signal caused by inserting the synchronization pattern can be reduced, and the reliability of the reproduced data is improved because there is no signal quality deterioration.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a multiplex conversion device of the present invention;
FIG. 2A is a block diagram on the transmitting side, and FIG. 2B is a block diagram on the receiving side.

FIG. 2 is a timing chart showing the operation of the multiplex conversion device of FIG.

3A and 3B are diagrams showing a configuration of a conventional multiplex conversion apparatus, wherein FIG. 3A is a block diagram on a transmission side, and FIG. 3B is a block diagram on a reception side.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transmission-side distortion reduction circuit 2 Sampling circuit 3 Multiplexer 4 Transmission-side synchronization pattern generation circuit 5 Timing generation circuit 6 Synchronization pattern insertion selection circuit 7 Transmission-side delay circuit 8 Change point detection circuit 9 Transmission-side inverter circuit 10 Synchronization pattern polarity selection Circuit 11 Receiving-side distortion reduction circuit 12 Decoding circuit 13 Separating circuit 14 Synchronous pattern detecting circuit 15 Receiving-side synchronous pattern generating circuit 16 Synchronous pattern inverter circuit 17 Match detecting circuit 18 Separation control circuit 19 Receiving-side delay circuit 20 Receiving-side inverter circuit 21 Data insertion selection circuit DT data signal SC sample clock SS sampling signal FS synchronization pattern insertion signal TD multiplexed signal FSZ synchronization pattern insertion data DTZ playback data signal

Claims (2)

(57) [Claims] 1. Asynchronous sampling of a plurality of data signals
And a transmission unit that generates a multiplexed signal by inserting a synchronization pattern for identifying each frame, and detects a synchronization pattern from the received multiplexed signal and separates it into a plurality of received data, in multiplex conversion unit constituted by a receiving unit for reproducing, and the transmission unit, when the detected position of the change point of the data signal and the insertion position of the synchronization pattern matches inverts the synchronization pattern insertion and, when the detected position of the change point of the data signal and the insertion position of the synchronization pattern does not match its said synchronization pattern
A transmission-side distortion reduction circuit for inserting the transmission section as it is, wherein the reception section has the same synchronization pattern as the transmission section generated by the reception section.
The synchronization pattern inserted in the received data
We have time and are in a position which the synchronization pattern has been inserted, the received data the synchronization pattern has been inserted
Insert the same data as the bit data immediately before the position, and generate the same synchronization pattern as the transmitting unit generated by the receiving unit
Of the synchronization pattern inserted in the received data
When the bit of the part is inverted , the synchronization pattern is inserted at the position where the inverted bit was inserted.
Multiplex conversion apparatus characterized by having a reception-side distortion reduction circuit for inserting the inverted data of the bit data immediately before the said position of the received data. 2. The multiplex conversion apparatus according to claim 1, wherein the transmission-side distortion reduction circuit comprises: a transmission-side delay circuit for delaying the asynchronously sampled data signal by one bit; an output signal of the transmission-side delay circuit; a changing point detection circuit for detecting a change point of the data signal by comparing the data signal subjected to asynchronous sampling, the transmitting-side inverter circuit for inverting the generated synchronization pattern on the transmitting unit, the detection of the change point detecting circuit According to the result , the synchronization pattern or the synchronization pattern inverted by the transmission-side inverter circuit.
Includes a synchronization pattern polarity selection circuit for selecting either of the turn, the receiving distortion reduction circuit includes a synchronization pattern inverter circuit for inverting the synchronization pattern generated by the receiving unit, an output of said synchronization pattern inverter circuit The multiplexed signal is compared and inserted into the received data.
A coincidence detection circuit for detecting an inverted bit of the synchronization pattern in the detection result of the inserted synchronization pattern in the received data, and the detection result of said coincidence detection circuit, for separating the multiplexed signal into a plurality of received data A separation control circuit for generating a control signal for receiving the synchronization pattern , a reception delay circuit for detecting bit data immediately before the position where the synchronization pattern was inserted among the reception data where the synchronization pattern was inserted, and the reception delay A receiving-side inverter circuit for inverting bit data detected by the circuit, and the control signal output from the separation control circuit,
Bit data detected by the reception-side delay circuit or bit data inverted by the reception-side inverter circuit
Multiplex conversion unit, wherein either a data insertion selection circuit to be inserted to a position where the sync pattern has been inserted, to have a.