JPH0738860A - Transmission equipment and reception equipment for digital video signal - Google Patents

Abstract

PURPOSE:To obtain the video signal transmission equipment which facilitates circuit design and is low in power consumption and used to multiplex and transmit auxiliary data in blanking periods of a digital video signal. CONSTITUTION:The auxiliary data are written in a memory 106. A multiplex control circuit 109 inputs a video synchronizing signal and outputs a multiplex control signal (e) to a memory control circuit 107 and a multiplexing circuit 108. The memory control circuit 107 outputs a video frequency-divided clock (h), divided by a frequency dividing circuit 112, to the memory 106 according to the multiplex control circuit (e) to control reading operation. The multiplexing circuit 108 multiplexes a video input signal (f) and the read auxiliary data (b) on a time division basis according to the multiplex control signal (e) and outputs the data to a transmission line through a transmitting circuit 111. A reception part separates the video signal and a sound signal by operating reversely to the multiplexing part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal transmission apparatus for multiplexing and transmitting auxiliary data such as a digital audio signal during a blanking period of a digital video signal.

[0002]

2. Description of the Related Art In recent years, in order to create high quality programs,
Digital transmission is being used to connect between professional broadcast equipment. Furthermore, by using time division multiplexing, auxiliary data such as audio signals are multiplexed in the blanking period of the video signal, and the video signal and auxiliary data that were conventionally transmitted through different transmission paths are
A method of transmitting on the same transmission line is under study.

A conventional digital video signal transmission device will be described below separately for a digital video signal transmission device and a digital video signal reception device. First, a conventional digital video signal transmitting device will be described.

FIG. 7 is a block diagram of a conventional digital video signal transmitting apparatus, and FIG. 8 shows the timing of each signal. In FIG. 7, 701 is a video signal input terminal for inputting a video signal, 702 is an auxiliary data input terminal for inputting auxiliary data, 703 is an auxiliary data clock input terminal for inputting an auxiliary data clock, and 704 is an input of a video synchronization signal. Video sync signal input terminal, 705 is a video clock input terminal for inputting a video clock, 706 is a memory for storing auxiliary data, 707 is a memory control circuit for controlling the reading operation of the memory 706, and 708 is a video signal and memory 706. A multiplexing circuit for inputting the read contents and outputting a multiplexed video signal by multiplexing them, 709 is a multiplexing control circuit for controlling the memory control circuit 707 and the multiplexing circuit 708, and 710 is suitable for transmitting the multiplexed video signal. A transmission circuit for converting into a video transmission signal, 711 is a video transmission signal output terminal for outputting a video transmission signal That.

The operation of the digital video signal transmitting apparatus configured as described above will be described below.

First, in the memory 706, the auxiliary data input from the auxiliary data input terminal 702 is stored using the auxiliary data clock input from the auxiliary data clock input terminal 703 as a write clock. Multiple control circuit 7
At 09, the blanking period is detected from the video synchronization signal input from the video synchronization signal input terminal 704, and the multiplex control signal (FIG. 8e) is output. In the memory control circuit 707, when the multiplex control signal e is input, the video clock input terminal 70
The video clock input from FIG.
(FIG. 8c) and reads the stored contents (FIG. 8c).
b).

In the multiplexing circuit 708, when a multiplexing control signal is input, the video signal input from the video signal input terminal 701 (FIG. 8f) is multiplexed with the contents read from the memory 706, and the video multiplexing signal (FIG. 8g) is obtained. Is output. Transmission circuit 71
At 0, the video multiplexed signal g is input and the video transmission signal is output to the video transmission signal output terminal 711.

Next, a conventional digital video signal receiving apparatus will be described. FIG. 9 is a block diagram of a conventional digital video signal receiving apparatus, and FIG. 10 shows the timing of each signal.

In FIG. 9, reference numeral 901 denotes a video transmission signal input terminal for inputting a video transmission signal transmitted through a transmission line,
902 is a receiving circuit that inputs a video transmission signal and outputs a video multiplex signal, a video synchronizing signal, and a video clock, 903 is a memory that stores auxiliary data, 904 is a memory control circuit that controls the writing operation of the memory 903, and 905 is Auxiliary data clock recovery circuit that recovers the auxiliary data clock,
906 is a demultiplexing control circuit that controls the memory control circuit 904 and the auxiliary data clock recovery circuit 905, 907 is a video multiplex signal output terminal that outputs a video multiplex signal, 908 is an auxiliary data output terminal that outputs auxiliary data, and 909 is an auxiliary An auxiliary data clock output terminal that outputs a data clock, and a video clock output terminal 910 that outputs a video clock.

The operation of the digital video signal receiving apparatus configured as described above will be described below.

First, in the receiving circuit 902, the video transmission signal input from the video transmission signal input terminal 901 is input, and the video multiplexed signal g is stored in the memory 903 and the video multiplexed signal output terminal 9.
07 to output the video synchronization signal to the demultiplexing control circuit 906.
The video clock d is supplied to the memory control circuit 904, the auxiliary data clock reproduction circuit 905, and the video clock output terminal 91.
Output to 0. The demultiplexing control circuit 906 detects the blanking period from the video synchronization signal and outputs the demultiplexing control signal (FIG. 10e).

When the demultiplexing control signal e is input, the memory control circuit 904 outputs the video clock (FIG. 10d) to the memory 903 (FIG. 10c), and the memory 903 multiplexes during the blanking period of the video multiplexed signal g. The auxiliary data stored is stored. The auxiliary data clock reproduction circuit 905 reproduces the auxiliary data clock (FIG. 10h) by the demultiplexing control signal e and the video clock d and outputs it to the memory 903 to read the auxiliary data (FIG. 10i).

[0013]

However, in the above-mentioned conventional configuration, when the auxiliary data stored in the memory is multiplexed with the video signal in the digital video signal transmitting apparatus, the auxiliary data is transmitted from the memory at the same transmission rate as the video signal. Need to read. Further, in the digital video signal receiving apparatus, when the auxiliary data multiplexed in the video multiplexed signal is written in the memory, it is necessary to write the auxiliary data in the memory at the same transmission rate as the video signal. Therefore, there is a problem that a high-speed memory is required, power consumption of the device is high, and the memory is controlled at high speed, which complicates the design of the device.

The present invention solves the above-mentioned problems of the prior art. By enabling the use of a low-speed memory, low power consumption and easy designing of a digital video signal transmission device (digital video signal transmission Device / digital video signal receiving device).

[0015]

To achieve this object, a digital video signal transmitting apparatus of a digital video signal transmitting apparatus of the present invention comprises a memory for storing auxiliary data and a video clock divided by n (n is 2). A frequency divider circuit that outputs the video division clock that is the above integer), a memory control circuit that controls the memory read operation, a video signal and the contents read from the memory are input, and video multiplexing is performed. It has a configuration including a multiplexing circuit for outputting a signal, a memory control circuit, a multiplexing control circuit for controlling the multiplexing circuit, and a transmitting circuit for converting the video multiplexed signal into a video transmission signal suitable for transmission.

The digital video signal receiving device of the digital video signal transmitting device of the present invention receives the received video transmission signal and outputs a video multiplex signal, a video synchronizing signal and a video clock, and a video clock n. A frequency dividing circuit for outputting a divided (n is an integer of 2 or more) video division clock, a memory for storing auxiliary data multiplexed in the video multiplex signal, and a memory control circuit for controlling a writing operation of the memory. , An auxiliary data clock recovery circuit for recovering the auxiliary data clock, and a demultiplexing control circuit for controlling the memory control circuit and the auxiliary data clock recovery circuit.

[0017]

With this configuration, the digital video signal transmitting device of the digital video signal transmitting device of the present invention stores the auxiliary data in the memory, and when the video signal blanking period is detected from the video synchronizing signal by the multiplexing control circuit, the multiplexing is performed. When the control signal is output to the memory control circuit and the multiplexing circuit, and when the multiplexing control signal is input to the memory control circuit, the video division clock from the frequency dividing circuit is output to the memory and the contents stored in the memory are output to the multiplexing circuit. When the output is output and the multiplex control signal is input by the multiplex circuit, the contents read from the memory are multiplexed to the video signal, and the output of the multiplex circuit is sent to the transmission line by the transmission circuit. Since the transmission rate of the video signal is 1 / n, and a low-speed memory can be used, the power consumption of the device can be reduced and its design can be facilitated.

With this configuration, the digital video signal receiving device of the digital video signal transmitting device of the present invention receives the video transmission signal transmitted from the transmission line by the receiving circuit, and the video multiplexing signal, the video synchronization signal, the video signal. When the clock is output and the demultiplexing control circuit detects the video blanking period from the video synchronization signal, the demultiplexing control signal is output to the memory control circuit and the auxiliary data reproducing circuit, and the demultiplexing control signal is input to the memory control circuit. At that time, the video frequency dividing clock from the frequency dividing circuit is output to the memory, and this is used as a writing clock to store the auxiliary data multiplexed in the blanking period of the video multiplexed signal in the memory, and the auxiliary data clock regeneration circuit , The auxiliary data regenerated clock is used to read the auxiliary data stored in the memory.
Memory writing speed is 1 / n of video signal transmission rate
Since the low-speed memory can be used, the power consumption of the device can be reduced and its design can be facilitated.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings separately for a digital video signal transmitting device and a digital video signal receiving device. First, the first
The digital video signal transmitting apparatus of the embodiment will be described.

FIG. 1 is a block diagram of the digital video signal transmitting apparatus of the first embodiment, and FIG. 2 shows the timing of each signal. In FIG. 1, 101 is a video signal input terminal for inputting a video signal f, 102 is an auxiliary data input terminal for inputting auxiliary data such as a digital audio signal,
103 is an auxiliary data clock input terminal for inputting an auxiliary data clock, 104 is a video synchronization signal input terminal for inputting a video synchronization signal, and 105 is a video clock input terminal for inputting a video clock d.

Reference numeral 106 is a memory for storing auxiliary data, 1
Reference numeral 07 is a memory control circuit for controlling the read operation of the memory 106, and 108 is a multiplexing circuit for inputting the video signal f and the content (b) read from the memory 106 and outputting a video multiplexed signal g obtained by multiplexing them. , 109 are multiplex control circuits for controlling the memory control circuit 107 and the multiplex circuit 108, 11
0 is a transmission circuit that converts the video multiplexed signal g into a video transmission signal suitable for transmission, a video transmission signal output terminal that outputs the video transmission signal to 111, and 112 is a video division clock h obtained by dividing the video clock d by two. It is a frequency dividing circuit for outputting.

The operation of the digital video signal transmitting apparatus of the first embodiment constructed as above will be described below.

First, in the memory 106, the auxiliary data input from the auxiliary data input terminal 102 is stored using the auxiliary data clock input from the auxiliary data clock input terminal 103 as a write clock. Multiplex control circuit 1
At 09, the blanking period is detected from the video synchronization signal input from the video synchronization signal input terminal 104, and the multiplex control signal (FIG. 2e) is output.

In the memory control circuit 107, the multiplex control signal e
When the input is input, the video frequency dividing clock (FIG. 2h) from the frequency dividing circuit 112 is output to the memory 106 (FIG. 2c), and the stored contents are read (FIG. 2b). In the multiplexing circuit 108, when the multiplexing control signal e is input, the memory output signal b having the content read from the memory 106 is multiplexed with the video signal (FIG. 2f) input from the video signal input terminal 101, and the video multiplexing signal ( 2g) is output. The transmission circuit 110 inputs the video multiplexed signal g and outputs the video transmission signal to the video transmission signal output terminal 111.

As described above, according to the digital video signal transmitting apparatus of the first embodiment, when the auxiliary data is multiplexed on the video signal, the reading speed of 1/2 of the transmission speed of the video signal is read from the memory 106. Since the auxiliary data is read, a low speed memory can be used. Therefore, the power consumption of the device can be reduced and the design thereof can be facilitated.

Next, the digital video signal receiving apparatus of the first embodiment will be described. FIG. 3 is a block diagram of the digital video signal receiving apparatus of the first embodiment, and FIG. 4 shows the timing of each signal.

In FIG. 3, reference numeral 301 denotes a video transmission signal input terminal for inputting a video transmission signal transmitted through a transmission line,
A receiving circuit 302 receives a video transmission signal and outputs a video multiplex signal g, a video synchronization signal, and a video clock d, 303
Is a memory for storing auxiliary data, 304 is a memory 303
, 305 is an auxiliary data clock recovery circuit for recovering the auxiliary data clock, 306 is a demultiplexing control circuit for controlling the memory control circuit 304 and the auxiliary data clock recovery circuit 305, 307
Is a video multiplex signal output terminal for outputting the video multiplex signal e, 3
08 is an auxiliary data output terminal for outputting auxiliary data j, 3
Reference numeral 09 is an auxiliary data clock output terminal for outputting the auxiliary data clock i, 310 is a video clock output terminal for outputting the video clock d, and 311 is a frequency dividing circuit for outputting a video frequency dividing clock h obtained by dividing the video clock by two. .

The operation of the digital video signal receiving apparatus of the first embodiment constructed as described above will be described below.

First, in the receiving circuit 302, the video transmission signal input from the video transmission signal input terminal 301 is input, and the video multiplexed signal g is stored in the memory 303 and the video multiplexed signal output terminal 3.
07 and outputs the video synchronization signal to the demultiplexing control circuit 306.
And further outputs the video clock d to the video clock output terminal 310 and the frequency dividing circuit 311.

The demultiplexing control circuit 306 detects the blanking period from the video synchronizing signal and outputs the demultiplexing control signal (FIG. 4e) to the memory control circuit 304 and the auxiliary clock reproducing circuit 305. When the demultiplexing control signal e is input, the memory control circuit 304 outputs the video frequency dividing clock (FIG. 4h) from the frequency dividing circuit 312 to the memory 303 (FIG. 4c), and the blanking period of the video multiplexing signal g. The auxiliary data, which is multiplexed with the above, is stored in the memory 303.

The auxiliary data clock reproduction circuit 305 reproduces the auxiliary data clock (FIG. 4i) by the demultiplexing control signal e and the video clock d, outputs it to the memory 303, and reads the auxiliary data (FIG. 4h).

As described above, in the embodiment of the first digital video signal receiving apparatus, when the auxiliary data is demultiplexed from the video multiplexed signal, the transmission rate of the video signal is 1/2
Since the auxiliary data is written in the memory 303 at the writing speed of 1, the low speed memory can be used. for that reason,
The power consumption of the device can be reduced and the design can be facilitated.

A second embodiment of the present invention will be described below with reference to the drawings, separately for a digital video signal transmitting device and a digital video signal receiving device.

In the second embodiment, the video signal is a signal in which a synchronization code or the like is multiplexed, and the synchronization can be detected from the video signal. First, the digital video signal transmitting apparatus of the second embodiment will be described.

FIG. 5 is a block diagram of the digital video signal transmitting apparatus of the second embodiment, and FIG. 2 shows the timing of each signal.

In FIG. 5, 501 is a video signal input terminal for inputting a video signal, 502 is an auxiliary data input terminal for inputting auxiliary data, 503 is an auxiliary data clock input terminal for inputting an auxiliary data clock, and 504 is an image signal. A sync separation circuit that detects a multiplexed sync code and outputs a video sync signal, 505 is a video clock input terminal that inputs a video clock, 506 is a memory that stores auxiliary data, and 507 is a read operation of the memory 506. A memory control circuit for controlling 508, a multiplexing circuit for inputting a video signal and contents read from the memory 506 and outputting a video multiplexed signal by multiplexing them, 509 for controlling the memory control circuit 507 and the multiplexing circuit 508. Multiple control circuit, 51
0 is a transmission circuit for converting a video multiplexed signal into a video transmission signal suitable for transmission, and a video transmission signal output terminal for outputting the video transmission signal to 511. 512 is a portion for outputting a video division clock obtained by dividing the video clock by two. It is a circuit.

The operation of the digital video signal transmitting apparatus of the second embodiment constructed as above will be described below.

First, the memory 506 stores the auxiliary data input from the auxiliary data input terminal 502 using the auxiliary data clock input from the auxiliary data clock input terminal 503 as a write clock. Multiple control circuit 5
09, the blanking period is detected from the video synchronization signal input from the sync separation circuit 504, and the multiplexing control signal (see FIG. 2) is detected.
e) is output. When the multiplexing control signal e is input, the memory control circuit 507 outputs the video frequency dividing clock (FIG. 2h) from the frequency dividing circuit 512 to the memory 506 (FIG. 2c) and reads the stored contents (FIG. 2b).

When the multiplexing control signal e is input, the multiplexing circuit 508 multiplexes the contents read from the memory 506 with the video signal (FIG. 2f) input from the video signal input terminal 501 to generate the video multiplexing signal (FIG. 2g). ) Is output. Transmission circuit 5
In 10, the video multiplexed signal g is input and the video transmission signal is output to the video transmission signal output terminal 511.

As described above, according to the digital video signal transmitting apparatus of the second embodiment, when the auxiliary data is multiplexed on the video signal, the memory 506 reads the data at half the transmission speed of the video signal. Since the auxiliary data is read, a low speed memory can be used. Therefore, the power consumption of the device can be reduced and the device can be easily designed.

Next, the digital video signal receiving apparatus of the second embodiment will be described. FIG. 6 is a block diagram of the digital video signal receiving apparatus of the second embodiment, and FIG. 4 shows the timing of each signal.

In FIG. 6, reference numeral 601 denotes a video transmission signal input terminal for inputting a video transmission signal transmitted through a transmission line,
Reference numeral 602 is a receiving circuit that inputs a video transmission signal and outputs a video multiplexed signal and a video clock, 603 is a memory that stores auxiliary data, 604 is a memory control circuit that controls a writing operation of the memory 603, and 605 is an auxiliary data clock. An auxiliary data clock reproducing circuit for reproducing, 606 a demultiplexing control circuit for controlling the memory control circuit 604 and the auxiliary data clock reproducing circuit 605, 607 a video multiplexed signal output terminal for outputting a video multiplexed signal, and 608 for outputting auxiliary data. Auxiliary data output terminal, 609 is an auxiliary data clock output terminal for outputting an auxiliary data clock, 610 is a video clock output terminal for outputting a video clock, and 611 is a frequency dividing circuit for outputting a video frequency dividing clock obtained by dividing the video clock by two. Is. Reference numeral 612 is a sync separation circuit that detects a sync code multiplexed in the video multiplex signal and outputs the video sync signal.

The operation of the digital video signal receiving apparatus of the second embodiment constructed as above will be described below.

First, in the receiving circuit 602, the video transmission signal input from the video transmission signal input terminal 601 is input, and the video multiplexed signal g is stored in the memory 603 and the video multiplexed signal output terminal 6.
07 and the sync separation circuit 612 to output the video clock d
Is output to the video clock output terminal 610 and the frequency dividing circuit 611. In the demultiplexing control circuit 606, the synchronous demultiplexing circuit 61
The blanking period is detected from the video synchronization signal input from the memory 2 and the demultiplexing control signal (FIG. 4e) is sent to the memory control circuit
04 and the auxiliary clock recovery circuit 605.

When the demultiplexing control signal e is input, the memory control circuit 604 outputs the video frequency dividing clock (FIG. 4h) from the frequency dividing circuit 612 to the memory 603 (FIG. 4).
c), the memory 603 stores the auxiliary data multiplexed during the blanking period of the video multiplexed signal. The auxiliary data clock reproduction circuit 605 reproduces the auxiliary data clock (FIG. 4i) by the demultiplexing control signal e and the video clock d, outputs it to the memory 603, and reads the auxiliary data (FIG. 4j).

As described above, in the second embodiment of the digital video signal receiving apparatus, when the auxiliary data is demultiplexed from the video multiplexed signal, the transmission rate of the video signal is ½.
Since the auxiliary data is written to the memory 603 at the writing speed of, the low speed memory can be used. for that reason,
The device can reduce power consumption and facilitate its design.

[0047]

As described above, according to the present invention, in the digital video signal transmitting device of the digital video signal transmitting device,
A memory for storing auxiliary data, a frequency dividing circuit for outputting a video frequency dividing clock obtained by dividing the video clock by n, a memory control circuit for controlling the reading operation of the memory, and a video signal and contents read from the memory. Is provided and a multiplexed circuit for outputting a multiplexed video signal, and a memory control circuit and a multiplexing control circuit for controlling the multiplexed circuit are provided, and a digital video signal receiving device of a digital video signal transmitting device A frequency dividing circuit for outputting a video frequency-divided clock obtained by frequency-dividing the clock by n, a memory for storing auxiliary data multiplexed in the video multiplexed signal, a memory control circuit for controlling a writing operation of the memory, and an auxiliary data clock. An auxiliary data clock recovery circuit for recovery, a memory control circuit, and a demultiplexing control circuit for controlling the auxiliary data clock recovery circuit are provided. And by, with low power consumption, and is one that can achieve easy digital video signal transmission apparatus design.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a video digital transmitter of the present invention.

FIG. 2 is a first and second video digital transmission device of the present invention.
Timing diagram of the example

FIG. 3 is a block diagram of a first embodiment of a video digital receiving apparatus of the present invention.

FIG. 4 is a first and second video digital receiver of the present invention.
Timing diagram of the example

FIG. 5 is a block diagram of a second embodiment of a video digital transmitting apparatus of the present invention.

FIG. 6 is a block diagram of a second embodiment of a video digital receiving apparatus of the present invention.

FIG. 7 is a block diagram of a conventional video digital transmission device.

FIG. 8 is a timing diagram of a conventional video digital transmitter.

FIG. 9 is a block diagram of a conventional video digital receiver.

FIG. 10 is a timing chart of a conventional video digital receiver.

[Explanation of symbols]

 106 Memory 107 Memory Control Circuit 108 Multiplexing Circuit 109 Multiplexing Control Circuit 112 Frequency Dividing Circuit 303 Memory 304 Memory Control Circuit 305 Auxiliary Data Clock Regenerating Circuit 306 Multiplexing Demultiplexing Control Circuit 311 Dividing Circuit 504 Sync Demultiplexing Circuit 506 Memory 507 Memory Control Circuit 508 Multiplexing Circuit 509 Multiplexing control circuit 512 Dividing circuit 603 Memory 604 Memory control circuit 605 Auxiliary data clock recovery circuit 606 Multiplexing demultiplexing control circuit 611 Dividing circuit 612 Synchronous demultiplexing circuit

Claims (6)

[Claims] 1. A memory for storing auxiliary data, a frequency dividing circuit for dividing a video clock by n (n is an integer of 2 or more), and a memory control circuit for controlling a read operation of the memory.
A multiplexing circuit for multiplexing the digital video signal and the output of the memory; and a multiplexing control circuit for controlling the memory control circuit and the multiplexing circuit, wherein the memory stores the auxiliary data, and the multiplexing control circuit is , When the blanking period is detected from the video sync signal, the multiplex control signal is output,
The memory control circuit inputs the video division clock divided by the division circuit, and when the multiplex control signal is input, reads the contents stored in the memory at the cycle of the video division clock. However, the digital video signal transmitting apparatus, wherein the multiplexing circuit multiplexes the contents with the digital video signal when the multiplexing control signal is input. 2. A memory for storing auxiliary data, a frequency dividing circuit for dividing a video clock by n (n is an integer of 2 or more), and a memory control circuit for controlling a write operation of the memory.
An auxiliary data clock regenerating circuit for regenerating an auxiliary data clock and a demultiplexing control circuit for controlling the memory control circuit are provided, and the demultiplexing control circuit inputs a video synchronization signal and demultiplexes when a blanking period is detected. A demultiplexing control signal is output, the memory control circuit inputs the video frequency dividing clock divided by the frequency dividing circuit, and when the demultiplexing control signal is input, at the cycle of the video frequency dividing clock, A video multiplex signal is written in a memory, the auxiliary data clock recovery circuit inputs the multiplex demultiplexing control signal and the video frequency dividing clock, and recovers the auxiliary data clock,
A digital video signal receiving device, characterized in that the auxiliary data stored in the memory is read at a cycle of the auxiliary data clock. 3. A digital video signal transmitting apparatus according to claim 1 and a digital video signal receiving apparatus according to claim 2, wherein the output of the multiplex circuit of the digital video signal transmitting apparatus is transmitted to the digital circuit via a transmission line. A digital video signal transmission device characterized by transmitting to a memory input of a video signal reception device. 4. A memory for storing auxiliary data, a sync separation circuit for inputting a digital video signal and outputting a video synchronizing signal, and a frequency dividing circuit for dividing the video clock by n (n is an integer of 2 or more). A memory control circuit for controlling the reading operation of the memory; a multiplexing circuit for multiplexing the digital video signal and the output of the memory; and a multiplexing control circuit for controlling the memory control circuit and the multiplexing circuit, The memory stores the auxiliary data, and the multiplexing control circuit is
When the video synchronization signal is input and a blanking period is detected, a multiplexing control signal is output, and the memory control circuit is
Input the video division clock divided by the divider circuit,
When the multiplex control signal is input, the content stored in the memory is read at the cycle of the video division clock,
The digital video signal transmitting apparatus, wherein the multiplexing circuit multiplexes the contents with the digital video signal when the multiplexing control signal is input. 5. A memory for storing auxiliary data, and a sync separation circuit for inputting a video multiplex signal and outputting a video sync signal,
A frequency dividing circuit for dividing the video clock by n (n is an integer of 2 or more), a memory control circuit for controlling the write operation of the memory, an auxiliary data clock reproducing circuit for reproducing an auxiliary data clock, and the memory control circuit. And a demultiplexing control circuit that controls the input signal, the demultiplexing control circuit inputs the video synchronization signal, outputs a demultiplexing control signal when a blanking period is detected, and the memory control circuit outputs the frequency division signal. When the video division clock divided by the circuit is input and the demultiplexing control signal is input, the video division signal is written in the memory at the cycle of the video division clock,
The auxiliary data clock reproduction circuit inputs the demultiplexing control signal and the video division clock, reproduces the auxiliary data clock, and reproduces the auxiliary data stored in the memory.
A digital video signal receiving device, characterized in that the data is read at the cycle of the auxiliary data clock. 6. A digital video signal transmitting device according to claim 4 and a digital video signal receiving device according to claim 5, wherein the output of the multiplex circuit of the digital video signal transmitting device is transmitted via a transmission line to the digital circuit. A digital video signal transmission device characterized by transmitting to a memory input of a video signal reception device.