JP2002135735A - Transmitting apparatus and reproducing apparatus of image with sound - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compose a simple encoding and demodulation circuit by means of arranging a gate signal to indicate clearly an effective duration of sound data at a specified timing during a horizontal blank duration, when both digital sound data and digital image data are transmitted by multiplexing. SOLUTION: Digital sound data (L or R, each 16 bits) sampled at 48 kHz are inputted and stored in FIFO 31. A signal LRCK, on which the digital sound data L or R is indicated by high or low, is inputted into a counter 32, and is reset at the rise of a horizontal synchronous signal. Accordingly, the number of frames of the sound data stored in the FIFO 31 is counted in the counter 32. Then, when transmittance of one horizontal direction image data is completed, a gate signal A-DE, which indicates the effective duration of sound data corresponding to the number of the frames counted in the counter 32, is outputted. During the time the gate signal A-DE is high, a switch SW 35 is switched to the signal of the FIFO 31, and the sound data of the FIFO 31 is multiplexed to a channel transmitting image data theretofore and transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video transmission apparatus with audio for multiplexing digital audio data with a digital video signal and transmitting the multiplexed digital audio data, and a reproducing apparatus therefor.

[0002]

2. Description of the Related Art A proposal of this kind is disclosed in Japanese Patent Laid-Open No. 5-64.
171 publication. It describes a method of multiplexing digital video and audio in a time-division manner and transmitting and demodulating them on the same line.

[0003]

However, the above technique is to transmit either or both of the number information of the audio sampling data and the position information indicating the timing position of the audio (sound) sampling data in the digital video signal.

[0004] Therefore, GVIF (Gigabit Video Interface)
When applied to the technique using ce), there is a disadvantage that an encoding circuit for obtaining number or position information and a demodulation circuit for obtaining audio data from the transmitted number or position information become complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and when multiplexing digital audio data and digital video data, a gate signal indicating a period during which the audio data is valid is replaced with a gate signal indicating a period during which the horizontal blank period is predetermined. It is an object of the present invention to provide a transmission apparatus and a method for transmitting video data with sound, which can be provided at the timing so that the encoding / demodulation circuit can have a simple configuration.

[0006]

In order to solve this problem, for example, a video transmission apparatus with sound according to the present invention has the following arrangement. That is, a video transmission device with audio that multiplexes digital audio data with a digital video signal and transmits the digital audio data, and a buffer memory that stores digital audio data input in chronological order, and a digital video signal within a horizontal blank period. A gate signal generating means for generating a gate signal synchronized with a carrier clock of digital video data for a time length corresponding to the amount of digital audio data stored in the buffer memory at a predetermined timing; After the transmission of the video signal, the digital audio data stored in the buffer memory within the section of the gate signal, in synchronization with the carrier clock of the digital video data, transmission means for transmitting the digital audio data together with the gate signal Is provided.

[0007]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

<First Embodiment> FIG. 2 shows the overall configuration of a system to which the present embodiment is applied. 11 is an IRD (Integrated Receiver Decoder) for receiving digital broadcasting,
Reference numeral 21 denotes a display / reproduction unit for displaying / reproducing a video / audio signal from the IRD 11. The broadcast here is DVB (Digit
al Video Broadcasting) broadcasting system, video is ISO
/ IEC61818-2 MPEG2, audio is ISO / IEC6
It is assumed that the data is sent according to MPEG2 of 1818-3. Reference numeral 17 denotes a CPU that controls the entire IRD according to a program, 18 denotes a memory (comprising a ROM and a RAM) that stores the program and is also used as a work area of the CPU, and 19 denotes a common bus that connects the CPU 17 to each unit. . A signal from the tuner 12 for receiving a digital broadcast wave and selecting a desired frequency in accordance with an instruction from the CPU 17 is demodulated through a demodulation circuit 13. Next, a stream having a desired PID is selected from the multiplexed stream sent to the demultiplexer 14, and the video / audio stream is sent to the AV decoder 15, where it is decoded into uncompressed video / audio data. The digital video signal 151 and the audio signal 152 are transmitted to the transmission unit 16. Although the details of the transmission unit 16 will be described later, these video and audio signals are multiplexed in a time-division manner, further multiplexed by a GVIF transmission chip, and sent to the display / playback unit 21 via a pair of differential GVIF cables.

The display / playback unit 21 converts the GVIF signal to a GVIF signal.
A receiving unit 22 demodulated by the IF receiving chip and further separated into video and audio signals, a drive unit 23 that drives the separated video signal from the receiving unit 22 into a signal that can be displayed on the display 24, It comprises an AMP 25 for amplifying the separated audio signal and a speaker 26 for converting it into sound.

FIG. 3 shows a detailed block diagram of the transmission section 16. The input video signal 151 includes RGB 8-bit video data V-DATA, a vertical synchronization signal VSYNC, and a horizontal synchronization signal HSY.
NC, V-DE (DataEnabl) indicating the range of effective video data
e) Video clock V-CK. Here, the video data is horizontal 6
It has a resolution of 40 pixels and a height of 480 pixels, a horizontal synchronizing signal of 31.5 KHz, a video clock of 26 MHz, and these signals are synchronized by the video clock.

The input audio signal 152 is serial audio data having a resolution of 16 bits each of stereo L / R sampled at 48 KHz asynchronous with the video clock.
A-DATA signal, LRCK signal indicating left channel in high period and right channel in low period, frequency 1.53 which is 32 times 48 KHz
6-MHz A-CK signal.

The write operation of audio data will be described with reference to FIG. 4 and its timing chart.

The audio data of 16 bits each of L and R sampled at 48 KHz is a signal c of FIG. 4 synchronized with A-CK.
, The first 16 bits indicate the left channel (DL0, DL1,..., DL15), the next 16 bits indicate the right channel (DR0, DR1,..., DR15). And this will be repeated. The audio data is written into the FIFO 31 bit by bit using A-CK as a write clock,
In a frame, it takes 48 KHz, that is, 20.8 μsec.

Next, the operation of reading audio data from the FIFO 31 (also outputting to the reproduction side) will be described with reference to FIG. 3 which is a block diagram and FIG. 5 which is a timing diagram.

The counter 32 is asynchronously reset at the rise of the horizontal synchronization signal HSYNC, and has an output for counting at the rise of the LRCK signal. Therefore, the output value of the counter 32 is 0, 1, or 2 (it may be 0 or 1) as a count signal (see FIG. 5D). The timing generator 33 is a circuit for generating timing, and generates a timing having a period proportional to the count value of the counter 32 after V-DE indicating the range of effective video data.
For example, if the count value is 1, the timing for 32V-DE
If the count value is 2, the timing for 64V-DE is generated,
This is an A-DE signal indicating the range of valid audio data. The section of the A-DE signal is stored in the FIFO 31 and corresponds to the number of unread frames.

An AND circuit 3 for taking the product of the A-DE signal and the V-CK signal
4 is a read clock for the FIFO 31, a read clock corresponding to the frame written to the FIFO 31 is generated between the valid audio data ranges, and the video clock is converted from the original sampling clock as shown in FIG. The audio data AT-DATA is read out one bit at a time in the format converted to the speed. It takes 1.2 μsec to read one frame. The switch SW35 is an A-DE indicating the range of valid audio data.
Only when the signal is high, the audio data is switched to the audio data AT-DATA instead of R0 (the least significant bit of the red component) of the video data. These data are transmitted by GVIF-GVIF-
It is input to TX36. For example, it is assumed that “CXB1455R” manufactured by SONY is used as a GVIF transmission chip (of course, the present invention is not limited to this as long as it performs the same operation). This chip has a resolution of 1024 pixels
A chip capable of inputting video data of 8 bits each of RGB up to 768 pixels vertically, a horizontal / vertical synchronization signal, a video enable signal, a video clock signal, and a control signal to obtain a differential output of GVIF. A signal corresponding to the video signal 151 is input to each input terminal of the horizontal / vertical synchronization signal, the video enable signal, and the video clock signal of this chip. An A-DE signal indicating the range of effective audio data is connected to the control signal terminal CNTL, and the output of the SW 35 is connected to any one of the 24 bit video terminals, for example, R0 which is the least significant bit of the R signal in the embodiment. While the audio data is valid, the R0 signal indicates the audio data. Due to the restrictions of the GVIF transmission chip, VSYNC / HSY
There is a restriction that the NC signal and the control signal must not change within two video clocks. Since the audio data has a maximum of two frames, that is, 2 × 32 = 64 video clocks, the front porch time needs to be set to 64 + 2 = 66 video clocks, that is, 2.6 μsec or more. As described above, the video signal and the audio signal can be multiplexed in a time division manner, converted to a GVIF signal, and transmitted.

The reproducing operation will be described with reference to FIG. 6 which is a block diagram of the receiving section 22 in the display / reproducing section 21 and FIG. 7 which is a timing chart.

The GVIF signal transmitted by the transmitting unit 16 is transmitted to the receiving unit 22 by the GVIF receiving chip GVIF.
The signal is decoded into the original signal using F-RX62 (for example, “CXB1445R” manufactured by SONY). The video signal 221 includes video data V-DATA of 8 bits for each of RGB, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and a V-DE (Da) indicating a range of effective video data.
taEnable), the video clock V-CK, and the drive unit 2
Sent to 3.

The following processing is performed for the audio signal 222.

The A-DE signal (gate signal) connected to the control output terminal CNTL of the GVIF-RX62 and indicating the range of valid audio data synchronized with the video clock V-CK is high.
Then, it is determined that the audio data has become valid, and the 5-counter 65 starts counting, generates a T-LRCK signal having a 32 V-CK cycle as shown in FIG. 7D, and inputs it to the DI1 terminal of the FIFO 67. On the other hand, the output of the D-FF 63 whose input using V-CK as a clock is R0 (the least significant bit of the R component) is delayed by 1 V-CK, and this is used as audio data A-DATA. The output of the D-FF 64 whose input is CNTL using the V-CK as a clock creates an AD-DE signal obtained by delaying the A-DE signal by 1 V-CK. The output of the AND circuit 65 that takes the product of the AD-DE signal and the V-CK signal is used as a write clock for the FIFO 67, and audio data is written to the FIFO 67.

The VCO 72 oscillates with a center oscillation frequency of 1.536 MHz, which is 32 times the sampling clock of the digital audio signal. The output signal of this VCO 72 is
3, the frequency is divided by 32 to be about 48 KHz.
The phase is compared with the LRCK signal from the DO1 terminal of the IFO 67.
The output signal of the phase comparator 70 is supplied to the VCO 7 through the LPF 71.
2 is supplied. Thus, the VCO 72 can generate a stable frequency. The output signal from the VCO 72 is connected to the read clock of the FIFO 67,
Signal. By providing the read clock A-CK signal to the FIFO 72, audio data is called up in 32-bit units, that is, one frame unit, and connected to the DATA input of the D / A converter 68. The left and right analog signals are extracted by discriminating the channels, and sent to the AMP 25 as audio signals 222.

As described above, a signal obtained by multiplexing a video signal and an audio signal in a time-division manner and further converted and transmitted to a GVIF signal can be separated and demodulated into the original video signal and audio signal.

The operation of this embodiment will be described with reference to FIG.

The audio data sampled at 48 KHz becomes serial data as shown in FIG. The audio data indicates that the audio data is frequency-converted with an asynchronous video clock to shorten the transmission period of the audio data, thereby performing multiplex transmission in the blank range of the effective video data range (d). At this time, a gate signal A-DE indicating that the audio data is valid is also transmitted. This signal A-
As shown in the figure, the gate period of the DE is F
Depends on the number of frames stored in the IFO,
Not fixed.

In this example, the audio data is transmitted during the horizontal front porch period. However, if the transmission chip is restricted such that VSYNC and HSYNC must not change within the control signal and two video clocks, the horizontal back porch period is required. Alternatively, audio data may be transmitted during the horizontal synchronization period.

<Second Embodiment> FIG. 8 shows the configuration of the transmitting section 16 of the second embodiment, and FIG. 9 shows the timing thereof, which will be described below. Input digital video signal 151
The frequency and the like of the audio signal 152 are the same as in the first embodiment.

In FIG. 8, reference numeral 80 denotes a serial / parallel converter which converts serial digital audio data A-DATA sent in synchronization with the A-CK clock into A-CK based on the rising edge of LRCK.
Is counted and converted into parallel data for each of the left channel and the right channel by 16 bits. Reference numeral 82 denotes a Q1 terminal for outputting a write signal W-CK at the timing of the position of the last bit of audio data as shown in FIG. 9D based on the LRCK signal and the A-CK clock, and at the rising edge of the horizontal synchronization signal HSYNC. Asynchronous reset and rise of LRCK signal to 0, 1,
It is a timing generator that has a Q2 terminal for counting as 2,... And outputs it as a count signal. FIFO
Reference numeral 81 writes 16-bit audio data from the serial / parallel converter 80 with the Q1 output of the timing generator 82 for each of the left and right channels.

On the other hand, a timing generator 83 is a circuit for generating timing, and a V-V signal indicating a range of effective video data.
Create a timing after DE with a period proportional to the count value. For example, if the count value is 1, the timing corresponding to 2 V-DE is generated, and if the count value is 2, the timing corresponding to 4 V-DE is generated, and this is set as the A-DE signal indicating the range of the valid audio data. If the output of the AND circuit 84, which takes the product of the A-DE signal and the V-CK signal, is used as the read clock of the FIFO 81, a read clock is generated during the range of valid audio data, and the speed is converted from the original sampling clock to the video clock. The audio data AT-DATA is read out in 16 bits at a time in the specified format. It takes 0.08 μsec to read one frame.
The switch SW85 sets the video data R7 only while the A-DE signal (gate signal) indicating the valid audio data range is high:
Switching to audio data AT-DATA instead of 0 and G7: 0. These data are transmitted by GVIF-TX, a GVIF transmission chip.
36. Switch SW to 16 bits of the 24 bit video terminal, for example, a total of 16 bits of R and B signals
When the audio data is valid by connecting the 85 outputs, R
And the B signal will indicate audio data. GVIF above
Due to the limitations of the transmission chip, there is a restriction that the VSYNC / HSYNC signal and the control signal must not change within two video clocks. Audio data can be up to 2 frames, that is, 2x2
= 4 video clocks, so the front porch time is 4
It is necessary to set + 2 = 6 video clocks, that is, 0.2 μsec or more. As described above, the video signal and the audio signal can be multiplexed in a time-division manner, converted to a GVIF signal, and transmitted.

The receiving section 22 also sets the FIFO of the audio data to 16
If writing and calling can be performed by converting into bits, the video signal and the audio signal are multiplexed in a time-division manner in the same configuration as the first embodiment described above, and the signal converted and transmitted to the GVIF signal is also used. Separates the original video signal and audio signal
Demodulation is possible.

<Third Embodiment> FIG. 10 shows the configuration of the transmitting section 16 of the third embodiment, and FIG. 11 shows the timing thereof.

The frequency and the like of the input digital video signal 151 and audio signal 152 are the same as in the second embodiment. The bus signal 19 includes 16-bit status parallel data C-DATA 15: 0 that the CPU 17 wants to send to the display / playback unit 21 via the transmission unit 16, and a timing signal STATUS when the CPU 17 validates the status data.

In FIG. 10, reference numeral 97 denotes a 16-bit D-FF (D
16-bit status parallel data C-DATA15: 0 from the CPU 17 with a type flip-flop
It is latched by a signal. The timing generator 93 is a circuit for generating timing, and after V-DE indicating the range of valid video data, generates a status transmission period, and further generates timing proportional to the count value. The status transmission period requires 1 V-CK, and the sum of this signal and the V-DE period is used as the Y1 output of the timing generator 93 (see FIG. 11 (j)). For example, the A-DE signal indicating the range of valid audio data generates a timing corresponding to 2 V-DE when the count value is 1, and a timing corresponding to 4 V-DE when the count value is 2, and sums this signal and the status transmission period period. To Y2 of the timing generator 93
Output (see FIG. 11 (k)). That is, video data is valid when Y1 of the timing generator 93 is high and Y2 is low, status data is valid when Y1 is high and Y2 is high, and audio data is valid when Y1 is low and Y2 is high.

An AND circuit 8 for taking the product of the A-DE signal and the V-CK signal
4 is used as a read clock of the FIFO 81. The switch SW95 is connected to Y1 and Y2 of the timing generator 93.
The input is switched by a signal. When Y1 is high and Y2 is low, the video data V-DATA is output. When Y1 is high and Y2 is high, the output of the D-FF 97, which is the status data, is output.
When Y2 is high, audio data AT-DATA is input. These data are GVIF-TX, which is a GVIF transmission chip.
36. Switch to 16 bits out of 24 bit video terminal, for example, 16 bits total for R and B signals
By connecting the output of the SW 95, the R and B signals indicate audio data when the audio data is valid, and indicate the status data when the status data is valid. the above
Due to the restrictions of the GVIF transmission chip, there is a restriction that the VSYNC / HSYNC signal and the control signal must not change within two video clocks. Audio data can be up to 2 frames or 2x
Since 2 = 4 video clocks and status data is 1 video clock, the front porch time needs to be set to 4 + 1 + 2 = 7 video clocks, that is, 0.3 μsec or more. As described above, the video signal and the audio signal can be multiplexed in a time-division manner, converted to a GVIF signal, and transmitted.

The receiving unit 22 also separates the video, status, and audio data by the combination of the CNTL and DF outputs of the GVIF chip, so that the video signal, the status signal, and the audio signal are time-divided in the same configuration as in the second embodiment. The multiplexed signal, which is further converted and transmitted to a GVIF signal, can also be separated and demodulated into the original video signal, status signal, and audio signal.

<Fourth Embodiment> FIG. 13 shows the overall configuration of a system to which the fourth embodiment is applied. In the figure, reference numeral 41 denotes a GVI which converts an analog video signal 451 from the video camera 42 and an analog audio signal 452 from the microphone 33 into digital signals by the transmission unit 45, multiplexes the video and audio in a time division manner, and
The signal is further multiplexed by the F transmission chip and sent to the display / playback unit 21 via a pair of differential GVIF cables. Display / playback unit 21
Has the same configuration as the first embodiment.

FIG. 14 is a block diagram of the transmitting unit 45, and FIG.
2 shows a timing chart, and the operation will be described below.

In FIG. 14, based on a crystal oscillator 50 of 24.576 MHz, an oscillator 53 has a video clock V-CK signal of 24.576 MHz, an audio clock V-CK signal having a frequency of 1/8 of 3.072 MHz, HSYNC with a high period of 32 v-ck at a frequency of 48KHz (512 V-CK period) that is 1/64 of the audio clock
The signal oscillates four types of synchronized frequencies of the ENA signal, a write permission period to the FIFO 54 having a period of 256 V-CK from the rising of the HSYNC signal.

A / D converter 51 which receives a stereo analog audio signal 452 and converts it into analog / digital
Samples the analog audio signal 452 at the rising edge of the 48 KHz HSYNC signal from the oscillator 53, and outputs 16-bit left and right serial digital audio data converted in synchronization with the A-CK signal (see FIG. 12C). ). FIFO5
No. 4 writes the serial digital audio data during the write enable period ENA using the A-CK signal as a write clock. That is, one frame of audio data synchronized with one horizontal synchronizing signal takes half the time of one horizontal synchronizing period.
4 will be written.

The A / D converter 52, which receives the analog video signal 451 and converts the digital video into an analog-to-digital signal, has a resolution of 384 pixels and converts the digitally-converted video signal into a signal of 384 V-CK after 64 V-CK from the rising edge of the HSYNC signal.
B: Output as an 8-bit V-DATA signal. At this time, a V-DE signal indicating the range of effective video data is output at the same timing, and a vertical synchronization signal VSYNC is output. As shown in FIG. 12 (f), the timing generator 55 indicates the range of valid audio data for 32 V-CK period from the fall of the V-DE signal.
Output DE signal. AN that takes the product of this signal and the V-CK signal
Assuming that the output of the D circuit 56 is the read clock of the FIFO 54, a read clock corresponding to one frame written to the FIFO 4 is generated during the range of the valid audio data, and the speed is converted from the original sampling clock to the video clock. The audio data AT-DATA is sequentially read out bit by bit in a format. 1.3 μs for reading one frame
ec takes. The switch SW57 switches to the audio data AT-DATA instead of the video data R0 only while the A-DE signal indicating the range of the valid audio data is high. These data are GVI
The signal is input to GVIF-TX58, which is the transmitting chip of F. Signals corresponding to the oscillator 54 and the A / D converter 52 are input to respective input terminals of the horizontal / vertical synchronization signal, the video enable signal, and the video clock signal of the chip. An A-DE signal indicating the range of valid audio data is connected to the control signal terminal CNTL.
ts, for example, switch SW to the least significant bit R0 of the R signal.
By connecting the outputs 57, this R0 signal indicates the audio data during the period in which the audio data is valid. As described above, when the audio sampling frequency and the horizontal synchronization frequency are equal and synchronized, the video signal and the audio signal can be multiplexed in a time division manner, converted to a GVIF signal, and transmitted.

In the display / reproducing section 21 to which a video signal and an audio signal are multiplexed and sent, these signals are separated and displayed / reproduced as in the first embodiment.

<Fifth Embodiment> Similar to the fourth embodiment, another example is considered in the system shown in FIG. For example, assume that the sampling clock of audio is 44.1 KHz. On the other hand, the vertical frequency of the video is 60 Hz and the total horizontal resolution is 122
Assuming five lines, the horizontal frequency is 73.5 KHz, which is 5/3 times the audio sampling clock. The horizontal frequency changes 5 times every 3 audio sampling clocks,
These signals may change synchronously and simultaneously.

A block diagram of the transmitting unit 45 shown in FIG.
The operation will be described with reference to the timing chart of FIG. It is assumed that the oscillator 123 of FIG. 16 oscillates an audio sampling clock SAMP signal of 44.1 KH and a video clock V-CK signal based on the oscillator 124. The PLL 126 receives the SAMP signal and converts it to 5
PLL oscillation of the horizontal synchronous HSYNC signal of 73.5KHz which is multiplied by / 3 times. When the rising of the SAMP signal and the rising edge of the HSYNC signal match,
A TART signal is output (see FIG. 15 (b)). The A / D converter 121 that inputs the analog audio signal 452 and converts the analog audio signal into a digital signal, samples the analog audio signal 452 at the rising edge of the 44.1 KHz SAMP signal from the oscillator 123, and outputs it as 16-bit digital data. This timing and data are represented by black circles A11 and A12 in FIG.
The results are shown in A13 and A21.

The correction circuit 125 receives the audio data, performs the following calculation from the SAMP, HSYNC, and START signals, and outputs the result as complementary data V11, V12,..., V15. 1) At the rising edge of the START signal, the audio sampling and the rising edge of the horizontal synchronizing signal overlap with each other, so this complementary audio data V11 = A11. 2) The following four complementary audio data are complemented from the two audio sampled data in consideration of the reciprocal of the temporal distance which is a correlation. That is, the complementary data V12 is at a distance of 6 from the sampling data A11 and at a distance of 4 from the sampling data A12. Therefore, the reciprocals thereof are used as coefficients, and V12 = 0.4 × A11 + 0.6 × A12. V14 = 0.2 × A12 + 0.8 × A13 V15 = 0.6 × A13 + 0.4 × A21 This is shown in FIG. 15E, and the output of the correction circuit 125 is as shown in FIG.

The A / D converter 122, which receives the analog video signal 451 and converts the analog to digital signal, outputs the digitally converted video signal as a V-DATA signal. At this time, a V-DE signal indicating the range of effective video data is output at the same timing, and a vertical synchronization signal VSYNC is output. The timing generator 127 outputs an A-DE signal indicating the range of valid data from the fall of the V-DE signal as shown in FIG. 128 inputs the output of the correction circuit 125 and latches at the rising edge of the A-DE signal indicating the range of valid data.
Bit D-FF. 16 bits out of 24 bits of the digitally converted video V-DATA signal of the A / D converter 122,
For example, a total of 16 bits of video data of R and B signals and D-
The audio data of the FF128 is input to the switch SW129, and is switched to the audio data instead of the video data R7: 0 and G7: 0 only while the A-DE signal indicating the valid audio data range is high. These data are input to a GVIF-TX58 which is a GVIF transmission chip. Signals corresponding to the oscillator 123 and the A / D converter 122 are input to respective input terminals of the horizontal / vertical synchronization signal, the video enable signal, and the video clock signal of this chip. An A-DE signal indicating the range of valid audio data is connected to the control signal terminal CNTL. The audio data is resampled to the same frequency as the horizontal synchronization signal, and the video data and the audio data are time-division multiplexed and transmitted by the GVIF method.

FIG. 17 is a block diagram of the receiving section 21. As shown in FIG.
Since the audio signal is sampled at 73.5 KHz, which is the same as the horizontal synchronization frequency, the data input of the D / A converter 131 is connected to the data output of the GVIF receiving chip 62, and the data input and sampled for each data valid audio data range is converted to an analog signal. By converting and outputting, an analog audio signal can be obtained.

As described above, when the audio sampling frequency and the horizontal synchronization frequency are integral multiples, the video signal and the audio signal are multiplexed in a time division manner, converted to a GVIF signal, transmitted, and separated / reproduced by a simple circuit. Things are possible.

Further, in the first embodiment, audio data and video data can be encoded with a simple configuration, transmitted through a pair of cables, demodulated, and the number of signal lines can be reduced to a minimum of one pair. .

Further, the second embodiment has an advantage that the transmission period can be shortened by transmitting the audio data in parallel.

The third embodiment has the effect of transmitting status data in addition to audio / video data via a pair of cables.

In the fourth embodiment, when the audio sampling frequency and the horizontal synchronizing frequency are equal and synchronized, the video signal and the audio signal can be multiplexed and transmitted in a simple circuit by time division.

In the fifth embodiment, when the audio sampling frequency and the horizontal synchronization frequency are integral multiples, the video signal and the audio signal are multiplexed in a time division manner, converted into a GVIF signal, transmitted, and separated by a simple circuit. -There is an effect that it is possible to reproduce.

[0052]

As described above, according to the present invention, when digital audio data and digital video data are multiplexed and transmitted, a gate signal indicating a period during which the audio data is valid is set at a predetermined timing during the horizontal blank period. , The encoding / demodulation circuit can have a simple configuration.

[Brief description of the drawings]

FIG. 1 is a diagram showing an operation timing chart of an apparatus according to a first embodiment.

FIG. 2 is a block diagram illustrating an overall configuration of the device according to the first embodiment.

FIG. 3 is a block diagram of a transmission unit according to the first embodiment.

FIG. 4 is a diagram illustrating an operation timing chart of a transmission unit according to the first embodiment.

FIG. 5 is a diagram illustrating an operation timing chart of a transmission unit according to the first embodiment.

FIG. 6 is a block diagram of a receiving unit according to the first embodiment.

FIG. 7 is an operation timing chart of the receiving unit of the first embodiment.

FIG. 8 is a block diagram of a transmission unit according to the second embodiment.

FIG. 9 is a diagram illustrating an operation timing chart of a transmission unit according to the second embodiment.

FIG. 10 is a block diagram of a transmission unit according to the third embodiment.

FIG. 11 is a diagram illustrating an operation timing chart of a transmission unit according to the third embodiment.

FIG. 12 is a diagram illustrating an operation timing chart of a transmission unit according to the fourth embodiment.

FIG. 13 is an overall block configuration diagram of an apparatus according to a fourth embodiment.

FIG. 14 is a block diagram of a transmission unit according to a fourth embodiment.

FIG. 15 is a diagram illustrating an operation timing chart of a transmission unit according to the fifth embodiment.

FIG. 16 is a block diagram of a transmission unit according to a fifth embodiment.

FIG. 17 is a block diagram of a receiving unit according to a fifth embodiment.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 7/085 7/10 F-term (Reference) 5C025 AA08 AA09 AA10 BA01 BA25 BA28 DA01 5C063 AB07 AB09 AC01 AC05 CA14 CA20 DA05 DA07 DA13 DB07 5C064 AC06 AD07 BA02 BB05 BC10 BC20 BD08 BD09 BD14

Claims (9)

[Claims] 1. A video transmission apparatus with sound for multiplexing digital audio data with a digital video signal and transmitting the multiplexed digital audio data, comprising: a buffer memory for storing digital audio data input in time series; A gate signal generating means for generating a gate signal having a time length corresponding to the amount of digital audio data stored in the buffer memory and synchronized with a carrier clock of digital video data at a predetermined timing during the period; After transmitting digital video signals for
Transmitting means for transmitting the digital audio data stored in the buffer memory within the section of the gate signal together with the gate signal in synchronization with a carrier clock of the digital video data. Transmission equipment. 2. The video transmission apparatus with sound according to claim 1, wherein said transmission means performs transmission using a GVIF transmission chip. 3. The sound-equipped audio device according to claim 1, wherein the gate signal generating means generates a gate signal having a time length in units of a frame of the audio data stored in the buffer memory. Video transmission device. 4. The video transmission apparatus with sound according to claim 1, wherein the predetermined timing is immediately after a video data valid section between one horizontal synchronization signal. 5. The digital audio data includes the GVI
2. The video transmission apparatus with sound according to claim 1, wherein the transmission is performed using a predetermined 1-bit signal line of the digital video data of the F transmission chip. 6. The digital audio data includes a GVI
2. The digital video data of the F transmission chip is transmitted using a signal line of a plurality of bits.
The video transmission device with sound according to Item. 7. The video transmission apparatus with sound according to claim 1, wherein said transmission means further transmits a predetermined status signal. 8. The transmission means transmits in a time division manner when a frequency of a signal at the time of inputting the audio data and a horizontal synchronization signal of an image are integral multiples. 2. The video transmission device with sound according to claim 1. 9. A video reproducing apparatus with sound for receiving and reproducing a signal from the video transmitting apparatus with sound according to claim 1, comprising: receiving a transmitted signal; A video signal, and receiving means for separating the control signal; and in a horizontal blank period of the video signal, data in a section of the gate signal obtained from the control signal is assumed to be acoustic data, and is synchronized with a carrier clock of the transmission. Audio data extracting means for extracting audio data by using the audio data extracting means, and outputting the audio data extracted by the audio data extracting means in accordance with the reproduction speed of the audio data. .