JP3496647B2 - Time information distribution method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time information distribution system, and more particularly to a time information distribution system for realizing system reference time coincidence for synchronizing a plurality of encoders and decoders in MPEG2 digital broadcasting. .

[0002]

2. Description of the Related Art Recent digital broadcasting in Japan is currently in a form of multiplexing and broadcasting a plurality of time-series information including video, audio, or various data streams.

Generally, the time-series information is multiplexed by MPEG2 (Mo, which is an international standard system suitable for broadcasting and communication media).
Ving Picture Experts Grou
p), and this MPEG2 is defined by ISO / IEC13818-1 which is an international standard. In digital broadcasting, the MPEG2 (ISO / IEC13818) system is usually adopted as a video encoding system. In the MPEG2 compression method, STC (System Time Clock) is used as a time management unit.
However, since there is no stipulation regarding synchronization of a plurality of encoders with respect to a device to which MPEG2 is applied, the relative time by STC is not managed unless special measures are taken.

Therefore, when the outputs of a plurality of encoders are switched, such a difference causes information discontinuity points, grammatical errors, prediction disagreement, etc. in the output codes after switching, so that the video material is decoded. Abnormality occurs in the result, and in the worst case, the decoded video signal is interrupted. In broadcasting stations and the like, switching of codes output from a plurality of encoders is frequently performed, such as switching between programs and CMs, and it is essential to solve these.

As an example of such a digital broadcasting synchronization technique, "Digital broadcasting time synchronization method, digital broadcasting transmission device, digital broadcasting reception device, digital broadcasting transmission / reception system, and digital broadcasting" disclosed in Japanese Patent Laid-Open No. 2000-4210. Data structure "is known.

[0006] In this publication, when transmitting multiplexed time series information, for an event such as a program including a portion on the time axis of the time series information, a reference time as an event reference and a plurality of times are set. Synchronize the presentation reference time and the event reference time on the receiving side of the multiplexed time series information by adding and transmitting the offset time information between the presentation reference time which is the reference for the presentation time synchronization between the series information. The technology to do this is described.

[0007]

In the above-mentioned conventional time information distribution system, relative time is not managed for synchronization of a plurality of encoders, and therefore information is not recorded after switching the outputs of a plurality of encoders. It has the drawback that continuous points, grammatical errors, prediction mismatches, etc. occur, and in the worst case, the decoded video signal is interrupted.

An object of the present invention is to make the system reference times coincide with each other in a plurality of encoders or decoders,
An object of the present invention is to provide a time information distribution system for synchronizing output codes after switching the outputs of a plurality of encoders.

[0009]

According to the time information distribution system of the present invention, various flags, system clocks, and MPEG (Moving Picture Expert) are used at the time of decoding.
ts Group) 2 data and enter STC (Sy
STC shift clock, STC data, STC load, and STC, which are information about the system time clock.
An STC information generation unit that outputs a counter clock pulse; and inputs the STC shift clock, the STC data, the STC load, and the STC counter clock to reproduce n (n is an integer) STC values that are synchronized, And n (n is an integer) STC reproducing units for outputting.

An STC information generation unit for inputting various flags and a system clock and MPEG2 data at the time of decoding, and outputting STC shift clock which is STC information, STC data, STC load and STC counter clock; the STC shift clock, A first STC reproducing unit and a second ST for reproducing the first STC value and the second STC value which are synchronized by inputting the STC data, the STC load and the STC counter clock, and outputting each of them.
It is characterized by having a C reproducing section and;

The frequencies of the system clock and the STC counter clock are 27 MHz.

The STC information generator generates a bit counter output of a total of 42 bits of upper 33 bits and lower 9 bits defined by MPEG2 according to the system clock, and the MPEG2 is decoded at the time of MPEG2 decoding.
PCR (Program Cloc) extracted from the data
The first 42-bit STC which modifies the value of the 42-bit bit counter output by k Reference) and uses the modified counter value as a new bit counter output.
A counter; the system clock, the MPEG2 data and the various flags are input, and a latch pulse, shift enable, the STC shift clock, the STC
A control unit for outputting a counter clock, the STC load, and the PCR; latching the bit counter output output by the first 42-bit STC counter with the latch pulse to output a latch output as an STC value that is valid data. A latch for outputting; an offset adding unit for adding a constant offset to the latch output and then outputting the offset added value output; and a serial STC for outputting the offset added value output by the shift enable and the STC shift clock. A first 64-bit shift register for outputting data;

The STC reproducing unit receives the ST
A second 64-bit shift register for storing C data for 64 clocks by the STC shift clock;
A differentiating circuit that differentiates the C load signal with the STC counter clock and outputs the differentiated load pulse;
At the rising edge of the differentiated load pulse, the second 6
A second 42-bit STC counter that loads 42 bits of the STC data output from the 4-bit shift register and outputs the STC information as the STC information by the STC counter clock.

The STC load is output from the STC information control unit as one clock of the STC shift clock, and the STC data is read by the first and second STC reproducing units at the timing of this STC load. And is reproduced as the synchronized first and second STC values.

Further, the STC load has the valid data part in which the STC information is included as a signal and the invalid data part in which no information is included as a signal.
It is characterized in that it represents the last 1 bit of the valid data portion for C data and is output each time the valid data portion is input.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the time information distribution system of the present invention.

In the present embodiment shown in FIG. 1, MPEG2 data 9, various flags 10 and system clock 3 are input and STC shift clocks 4 and ST which are STC information.
STC information generator 1 which outputs C data 5, STC load 6 and 27 MHz clock 7 as STC counter clock, and STC value 8 which is synchronized by inputting STC shift clock 4, STC data 5, STC load 6 and 27 MHz clock 7. And STC reproducing units 2 and 2a for reproducing the STC value 8a and outputting each.

Hereinafter, the STC counter clock is 27 MHz.
It is referred to as z clock 7.

Next, the operation will be described.

MPEG2 (Moving Picture)
e Experts Group) encoding, 27M
STC (System Time Clock) which is a system reference time based on the system clock 3 of Hz.
Encoding / decoding is performed using k). The STC information generation unit 1 uses the 27 MHz system clock 3 for STC information.
As information, the STC shift clock 4, STC data 5, and STC load 6 are generated and output.

Generally, there are a plurality of STC reproducing units 2 and 2a from 1 to n (n is a natural number), and they receive the STC shift clock 4, the STC data 5, and the STC load 6, respectively, and synchronize with each other. Each reproduces and outputs n STC values 8 and 8a.

Here, a case where n = 2 will be described.

The STC information generator 1 receives the MPEG2 input
For the data 9 and various flags 10, STC information is generated and output from the system clock 3 of 27 MHz. When decoding, MPEG2 TS (Transport St)
PCR (Program Clo) included in
ck Reference) is used to generate STC information (STC shift clock 4, STC data 5, STC load 6) to be transmitted to the STC reproducing units 2 and 2a. S
From the STC information (STC shift clock 4, STC data 5, STC load 6) received from the STC information generation unit 1, the TC reproduction units 2 and 2a synchronize the STC values 8 and 8a.
Will be played.

That is, STs of a plurality of STC reproducing units 2 and 2a
The C information can be synchronized.

FIG. 2 is a detailed block diagram showing an example of the STC information generator of FIG.

In FIG. 2, components corresponding to those shown in FIG. 1 are designated by the same reference numerals or symbols, and their description will be omitted.

The 42-bit STC counter 11 is 27M
PCR (Program) extracted from the MPEG2 data 9 when decoding the system clock 3 of Hz and MPEG2.
MP by mClock Reference) 21
A bit counter output 18 of 42 bits in total including upper 33 bits and lower 9 bits defined by EG2 is generated. 42-bit STC counter 1 by this PCR 21
The value of 1 is modified, and the modified counter value is used as a new bit counter output 18.

The control unit 12 controls the timing of outputting STC information. That is, the output of the STC information is controlled at the optimum timing for the system, and the latch pulse 19, shift enable 20, STC shift clock 4, 27 MH are controlled.
The z clock 7, STC load 6 and PCR 21 are output to control the timing of outputting valid data of STC information.

The shift enable 20 and the STC shift clock 4 are output to the 64-bit shift register 15. In response to this, the latch 13 outputs the bit counter output 18 of the 42-bit STC counter 11 to the latch pulse 1
It is latched by 9 and outputs a latch output 22 as an STC value which becomes valid data.

The offset adder 14 adds a fixed offset 23 to the latched latch output 22. After adding the offset 23, the offset addition unit 14 outputs the offset addition value 24 to the 64-bit shift register 15. The 64-bit shift register 15 outputs the offset addition output 24 to the shift enable 20 and the STC.
Serial conversion to STC data 5 with shift clock 4,
It is output to each of the STC reproducing units 2 and 2a. 64 here
Although it is a bit shift register, a shift register having a different number of bits is also possible.

Since the latch output 22 as the STC value is 42 bits, the remaining 22 bits are STC reproducing units 2 and 2a.
Various flags 10 that you want to transmit to STC data 5
Will be output.

FIG. 3 is a time chart showing the generated STC information.

The STC information is the STC shift clock 4, S
It consists of three signals, TC load 6 and STC data 5.
The STC load 6 represents the last 1 bit of the valid data portion 26 of the STC data 5, and is output every time the valid data portion 26 is input.

The valid data portion 26 is a portion that includes STC information as a signal, and the invalid data portion 27 is a portion that does not include any information as a signal. Invalid data is ST
Since the data is not related to C information, it is not used as STC data. The valid data is STC information data, and the optimum timing for the system (for example, video 1
It is output for each field and for each frame), and the other parts are invalid data.

In the case of FIG. 2, 64-bit shift register 1
5, the valid data portion 26 of STC data 5 is STC.
This corresponds to 64 clocks of the shift clock 4. This STC
The load 6 and the valid data section 26 are output at the optimum timing for the system.

The STC shift clock 4 is 27 MH.
It is set to an integral fraction of the system clock 3 of z, for example, 27/2 = 13.5 MHz. The STC load 6 corresponds to one clock of the STC shift clock 4 and the control unit 1
2 is output from the STC playback section 2 and 2a.
The STC data 5 is read at the timing of the C load 6, and the synchronized STC values 8 and 8a are reproduced.

FIG. 4 is a time chart showing the effective data part of FIG.

In this example, the effective data is 64 bits. The top 3 STCs in the time slots S41 to S09
The upper 9 bits of the STC are transmitted in a 3-bit time slot of S08 to S00. In addition to 42 bits of STC information, various flags can be transmitted.
For example, when the STC load 6 is output for each video field, the odd / even information of each field can be superimposed.

The offset addition value 24 which is the output of the offset addition unit 14 in FIG. 2 becomes S41 to S00 in FIG. Various flags and reserve bits are added to this, and 64 bits are serially converted by the 64-bit shift register 15 to form the effective data portion 26 of the STC data 5. That is, in this case, the effective data is 64 bits.

If the length of valid data is 42 bits or more, STC information can be represented. STC playback unit 2,
If there is information to be sent at the same time as STC information in 2a, various flags 10 are used for the prepared 16 bits.

Further, in the case where 16 bits of various flags are insufficient, or when it is desired to send other user information or the like, the reserved bits (R0 to R5) are 6 bits (6 bits are the whole). 61 bits,
I use this because it is prepared (just because it is good to cut).

The STC load 6 is designed to output the STC data 5 at the same time as the last bit of the valid data portion 26. This is the ST of the 64-bit shift register 15 when the STC load 6 rises in the STC reproducing units 2 and 2a.
This is because when the C data 5 is loaded, the STC data 5 can be loaded as it is.

FIG. 5 is a detailed block diagram showing an example of the STC reproducing section of FIG.

In FIG. 5, components corresponding to those shown in FIG. 1 are designated by the same reference numerals or symbols, and their description will be omitted.

The 64-bit shift register 28 stores the input STC data 5 for 64 clocks with the STC shift clock 4. The 42-bit STC counter 29
Counting up with a 27 MHz clock 7, the STC values 8 and 8a in the STC reproducing units 2 and 2a are shown. The signal of the STC load 6 is differentiated by the differentiating circuit 30 by the 27 MHz clock 7 to have a width of 1 clock of the 27 MHz clock 7, and 64 is generated at the rising edge of the differentiated load pulse 31.
42 bits of STC data 5 output from the bit shift register 28 are loaded into a 42-bit STC counter 29 and output as an STC value 8.

FIG. 6 is a time chart showing the operation of the STC reproducing section.

The transmitted STC data 5 is loaded into the STC value which is being counted up by the 27 MHz clock 7. The STC of this 42-bit STC counter 29
Use the value on the playback side.

With this configuration, a plurality of STCs are
The STC values 8 and 8a of the reproducing units 2 and 2a can be synchronized.

The number of bits of valid data in the STC information, the contents of various flags 10, the interval between STC loads 6,
The frequency of the STC shift clock 4 is arbitrary.

The present method can be applied to the distribution of STC information for both the encoding system and the decoding system.

As described above, in the time distribution system of this system, STC (System Time Clock) is used.
Information is distributed as three STC information signals, and a plurality of S
By reproducing this STC information signal, the TC reproducing unit can realize the coincidence of the system reference times of a plurality of STC reproducing units and can synchronize them.

When performing MPEG2 encoding, if there are a plurality of substrates in one device, for example, if there is an audio encoding unit and a video encoding unit, in order to make the STC information match in each encoding unit, The STC information is distributed as clock, load, and data, and the PCR and PTS are embedded in the TS, which is a time slot, based on the STC information reproduced on each board.

Even when the decoding is performed, the STC is reproduced from the PCR and PTS embedded in the TS, and the reproduced S is reproduced.
The TC is distributed to the audio decoding unit and the video decoding unit, and the STC
Is used as a reference time for decoding. This makes it possible to match the decoding times of audio and video.

The time information distribution method according to this method is
Since it does not adversely affect the system of the video signal synchronization system in the office which is widely used at present, even if the synchronization generator and the distributor are replaced, the conventional devices such as the VTR and the frame synchronizer can be used together. It excels in the compatibility between the conventional baseband system and the new MPEG compression system.

[0056]

As described above, according to the time information distribution method of the present invention, a plurality of encoding units / decoding units can match the system reference time, which is a time management unit, so that a plurality of reproductions can be performed. This has the effect of synchronizing the system reference times of the departments.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a time information distribution system of the present invention.

FIG. 2 is a detailed block diagram showing an example of an STC information generation unit in FIG.

FIG. 3 is a time chart showing generated STC information.

FIG. 4 is a time chart showing an effective data part of FIG.

5 is a detailed block diagram showing an example of the STC reproducing unit in FIG. 1. FIG.

FIG. 6 is a time chart showing the operation of the STC reproducing unit.

[Explanation of symbols]

1 STC information generator 2,2a STC playback unit 3 system clock 4 STC shift clock 5 STC data 6 STC Road 7 27MHz clock 8,8a STC value 9 MPEG2 data 10 Various flags 11 42-bit STC counter 12 Control unit 13 Latch 14 Offset addition section 15 64-bit shift register 18-bit counter output 19 Latch pulse 20 shift enable 21 PCR 22 Latch output 23 offset 24 Offset addition value 26 Effective data section 27 Invalid data section 28 64-bit shift register 29 42-bit STC counter 30 Differentiation circuit 31 load pulse

Continuation of the front page (56) References JP 2000-4443 (JP, A) JP 11-355263 (JP, A) JP 11-215144 (JP, A) JP 2000-4210 (JP, A) ) JP 2002-204427 (JP, A) JP 2002-199396 (JP, A) JP 2001-1003026 (JP, A) JP 11-187396 (JP, A) JP 11-154923 (JP , A) JP-A-11-27668 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/00 H04N 7/08 H04N 7/081 H04N 7/24

Claims (7)

(57) [Claims] 1. Various flags, system clocks, and MPEG (Moving Picture E) at the time of decoding.
xperts Group) 2 data and enter
An STC information generation unit that outputs an STC shift clock, STC data, an STC load, and an STC counter clock that are C (System Time Clock) information; an input of the STC shift clock, the STC data, the STC load, and the STC counter clock And n (n is an integer) STC reproducing units for reproducing n (n is an integer) STC values synchronized with each other and outputting the STC values. 2. An STC information generation unit which inputs various flags and a system clock and MPEG2 data at the time of decoding, and outputs STC shift clock, STC data, STC load and STC counter clock which are STC information; and the STC shift. Clock, STC data,
A first STC value and a second STC that are synchronized by inputting the STC load and the STC counter clock pulse
A time information distribution system, comprising: a first STC reproducing unit and a second STC reproducing unit for reproducing values and outputting each. 3. The time information distribution system according to claim 1, wherein the frequencies of the system clock and the STC counter clock are 27 MHz. 4. The STC information generation unit generates a bit counter output of a total of 42 bits of upper 33 bits and lower 9 bits defined by MPEG2 according to the system clock, and from the MPEG2 data at the time of decoding MPEG2. Extracted PCR (Progr
am Clock Reference) corrects the value of the 42-bit bit counter output, and uses the corrected counter value as a new bit counter output.
A 2-bit STC counter; a control unit which inputs the system clock, the MPEG2 data and the various flags, and outputs a latch pulse, a shift enable, the STC shift clock, the STC counter clock, the STC load and the PCR; The bit counter output output from the first 42-bit STC counter is latched by the latch pulse, and becomes S as valid data.
A latch that outputs a latch output as a TC value; an offset adder that adds a constant offset to the latch output and then outputs the offset added value output;
The time information according to claim 1, 2 or 3, further comprising: a first 64-bit shift register that outputs the offset addition value output as serial STC data according to the shift enable and the STC shift clock. Distribution system. 5. The STC reproduction unit stores a second 64-bit shift register that stores the input STC data for 64 clocks by the STC shift clock; and differentiates the signal of the STC load by the STC counter clock. A differentiating circuit for outputting the differentiated load pulse; 42 bits of the STC data output by the second 64-bit shift register is loaded at the rising edge of the differentiated load pulse, and the STC is loaded.
The second 42-bit STC counter which outputs as the STC information according to a counter clock; and the time information distribution system according to claim 1, 2 or 3. 6. The STC load is output from the STC information control unit as one clock of the STC shift clock, and the STC data is synchronized with the timing of the STC load by the first and second STC reproducing units. 3. The time information distribution method according to claim 2, wherein the time information distribution method is read by, and reproduced as the synchronized first and second STC values. 7. The STC load has the last part of the valid data part with respect to the STC data having a valid data part including the STC information as a signal and an invalid data part not including any information as a signal. 3. The time information distribution system according to claim 1, wherein the time information distribution system represents one bit and is output each time the valid data section is input.