JP2002015527A - Clock generator, and recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To selectively obtain a clock synchronized with reference clock information contained in digital data and a clock of a fixed frequency using a single oscillator. SOLUTION: When a MPEG2-TS from a digital broadcasting tuner is inputted and recorded) on a recording and reproducing device 10, a clock-generating part 90 generates a PLL to obtain the clock synchronized with a PCR included in the MPEG2-TS. The output value of a counter 47 is added to each packet as arrival time information on the packet in the arrival time addition circuit 48, and the MPEG2-TS is recorded on a disk 61. At reproduction, the clock of a fixed frequency of 27 MHz is obtained from a VCXO 91. Arrival time information added to the first packet of the reproduced MPEG2-TS is loaded to the counter 47, and when the output value of the counter 47 matches value of arrival time information added to packets after the second packet, the packets are outputted to the digital broadcasting tuner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus for generating a clock for processing digital data such as an encoded bit stream, and an apparatus for recording and reproducing digital data such as an encoded bit stream.

[0002]

2. Description of the Related Art In digital broadcasting, video, audio, etc.
MPEG (Moving Picture Explorer)
ts Group) and broadcasted by a satellite communication network or the like, and the receiving side decodes the encoded bit stream in real time,
Further, by being converted into an analog signal and output to the monitor output device, the viewer can view video and audio.

[0003] A digital broadcast receiver or a digital broadcast tuner includes a PCR (Program Clock Reference) included in a received encoded bit stream.
ns) synchronized with reference time information such as 27M
A clock generation device for generating a clock of Hz is implemented, whereby a clock having the same phase as that of the transmission side is generated on the reception side, and when decoding the encoded data, a buffer for temporarily storing the encoded data is provided. Encoded data can be decoded without causing overflow or underflow, and even during long-time reception, video and audio can be viewed without disturbance of video and audio.

[0004]

With the full-scale use of digital broadcasting, an encoded bit stream received by a digital broadcast receiver or a digital broadcast tuner is input to a digital recording / reproducing apparatus and recorded on a recording medium. It is considered that a recorded encoded bit stream is reproduced from a recording medium, output to a digital broadcast receiver or a digital broadcast tuner, and decoded by the digital broadcast receiver or the digital broadcast tuner to obtain a reproduced output. .

In such a recording / reproducing apparatus, the clock generating apparatus as described above is mounted, and at the time of recording, the clock generating apparatus transmits the reference time information included in the encoded bit stream input to the recording / reproducing apparatus. It is necessary to obtain a synchronized clock and supply it to the coded bit stream processing circuit.

However, as described above, the clock generator of the recording / reproducing apparatus can obtain a clock synchronized with the reference time information included in the encoded bit stream, similarly to the clock generator of the digital broadcast receiver or the digital broadcast tuner. In the case of the PLL (Phase Locked Loop) configuration, at the time of reproduction, since the reference time information does not exist in the encoded bit stream reproduced from the recording medium, an appropriate clock cannot be obtained from the clock generation unit having the PLL configuration. Unless an oscillator for generating a clock is provided separately for data processing during reproduction, it will not be possible to process the encoded bit stream reproduced from the recording medium and output it to the digital broadcast receiver or digital broadcast tuner. Will be.

Accordingly, the present invention provides a clock synchronized with reference time information included in digital data for recording digital data, and a fixed-frequency clock used for reproducing digital data, using one oscillator. Are selectively obtained.

[0008]

According to the present invention, there is provided a clock generating apparatus comprising: an oscillator whose oscillation frequency changes in accordance with a control value; a counter for counting a clock from the oscillator;
Extracting means for extracting reference time information from digital data including reference time information; comparing means for calculating a difference value between the value of the extracted reference time information and the output value of the counter; and the calculated difference value Calculating means for calculating a control value supplied to the oscillator from the control means, wherein the calculating means is controlled by a mode switching signal from the control means, and a value calculated from the difference value as the control value is supplied to the oscillator. A synchronous mode in which a clock synchronized with the reference time information is obtained from the oscillator, and a fixed mode in which a fixed frequency clock is obtained from the oscillator by supplying a fixed value as the control value to the oscillator. It can be switched to any one of

According to the clock generation device having the above configuration,
For example, when a coded bit stream of a digital broadcast is input from a digital broadcast tuner to a recording / reproducing apparatus and recorded, the system controller of the recording / reproducing apparatus uses a mode switching signal to operate the arithmetic means of the clock generating apparatus as a control value and to output reference time information as a control value. The clock generation device forms a PLL by switching to supply a value based on the difference between the value of the counter and the output value of the counter to the oscillator. On the other hand, when the encoded bit stream is reproduced from the recording medium and output from the recording / reproducing apparatus to the digital broadcast tuner, the system controller of the recording / reproducing apparatus uses the mode switching signal to operate the arithmetic means of the clock generating apparatus. A fixed value to the oscillator as the control value. By switching to a clock generating apparatus without forming the PLL, clock fixed frequency is obtained from the oscillator.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Outline of Recording / Reproducing Apparatus ... FIG. 1] FIG. 1 shows an example of a recording / reproducing apparatus according to the present invention, in which video and audio are compression-encoded in accordance with the MPEG2 standard.
Multiplexing according to the PEG2 system standard
-As TS (Transport Stream),
This is a case where data is recorded on a disk (hard disk) in an HDD (Hard Disk Drive) and reproduced from the disk.

Hereinafter, the analog video signal and the analog audio signal are referred to as a video signal and an audio signal, respectively.
The digital video signal and digital audio signal are referred to as digital video data and digital audio data, or simply video data and audio data. “Interface” is abbreviated as “I / F”.

In this example, the recording / reproducing apparatus 10 is connected to an antenna 1 for receiving a terrestrial analog television broadcast,
Analog input terminals 11V, 11A, 11S, analog output terminals 12V, 12A, 12S, digital input / output terminal 1
5, digital I / F circuit 17, input processing unit 20, output processing unit 30, demultiplexing processing unit 40, buffer control circuit 5
0, an HDD 60, a system controller 70, and a synchronization control circuit 80. The demultiplexing processing unit 40 includes a multiplexing circuit 41 and a demultiplexing circuit 42.

Although omitted from the drawing, the system controller 70 is a CPU (Central Processing).
Unit), ROM (Read Only) in which a program to be executed by the CPU and fixed data are written.
Memory) and a RAM (Random Access Mem) functioning as a work area of the CPU and the like.
or the like, and controls the entire recording / reproducing apparatus 10.

(Analog Input Processing and Recording) The terrestrial analog television broadcast received by the antenna 1 is tuned by the terrestrial tuner 21 to obtain a video signal and an audio signal from the terrestrial tuner 21. And an audio signal are supplied to one input terminal of the input switching circuit 22.

A composite video signal is supplied from an external device to the input terminal 11V, an audio signal is supplied from the external device to the input terminal 11A, and a separate video signal is supplied from the external device to the input terminal 11S.

The composite video signal from the input terminal 11V and the audio signal from the input terminal 11A are supplied to the other input terminal of the input switching circuit 22,
Is switched by the system controller 70,
One of the video signal and the audio signal is selected and taken out from the input switching circuit 22.

The video signal from the input switching circuit 22 is YC
The signal is separated into a luminance signal and a color difference signal by a separating circuit 23 and supplied to one input terminal of another input switching circuit 24. Also,
A separate video signal (luminance signal and color difference signal) from the input terminal 11S is supplied to the other input terminal of the input switching circuit 24, and the input switching circuit 24
0, and any one of the luminance signal and the color difference signal is selected and taken out from the input switching circuit 24.

The luminance signal and the color difference signal from the input switching circuit 24 are output from an NTSC (National Televi).
The A / D conversion is performed by the S / N system decoder 25, and the image data is further subjected to chroma-encoding processing to obtain component video data from the NTSC decoder 25.

The NTSC decoder 25 separates a vertical synchronizing signal and a horizontal synchronizing signal from the luminance signal from the input switching circuit 24, and generates a clock and a field discrimination signal based on the separated synchronizing signal. The synchronization signal, the clock, and the field discrimination signal are supplied to the synchronization control circuit 80. In the synchronization control circuit 80, the recording / reproducing device 10
A clock and a timing signal required for each section are generated and supplied to each section of the recording / reproducing apparatus 10.

The video data from the NTSC decoder 25 is subjected to video processing such as pre-filtering by a pre-video processing circuit 26, and then supplied to an MPEG video encoder 27 and a post-video processing circuit 32 of an output processing unit 30. .

In the MPEG video encoder 27, the video data from the pre-video processing circuit 26
T (Discrete Cosine Transfo
rm), and the video ES (Ele
mental stream) is generated and its MP
The EG video ES is supplied to the demultiplexing processing unit 40.

On the other hand, the audio signal from the input switching circuit 22 is converted into digital audio data by the audio A / D converter 28, and then supplied to the MPEG audio encoder 29 and the output switching circuit 35 of the output processing unit 30. .

In the MPEG audio encoder 29, the audio A
The audio data from the / D converter 28 is compressed according to the MPEG format to generate an audio ES, and the MP
The EG sound ES is supplied to the demultiplexing processing unit 40.

The demultiplexing processing section 40 includes a multiplexing circuit 41
, The video ES from the MPEG video encoder 27
The audio ES from the MPEG audio encoder 29 and the various control signals are multiplexed, and the T
S is generated, and the MPEG2-TS is sent to the buffer control circuit 50.

The buffer control circuit 50 includes a multiplexing circuit 41
MPEG2-TS continuously input from the HDD 6
Transmitted intermittently to zero. That is, when the HDD 60 is performing a seek operation, writing cannot be performed.
The input MPEG2-TS is temporarily stored in a buffer,
When the DD60 is writable, the MPEG2-T
S is read from the buffer at a rate higher than the input rate and sent to the HDD 60. Thus, the MPEG2-TS continuously input to the buffer control circuit 50 is recorded on the disk (hard disk) 61 without interruption.

The HDD 60 includes a system controller 70
Controlled by the MPEG2-TS
Write. As a protocol (I / F) between the buffer control circuit 50 and the HDD 60, IDE (Integ)
rate DeviceElectronics) is used.

(Reproduction and Analog Output Processing) During reproduction, the HDD 60 is controlled by the system controller 70 to read the MPEG2-TS from the disk 61 and send it to the buffer control circuit 50. The buffer control circuit 50 converts the MPEG2-TS intermittently input from the HDD 60 into a continuous MPEG2-TS
The signal is converted into a TS and supplied to the demultiplexing circuit 42 of the demultiplexing processing unit 40.

In the separation circuit 42, the continuous MPEG
By analyzing the header of the 2-TS, the MP
EG2-TS to PES (Packetized El)
elementary stream) is separated into MP
It is supplied to the EG video / audio decoder 31.

In the MPEG video / audio decoder 31, the PES from the separation circuit 42 is separated into a video ES and an audio ES, and the video ES is decoded by an MPEG video decoder and converted into baseband video data.
S is decoded by the MPEG audio decoder and converted into baseband audio data. The converted video data is supplied to a post video processing circuit 32, and the audio data is supplied to an output switching circuit 35.

In the post video processing circuit 32, video processing such as switching or combination of the two or post filtering is performed on the video data from the MPEG video / audio decoder 31 and the video data from the pre-video processing circuit 26. The video data after the processing is OSD (On Sc)
(replay) processing circuit 33.

In the OSD processing circuit 33, a process is performed on the video data from the post video processing circuit 32 so that an image such as graphics is superimposed or partially displayed on the display screen. The data is supplied to the NTSC encoder 34.

In the NTSC encoder 34, the video data (component video data) from the OSD processing circuit 33 is converted into luminance data and chrominance data, and the luminance data and chrominance data are respectively converted to D / D data.
The signal is A-converted to obtain a composite video signal and a separate video signal of an analog signal. The composite video signal is led to the output terminal 12V, and the separate video signal is led to the output terminal 12S.

On the other hand, in the output switching circuit 35, the MPEG video / audio decoder 3 is controlled by the system controller 70.
1 and the audio data from the audio A / D converter 28 are selected and taken out. The selected audio data is converted into an analog audio signal by the audio D / A converter 36, and is output to the output terminal 12A.

(Outline of I / F with External Device) The recording / reproducing device 10 includes a digital input / output terminal 15 and a demultiplexing processing unit 4.
0 via the bidirectional buses 16 and 18
By connecting the external device 110 to the digital input / output terminal 15 assuming that the F circuit 17 is connected, the encoded video / audio data input from the external device 110 is recorded on the disk 61, Can be output to the external device 110.

As the external device 110, an IRD (Int
It is possible to connect a device such as an eGraded ReceiverDecoder or a personal computer. The digital I / F between the external device 110 and the recording / reproducing device 10 is an IEEE (Institute of
Electronic and Electroni
(cs Engineers) 1394 standard I / F or the like can be used.

Digital input / output terminal 1 from external device 110
5 is subjected to processing such as format conversion by the digital I / F circuit 17, and is converted into MPEG2-TS suitable for the recording / reproducing apparatus 10; 40. The demultiplexing unit 40 analyzes and generates control signals as necessary, sends the MPEG2-TS to the buffer control circuit 50, and sends the MPEG2-TS to the disk 6 by the HDD 60.
1 is recorded.

At the same time, the separation circuit 42 separates the PES from the recorded MPEG2-TS,
By being supplied to the video / audio decoder 31, an analog video signal and an analog audio signal based on the video / audio data from the external device 110 can be obtained at the output terminals 12V, 12S, and 12A.

At the time of reproduction, the MPEG2-TS is read from the disk 61 by the HDD 60, converted into a continuous MPEG2-TS by the buffer control circuit 50, and sent to the demultiplexing processing section 40. The multiplexing / demultiplexing unit 40 analyzes and generates a control signal as necessary, and sends the MPEG2-TS to the digital I / F circuit 17. In the digital I / F circuit 17, the MPEG2-TS is converted to the external device 1 by a process reverse to that at the time of recording.
The data is converted into video and audio data that conforms to 10 and output to the external device 110 via the digital input / output terminal 15.

At the same time, the PES is separated from the reproduced MPEG2-TS by the separation circuit 42,
By being supplied to the video / audio decoder 31, a reproduced analog video signal and a reproduced analog audio signal can be obtained at the output terminals 12V, 12S and 12A.

[Recording and Reproduction of Encoded Data of Digital Broadcasting and Clock Generation ... FIGS. 2 to 4] In the recording and reproducing apparatus 10 as described above, a digital broadcast tuner is connected as the external device 110 and received by the digital broadcast tuner. A clock generation method and a data processing method in the case where the encoded bit stream obtained as described above is input to the recording / reproducing apparatus 10 and recorded on the disk 61, and the encoded bit stream reproduced from the disk 61 is output to a digital broadcast tuner are described below. .

(System Configuration--FIG. 2) FIG. 2 shows an example of a system configuration in this case. In this example, information such as video and audio of a plurality of programs is transmitted from a broadcast station to an MP.
It is compressed and encoded according to the EG2 standard, multiplexed according to the MPEG2 system standard, and broadcast as MPEG2-TS.

On the receiving side, the digital broadcast is received by the antenna 130, the encoded data of the program selected by the user is decoded by the digital broadcast tuner 120, further converted into an analog signal, and output to the monitor output device 140. Is done.

The digital input / output terminal 15 of the recording / reproducing apparatus 10 is connected to the digital broadcast tuner 120. Digital broadcast tuner 120 and recording / reproducing device 1
As the digital I / F with 0, for example, the above-described IE
EE1394 standard I / F is used. Then, as described later, the encoded data of the program selected by the digital broadcast tuner 120 is transmitted to the digital broadcast tuner 12.
0 from the recording / reproducing apparatus 1 via the digital I / F circuit 17
0 and recorded on the disk 61, and the encoded data reproduced from the disk 61
The signal is output to the digital broadcast tuner 120 via the / F circuit 17.

(Configuration of Demultiplexing Processing Unit and Clock Generating Unit: FIG. 3) FIG. 3 shows the demultiplexing processing unit 40 of the recording / reproducing apparatus 10 and the clock generating unit 90 provided in the demultiplexing processing unit 40 in this case. An example is shown. The demultiplexing processing unit 40 in this example includes a clock generation unit 90, a multiplexing circuit 4
1, a separation circuit 42, selectors 43 and 44, an arrival time measurement counter 47, an arrival time addition circuit 48, and an output timing control circuit 49.

Although not shown in the figure, the demultiplexing processing section 40 has a CP for controlling the entire demultiplexing processing section 40 therein.
U and the VCXO of the clock generation unit 90.
(Voltage Controlled Crystal
al Oscillator) 91 and a D / A converter 97, except for a one-chip LSI (Large Sc).
are configured as an integrated circuit).

The clock generator 90 is a VCXO 91 whose oscillation frequency changes within a certain range around 27 MHz in accordance with the control voltage, and an STC (System Time Clock) for counting clocks from the VCXO 91.
k) The PID (Pack) of the PCR as the reference time information included in the MPEG2-TS output from the counter 92 and the digital I / F circuit 17 to the bidirectional bus 18 as the reference time information.
et Identification)
The D detection circuit 93 outputs the M output from the digital I / F circuit 17 to the bidirectional bus 18 based on the detected PID.
A PCR extraction circuit 94 for extracting the PCR contained therein from PEG2-TS, the value of the extracted PCR and ST
A comparison circuit 95 for calculating a difference value from an output value (count value) of the C counter 92; a control calculation circuit for outputting a value calculated from the calculated difference value or a preset fixed value as control data 96, and converting the control data into an analog control voltage of
It is configured by a D / A converter 97 that supplies the XO 91.

When the control value from the control operation circuit 96 is a fixed value, the VCXO 91 has an oscillation frequency of 27 MHz.
Hz, and the control value from the control operation circuit 96 is a value based on the difference value from the comparison circuit 95. When the control value is larger, the oscillation frequency is higher. In response, the oscillation frequency changes substantially linearly.

The control operation circuit 96 receives a mode switching signal sent from the system controller 70 to the control operation circuit 96 based on a user's operation mode switching operation on an operation unit (not shown in the drawing of the recording / reproducing apparatus 10). The output control value is switched as described above.

The arrival time measurement counter 47 counts the clock from the VCXO 91 similarly to the STC counter 92, and can also be used as the STC counter 92. In this example, the arrival time measurement counter 47 is provided separately from the STC counter 92. . The arrival time adding circuit 48 and the output timing control circuit 49 will be described later.

(Operation at Recording) M broadcast from a broadcasting station
PEG2-TS includes a plurality of programs, for example, as shown in FIG.
As shown in (A), information such as video and audio of three programs A, B, and C is multiplexed into one stream.

In the digital broadcast tuner 120 shown in FIG.
The user selects a program to be recorded. The digital broadcast tuner 120 uses only the selected program as an MPEG2-TS, and
The data is transmitted to the recording / reproducing apparatus 10 via the F circuit 17. Therefore, the MPEG2-T input to the recording / reproducing device 10
S is a missing TS (partial TS) as shown in FIG.

In the demultiplexing processing section 40 shown in FIG. 3, the first PCR value included in the MPEG2-TS input to the recording / reproducing apparatus 10 via the digital I / F circuit 17 and obtained on the bidirectional bus 18 is used. , PCR extraction circuit 94 to STC
It is loaded into the counter 92 and the arrival time measurement counter 47.

The second and subsequent PCR values are compared with the output value of the STC counter 92 by the comparison circuit 95 every time the PCR value is extracted from the PCR extraction circuit 94. At the time of this recording, the mode switching signal sent from the system controller 70 to the control arithmetic circuit 96 is in a state in which the PLL is instructed, and the control arithmetic circuit 96 calculates the value calculated from the difference value from the comparison circuit 95. D / A converter 9 as control data
7 is switched to a PLL on state.

Therefore, at this time, the STC counter 9
The oscillation frequency of the VCXO 91 is feedback controlled such that the output value of the counter 2 and the output value of the arrival time counter 47 become equal to the PCR value extracted from the PCR extraction circuit 94, and the difference value between the two becomes zero.

That is, since the oscillation frequency of the VCXO 91 is low, the output values of the STC counter 92 and the arrival time measurement counter 47 increase slowly, and the output value is
When the value is smaller than the R value, the oscillation frequency of the VCXO 91 is controlled to increase. On the contrary, since the oscillation frequency of the VCXO 91 is high, the output values of the STC counter 92 and the arrival time measurement counter 47 increase at a high speed. When the value is larger than the PCR value, control is performed so that the oscillation frequency of the VCXO 91 becomes lower.

By such feedback control,
The output values of the STC counter 92 and the arrival time measurement counter 47 become equal to the PCR value extracted from the PCR extraction circuit 94, and the output value of the MPEG2-TS obtained on the bidirectional bus 18 via the digital I / F circuit 17. It indicates the arrival time of each packet.

Then, in the arrival time adding circuit 48,
The output value of the arrival time measurement counter 47 is added to the end of each packet of the MPEG2-TS obtained on the bidirectional bus 18 as information indicating the arrival time of the packet. The TS is sent from the arrival time adding circuit 48 to the buffer control circuit 50 via the selector 43, and the buffer control circuit 50 fills the space between the packets as shown in FIG. Will be recorded.

(Operation at the time of reproduction) At the time of reproduction, the user selects the data of the program to be viewed from the data recorded on the disk 61 in the recording / reproducing apparatus 10.

As a result, as shown in FIG. 4C, the data of the selected program is added to the end of each packet from the disk 61 by adding the arrival time information to the end of each packet. Read as TS. The reproduced MPEG2-TS is sent to the buffer control circuit 50, and is supplied from the buffer control circuit 50 to the output timing control circuit 49 via the selector 44.

At the time of this reproduction, the mode switching signal sent from the system controller 70 to the control operation circuit 96 is in a state of instructing the PLL to be turned off, and the control operation circuit 96 controls the preset fixed value. The PLL is turned off to output data to the D / A converter 97 and the oscillation frequency of the VCXO 91 becomes 27 MHz.
fixed to z.

The clock of a fixed frequency of 27 MHz from the VCXO 91 is counted by the arrival time measuring counter 47. The output timing control circuit 49 outputs the reproduced M
The arrival time information added to the first packet of the PEG2-TS is loaded into the arrival time measurement counter 47.

Further, the output timing control circuit 49
For each of the second and subsequent packets of the reproduced MPEG2-TS, the output value of the arrival time counter 47 is added to the value of the arrival time information added to the packet while referring to the output value of the arrival time counter 47. When they match, the packet is output to the bidirectional bus 18.

Thus, the output timing control circuit 4
9 to the bidirectional bus 18 as shown in FIG.
The packet is output at the same timing as during recording, and the MPEG2-TS with the same omission as during recording is output. However, since the arrival time information is used only inside the recording / reproducing device 10, the output timing control circuit 49
Is not output.

The MPEG2- output to the bidirectional bus 18
The TS is output to the digital broadcast tuner 120 via the digital I / F circuit 17, decoded, converted into an analog signal, and output to the monitor output device 140.

(Operation at Analog Input and Analog Output) As described above with reference to FIG. 1, the MPE obtained from the multiplexing circuit 41 by the video signal and the audio signal from the terrestrial tuner 21 or the input terminals 11V, 11S, 11A.
When the G2-TS is recorded on the disk 61, as shown in FIG.
S is sent to the buffer control circuit 50 via the selector 43 and is recorded on the disk 61 by the HDD 60.

In this case, the mode switching signal from the system controller 70 is in a state of instructing the PLL to be turned off, and the VCXO 91 outputs a clock of a fixed frequency of 27 MHz, and the clock of the fixed frequency is supplied to the multiplexing circuit 41. Then, the multiplexing processing in the multiplexing circuit 41 is performed.

Also, the MPEG2-recorded as described above
The TS is reproduced from the disk 61 and the output terminal 12 shown in FIG.
When a reproduced video signal and a reproduced audio signal are obtained at V, 12S and 12A, as shown in FIG. 3, the reproduced MPEG2-TS from the buffer control circuit 50 is supplied to the separation circuit 42 via the selector 44. Is done.

Also in this case, the mode switching signal from system controller 70 is in a state of instructing PLL off, and a fixed frequency clock of 27 MHz is output from VCXO 91, and the fixed frequency clock is supplied to separation circuit 42. Then, the separation processing in the separation circuit 42 is performed.

[Other Examples or Embodiments] In the above-described example, the recording / reproducing device 10 is connected via the digital I / F circuit 17.
Is a partial TS (missing TS) as shown in FIG. 4B, and the MPEG2-TS input to the recording / reproducing apparatus 10 has only one sequence of PCR packets. No, the PID detection circuit 9
3 is PAT (Program Associate)
n Table) and PMT (ProgramMMap)
Table) in order to obtain the P
The ID can be specified.

However, the MPEG2-TS input to the recording / reproducing device 10 via the digital I / F circuit 17 is a full TS (a plurality of programs are multiplexed and a packet TS)
MPEG2-TS input to the recording / reproducing apparatus 10 has P
Since there are as many CR packets as the number of programs, the PID of the PCR cannot be specified as it is. Therefore, in this case, a means for specifying the PID of the PCR by some method is necessary, for example, by notifying the program selected by the digital broadcast tuner 120 to the recording / reproducing device 10.

The bit stream input to the recording / reproducing apparatus 10 via the digital I / F circuit 17 is an MPE.
Even in the case other than the G2-TS, as long as a packet to which reference time information such as PCR is added is transmitted, a PLL on / off function similar to the above-described example can be realized. For example, MPEG2-PS (ProgramSt
stream), the SCR (System Clock)
Reference), DSS (Digital S)
Attellite System: a system stream format often used in digital satellite broadcasting in the United States, RTS (Reference Time Stream)
Since p) respectively corresponds to the PCR of MPEG2-TS, the PLL on / off function similar to the above-described example can be realized by extracting the reference time information.

In the above example, the digital broadcast tuner 120 is connected to the recording / reproducing apparatus 10.
For example, another digital recording / reproducing device is connected to the recording / reproducing device 10, digital data from the other digital recording / reproducing device is input to the recording / reproducing device 10 and recorded on the disc 61, or digital data is read from the disc 61. Reproduce and output to another digital recording / reproducing device, or connect a digital moving image photographing device to the recording / reproducing device 10 and input digital data from the digital moving image photographing device to the recording / reproducing device 10 to record on the disk 61 You can also.

Further, in the above-described example, the digital broadcast tuner 120 is connected to the recording / reproducing device 10 as an external device. However, the digital broadcasting tuner is incorporated in the recording / reproducing device to be integrated with the recording / reproducing device, or the recording / reproducing device is integrated. The device may be incorporated in a digital broadcast receiver and integrated with the receiver. In this case, the clock generation unit 90 of the recording / reproducing device 10 and the clock generation unit of the digital broadcast tuner or the digital broadcast receiver are shared. Can be

In the above example, a hard disk is used as a recording medium (storage element) of the recording / reproducing apparatus. However, an optical disk, a magneto-optical disk, a semiconductor memory, or the like may be used.

[0075]

As described above, according to the present invention, a clock synchronized with reference time information included in digital data for recording digital data and the like, and a clock for reproducing digital data are recorded by one oscillator. , And a clock of a fixed frequency can be selectively obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a recording / reproducing apparatus of the present invention.

FIG. 2 is a diagram showing an example of a system configuration when an external device is connected to the recording / reproducing device of the present invention.

FIG. 3 is a diagram illustrating an example of a demultiplexing processing unit and a clock generation unit.

FIG. 4 is a diagram illustrating an example of data processing when recording and reproducing an encoded bit stream of a digital broadcast.

[Explanation of symbols]

Since the main parts are all described in the figure, they are omitted here.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Isao Obata 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Ken Ken 7-35, Kita-Shinagawa, Shinagawa-ku, Tokyo No. Sony Corporation F-term (reference) 5C020 AA09 AA37 BA20 BB07 CA11 CA13 CA15 5C053 FA23 GA11 GB06 GB10 GB38 HA01 HC02 JA22 JA26 KA08 KA10 KA18 KA20 KA21 KA24 LA06 5D044 AB07 BC01 CC04 GK08 GM14 GM17 GM34

Claims (5)

[Claims] An oscillator whose oscillation frequency changes in accordance with a control value, a counter for counting a clock from the oscillator, extraction means for extracting reference time information from digital data including reference time information, Comparing means for calculating a difference value between the value of the reference time information and the output value of the counter, and calculating means for calculating a control value to be supplied to the oscillator from the calculated difference value. A synchronous mode in which the arithmetic means is controlled by a mode switching signal and a clock synchronized with the reference time information is obtained from the oscillator by supplying a value calculated from the difference value as the control value to the oscillator. A fixed mode in which a fixed value clock is obtained from the oscillator by supplying a fixed value as the control value to the oscillator, A clock generator that can be switched to either. 2. An oscillator whose oscillation frequency changes according to a control value, a counter for counting a clock from the oscillator, extraction means for extracting reference time information from digital data including reference time information, and an extraction means for extracting the reference time information. A comparison unit that calculates a difference value between the value of the reference time information and the output value of the counter, and a clock generation unit that has a calculation unit that calculates a control value to be supplied to the oscillator from the calculated difference value. A clock synchronized with the reference time information from the oscillator by controlling the arithmetic means by a mode switching signal and supplying the clock generator with a value calculated from the difference value as the control value to the oscillator. Is obtained, and a fixed value is supplied to the oscillator as the control value, whereby a clock of a fixed frequency is generated from the oscillator. A recording / reproducing apparatus comprising: a control unit configured to switch to one of an obtained fixed mode. 3. The recording / reproducing apparatus according to claim 2, wherein the controller switches the clock generator to the synchronous mode when the digital data is recorded on a recording medium, and reproduces the digital data from the recording medium. A recording / reproducing apparatus that switches the clock generation unit to the fixed mode when the operation is performed. 4. The recording / reproducing apparatus according to claim 3, wherein an arrival time counter for counting clocks from said oscillator, serving as said counter, or different from said counter, and digital data recorded on said recording medium. An arrival time adding means for adding the output value of the arrival time measurement counter as arrival time information; and calculating the arrival time by adding the digital data reproduced from the recording medium to the value of the arrival time information added thereto. An output timing control means for outputting when the output values of the counters match, and a recording / reproducing apparatus comprising: 5. The recording / reproducing apparatus according to claim 3, wherein an analog signal input from the outside is converted into digital data, and a processing section for recording the digital signal on the recording medium, and the recorded digital data is converted into digital data. A processing unit for reproducing from the recording medium, converting the signal to an analog signal, and outputting the signal to the outside, wherein the control unit switches the clock generation unit to the fixed mode at the time of analog input and analog output. Recording and playback device.