JPH0583224A - Stuff multiplexer - Google Patents

Abstract

PURPOSE:To attain stuff multiplex transmission by synchronizing a start-stop data input with a write clock so as to reduce a distortion factor of a waveform in the input data and a data transmission error. CONSTITUTION:Inputted start-stop data are fed to a buffer memory 3 via an interface circuit 11 and an asynchronization and synchronization conversion circuit 2. A clock generated by frequency-dividing an in-equipment reference clock 12 at a frequency divider circuit 7 is processed by the circuit 2 and the result is fed to the memory 3 and a phase comparator circuit 4. A read clock generating circuit 6 generates a clock together with the circuit 7 and gives the clock to a stuff control circuit 5. The circuit 5 controls the read clock based on the output of the circuit 4 and sends it to the memory 3. The circuit 4 sends the result of phase comparison between the write clock and the read clock to the circuit 5, which sends stuff information to a timing adjustment circuit 8. A multiplex control circuit 9 multiplexes the output of the memory 3 and the output of the circuit 8 and outputs the result. In this case, the start- stop data are synchronized by the write clock.

Description

Detailed Description of the Invention

[0001]

The present invention is used in a time division multiplex transmission device. In particular, it relates to a stuff multiplex transmission technique for start-stop data.

[0002]

2. Description of the Related Art In this type of multiplexing method, input start-stop data is subjected to multipoint sampling processing at a clock several times the speed of the input data, time-division multiplexed as pseudo-synchronous data, and reproduced at the opposite station. This data is output to the terminal device.

[0003]

According to this method, the start-stop data is sampled at multiple points with a frequency clock that is an integral multiple of the transmission rate of the start-stop data, and time-division multiplexed as pseudo sync data. For this reason, when high-speed start-stop data is input, a sampling clock with a high frequency is required for multipoint sampling processing, which lowers the multiplexing efficiency. When data is reproduced by the opposite station when sampling is performed by the clock, the distortion factor of the waveform is deteriorated and a data transmission error occurs.

The present invention has been made against such a background, and an object thereof is to provide an apparatus capable of performing stuff multiplex transmission of start-stop type data while reducing a waveform distortion rate and a data transmission error.

[0005]

According to the present invention, a data input terminal for inputting data, a buffer memory for temporarily storing the data, a read clock generating circuit for reading the data from the buffer memory, and a read clock generating circuit for the read clock. A phase comparison circuit that outputs a stuff request by comparing the phase with a write clock of the buffer memory generated by dividing a reference clock in the device, and generates a stuff information by inputting the stuff request from the phase comparison circuit. In a stuff multiplexer including a stuff control circuit and a multiplex control circuit for multiplexing the data read from the buffer memory and the stuff information, start-stop data is input to the data input terminal. Is synchronized with a write clock generated by dividing the reference clock in the device,
It is characterized in that an asynchronous synchronous conversion circuit for writing in the buffer memory is provided in a preceding stage of the buffer memory.

The above is described again from the viewpoint of data transmission / reception. In the device of the present invention, which is the data transmission side of the multiplexing device, the input start / stop data is subjected to asynchronous synchronous conversion processing and converted into synchronous data. Synchronous conversion circuit, buffer memory for accumulating data, read clock generation circuit of this buffer memory, and phase comparison for detecting the phase difference between the read clock and the write clock generated by dividing the reference clock in the device A unit, a stuff control circuit for generating stuff information, and a multiplexing control circuit for multiplexing data and stuff information, and detecting a phase difference between the write clock and the read clock to the buffer memory, The number of data to be multiplexed into N + n
And N and N-m (N, n, and m are integers) mixed arrays, and by rearranging the array of N + n, N, and N-m, the frequency difference or phase of the start-stop data and the timing signal in the device Absorb differences and perform staff multiplexing.

On the data receiving side, a separation control circuit for separating the data from the stuff information and detecting the stuff information,
A buffer memory that stores data, a write clock generation circuit that controls a write clock to the buffer memory, and a DPLL (Digital Phase Loc) that generates a read clock that smoothly changes according to stuff information.
and a read clock generation circuit configured by a Ked Loop) and reproducing data having an array of N + n and N / N-m mixed in a unit frame from the opposite station as start-stop data. And

[0008]

By synchronizing the asynchronous data input with the asynchronous synchronous conversion circuit, the signal is converted into a signal more suitable for stuff multiplex transmission.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

According to the present invention, a data input terminal 1 for inputting data and a buffer memory 3 for temporarily storing this data are provided.
And a read clock generation circuit 6 for reading data from the buffer memory 3, and a phase of the read clock is compared with a write clock of the buffer memory 3 generated by dividing the reference clock 12 in the device and outputs a stuff request. And a stuff control circuit 5 for inputting a stuff request from this phase comparison circuit 4 and generating stuff information.
In the stuff multiplexer including the multiplex control circuit 9 for multiplexing the data read from the buffer memory 3 and the stuff information, the start-stop data is input to the data input terminal 1, and the start-stop data is stored in the device. Reference clock 12
Is synchronized with a write clock generated by dividing the frequency of the clock, and an asynchronous synchronous conversion circuit 2 for writing in the buffer memory 3 is provided in the preceding stage of the buffer memory 3.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a diagram showing the configuration of a stuff multiplex signal receiving apparatus used in the embodiment of the present invention. 3 to 4
FIG. 6 is a diagram showing a data transition state in the device of the embodiment of the present invention.

In FIG. 1, a data input terminal 1 to which start-stop type data is input is a data input interface circuit 1.
1 and the asynchronous-synchronous conversion circuit 2 and then the buffer memory 3
Connected to. In-apparatus reference clock 12 by frequency dividing circuit 7
The clock generated by dividing the
Is processed and connected to the buffer memory 3 and the phase comparison circuit 4. The read clock generating circuit 6 generates a clock together with the frequency dividing circuit 7 and outputs it to the stuff control circuit 5. The stuff control circuit 5 controls the read clock by the output of the phase comparison circuit 4 and outputs it to the buffer memory 3. The phase comparison circuit 4 compares the phases of the write clock and the read clock generated in the asynchronous synchronous conversion circuit 2 and outputs the result to the stuff control circuit 5, which supplies the stuff information to the timing adjustment circuit 8. Output. The multiplexing control circuit 9 multiplexes the output of the buffer memory 3 and the output of the timing adjustment circuit 8 and outputs the multiplexed output from the multiplexed data output terminal 10.

In FIG. 2, the multiplexed data input terminal 20 is connected to the separation control circuit 21, and the data separated by the separation control circuit 21 is output to the buffer memory 25. Similarly, the stuff control information separated by the separation control circuit 21 is output to the timing adjustment circuit 27. The write clock generating circuit 23, together with the frequency dividing circuit 22, generates a write clock from the in-device reference clock 12 and outputs it to the destuff control circuit 24. The destuff control circuit 24 controls the write clock by the output of the timing adjustment circuit 27 and outputs it to the buffer memory 25 and the phase comparison circuit 26.
The phase comparison circuit 26 includes a DPLL read clock generation circuit 28.
The read clock generated in step S4 and input to the buffer memory 25 is compared with the output of the destuff control circuit 24, and the output is input to the DPLL read clock generation circuit 28. The output data of the buffer memory 25 is output to the data output terminal 31 via the data output interface circuit 29.

Next, the state of data transition from the time data is input to the device of the present invention to the time it is output to the receiving device will be described.

The number of data to be multiplexed in a unit frame is a mixed array of N + n, N and N-m (N, n and m are integers), and this N + n, N and N-m array is rearranged. Thus, the stuff multiplexing is performed by absorbing the frequency difference or phase difference between the start-stop data and the in-apparatus timing signal, but here, n = 1 and m = 1 will be described.

FIG. 3 shows the state of the transmitting side, and FIG. 4 shows the state of the receiving side. Data 3 input to data input terminal 1
1 is written in the buffer memory 3 by the write clock 32 generated in the asynchronous synchronous conversion circuit 2. The read clock 33, which is the output of the read clock generation circuit 6, is added to the stuff control circuit 5. In the stuff control circuit 5, N + 1 or N-1 clocks are obtained within a time unit of the time T shown in FIG. Data is read from the buffer memory 3 by the controlled output clock 34 and input to the multiplexing control circuit 9. Here, the write clock 32 and the read clock 33 generated in the asynchronous synchronous conversion circuit 2
If the frequencies of are the same, the alternating repetition of N + 1 and N-1 is performed regularly. The frequency of the write clock 32 generated in the asynchronous synchronous conversion circuit 2 is the read clock 33.
If the frequency is slightly higher than the
The output 35 of the phase comparison circuit 4 rises at the time when the number of pieces is generated, and the output of the stuff control circuit 5 which receives this information is controlled to reduce this phase difference. As shown in the section of b, the state where the number of clocks in the time unit of T of the output clock is N + 1 is continued. By this control, the phase difference is reduced, and thereafter, the repetition of N + 1 and N-1 continues. After that, the above control is performed every time the phase difference is generated for one clock. The stuff information 36 for determining the number N + 1 or N-1 of data in the unit section is generated by the timing adjustment circuit 8 and sent to the multiplexing control circuit 9. The staff information 36 is the number of data N + 1 in the unit section.
When it is, it becomes 1, and when it is N-1, it becomes 0.

The multiplexing control circuit 9 multiplexes the data read from the buffer memory 3 and the stuff information 36 which is the output of the timing adjustment circuit 8, and multiplex data output 37 in which the stuff information 36 is multiplexed after the multiplexed data. Output to the multiplex data output terminal 10. When the frequency of the write clock 32 generated by the asynchronous synchronous converter circuit 2 is slightly lower than the frequency of the read clock 33, the state of N−1 remains until the phase difference between the write clock 32 and the read clock 33 disappears. The process is continuous, and the other processes are the same as those described above. As a result, the start-stop data having a frequency different from that of the read clock 33 can be multiplexed without error.

Next, the operation on the receiving side will be described. The data input from the multiplex data input terminal 20 is separated by the separation control circuit 21 into a data portion 42 and stuff information 43. The clock generated by the write clock generation circuit 23 is input to the destuff control circuit 24. The destuff control circuit 24 controls the clock generated by the write clock generation circuit 23 according to the stuff information 43 that has passed through the timing adjustment circuit 27, and generates the write clock 44. The data 42 separated by the separation control circuit 21 by the write clock 44 is written in the buffer memory 25. The read clock 45 for reading data from the buffer memory 25 is generated by the DPLL read clock generation circuit 28. The phase comparison circuit 26 compares the phase difference between the write clock 44 and the read clock 45, and the result is DPLL.
It is output to the read clock generation circuit 28. The DPLL read clock generation circuit 28 gently changes the frequency or phase of the reception side output clock according to the input phase difference information so that the phase difference between the write clock 44 and the read clock 45 is minimized. By this control, the start-stop type output data 46 is output from the data output terminal 30 via the data output interface circuit 29 so as to follow the frequency change of the input data.

[0019]

When the asynchronous data is subjected to the asynchronous synchronous conversion processing to multiplex N data in the unit section, the data is changed into a mixed form of N + n and N and N-m, and N + n data is changed due to the fluctuation of the input data. Continuous or N-m continuous or N and N
Staff processing is performed in the form of a mixture of −m and N + n,
Stuff information is time-division multiplexed with data and transmitted to the opposite station, and the staff information received by the opposite station and the DPLL are used to reproduce the time-division-multiplexed data and output it to the terminal device, so that the start-stop data is error-free. There is an effect that time division multiplex transmission is possible.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a receiving side device used in an embodiment of the present invention.

FIG. 3 is a diagram for explaining a data transition status in the device according to the embodiment of the present invention.

FIG. 4 is a diagram for explaining a data transition status in the receiving side apparatus used in the embodiment of the present invention.

[Explanation of symbols]

 1 Data Input Terminal 2 Asynchronous Synchronous Conversion Circuit 3, 25 Buffer Memory 4, 26 Phase Comparison Circuit 5 Stuff Control Circuit 6 Read Clock Generation Circuit 7, 22 Frequency Division Circuit 8, 27 Timing Adjustment Circuit 9 Multiplexing Control Circuit 10 Multiplexed Data Output Terminal 11 data input interface circuit 12 in-apparatus reference clock 20 multiplexed data input terminal 21 separation control circuit 23 write clock generation circuit 24 destuff control circuit 28 DPLL read clock generation circuit 29 data output interface circuit 30 data output terminal 31 start-stop input data 32, 44 Write clock 33, 45 Read clock 34 Output clock 35 Output of phase comparator 36, 43 Stuff information 37 Multiplex data output 41 Multiplex data input 42 Data portion 46 Start-stop data output

Claims (1)

[Claims] 1. A data input terminal for inputting data, a buffer memory for temporarily storing the data, a read clock generating circuit for reading the data from the buffer memory, and a phase of the read clock as a reference clock in the apparatus. A phase comparison circuit for outputting a stuff request by comparing with a write clock of the buffer memory generated by frequency division, a stuff control circuit for receiving the stuff request from the phase comparison circuit and generating stuff information, and the buffer. In a stuff multiplexer including a multiplexing control circuit for multiplexing data read from a memory and the stuff information, start-stop data is input to the data input terminal, and the start-stop data is used as a reference clock in the device. Asynchronous synchronous conversion that synchronizes with a write clock generated by frequency division and writes to the buffer memory A stuff multiplexing apparatus comprising a circuit in the preceding stage of the buffer memory.