JP2979847B2 - Positive / negative staff synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a positive / negative stuff synchronization system in digital signal transmission.

[0002]

2. Description of the Related Art In order to transmit digital signals efficiently and economically, a plurality of low-speed digital signals are generally transmitted as one high-speed digital signal by time division multiplexing. In order to perform time division multiplexing, it is necessary that the speeds of a plurality of low-speed digital signals to be multiplexed are equal to each other, that is, bit synchronization is established. However, the speed of a digital signal in an actual transmission path network does not exactly match if the reference clock source is different. Therefore, on the transmitting side, the speeds of a plurality of low-speed signals that are not exactly the same are pseudo-matched with the speed of one synchronization clock, and then time-division multiplexing is performed. A method is used in which a signal is separated into low-speed signals and then restored to the speed at the time of input to the transmission unit. On the transmitting side, in order to simulate bit synchronization of the input asynchronous low-speed signal with one synchronization clock, the frequency of the low-speed clock synchronized with the input low-speed signal and the frequency of the synchronization clock frequency A stuff synchronization method is generally used in which stuff bits meaningless as information are inserted into a low-speed signal according to the difference. On the receiving side, the above stuff bit is deleted, that is, destuffed, and the original speed is restored. When destuffing is performed on the receiving side, a gap occurs in the low-speed signal. The gap due to the destuffing causes a temporal change in the frequency of the restored low-speed clock, that is, destuffing jitter, and lowers the transmission quality. In general, a phase locked loop (hereinafter, referred to as a PLL) is used to suppress and smooth destuff jitter and restore a low-speed clock input to a transmission unit.

When the stuffing cycle is short, the cycle in which a gap occurs due to destuffing is short, so that the frequency of the destuffing jitter is high, and it can be suppressed relatively easily using a PLL. However, when the speed of the input asynchronous low-speed signal is close to the frequency of the synchronization clock and the frequency difference is small, the stuffing cycle becomes longer. Accordingly, the cycle in which the gap is generated by the destuffing becomes longer, so that the frequency of the destuffing jitter becomes lower. Of the frequency components of the destuff jitter, components lower than the low-pass cutoff frequency of the low-pass filter that constitutes the PLL cannot be suppressed.
Destuff jitter increases and transmission quality is significantly reduced.

FIG. 5 is a block diagram showing a configuration of a conventional stuff synchronization system, for example, disclosed in Japanese Patent Application Laid-Open No. 62-291230. 6 and 7 are diagrams for explaining the operation of FIG. In FIG. 5, 1 is a clock regenerator, 2 is a write address generator, 3 is a memory unit (elastic store), 4 is a synthesizing unit (multiplexer), 5 is a timing generator / controller, 6 is a read address generator, 7b is an analog phase comparator, 8 is a digital phase comparator, 9b is an addition amplifier, 12 is a first comparator, and 13 is a digital comparator.
An analog converter, 14 is a waveform generator, 15 is an addition amplifier, 16 is an addition amplifier, and 17 is a second comparator. In addition, a is an input signal, b is a synchronization signal, c is a positive stuff threshold signal, d is a difference signal between the write timing and the read timing to the elastic store 3, e is a stuffable timing signal, and f is a positive stuff signal. Request signal, g is a negative stuff request signal, h is a negative stuff threshold signal, i
Represents a difference signal between the write address and the read address to the elastic store 3, and j represents a phase difference signal between the write clock and the read clock.

Next, the operation of FIG. 5 will be described with reference to FIGS. In the clock regenerator 1, a clock component is extracted from the asynchronous input signal a to generate a write clock to the elastic store 3 synchronized with the asynchronous input signal a. The write address generator 2 divides the frequency of the write clock to generate a write address for the elastic store 3. The asynchronous input signal a is sequentially written to the elastic store 3 in accordance with the write address. The timing generator / controller 5 outputs a read clock from the elastic store 3 and a stuff signal. The read address generator 6 divides the frequency of the read clock to generate a read address from the elastic store 3. The contents of the elastic store 3 are read in the order in which they were written in accordance with the read address. The multiplexer 4 combines the signal read from the elastic store 3 and the stuff signal to generate a synchronization signal b.

The analog phase comparator 7b compares the phase of the write clock to the elastic store 3 with the phase of the read clock from the elastic store 3, and outputs a voltage signal j proportional to the phase difference. When the write clock is faster than the read clock, the phase difference increases, so that the output voltage signal j fluctuates in a saw-tooth shape having an upward slope as shown in FIG. The frequency of the fluctuation is equal to the frequency difference between the write clock and the read clock. In the digital phase comparator 8, a phase comparison between the write address to the elastic store 3 and the read address from the elastic store 3, that is, a comparison between the write address and the read address represented by a binary number, is performed. Is output as a difference signal between the write address and the read address represented by the following expression. The digital-analog converter 13 converts the phase comparison result into a voltage signal i proportional to the phase difference. If the write clock is faster than the read clock, and if no stuff operation is performed, the difference between the write address and the read address increases to the capacity of the elastic store 3 and then becomes 0 again, and the output voltage signal i is as shown in FIG. b)
Fluctuates stepwise as shown in FIG. That is, the write address may overtake the read address, resulting in a read error. In the summing amplifier 9b, a voltage signal j proportional to the phase difference between the write clock and the read clock output from the analog phase comparator 7b, and a digital signal
The voltage signal i proportional to the difference between the write address and the read address, which is the output of the analog converter 13, is added, and the output of the addition amplifier 9b has the difference between the write timing to the elastic store 3 and the read timing. A proportional voltage signal d is obtained. If the write clock is faster than the read clock, and if no stuff operation is performed, the output voltage signal d fluctuates in a saw-tooth shape having a right-up slope as shown in FIG. As described above, if there is a speed difference between the write clock and the read clock to the elastic store 3, if the operation is continued without performing stuffing, a read error will occur. A read error is avoided by advancing or delaying. A voltage signal d proportional to the difference between the write timing and the read timing for the elastic store 3
Changes discontinuously each time the stuff is performed, and the resulting fluctuation range remains within a certain range defined by the threshold value.

In the waveform generator 14, a periodic signal is generated. In the summing amplifier 15 and the summing amplifier 16, in this case, the voltage applied to the summing amplifier 15 is higher than the voltage applied to the summing amplifier 16, and the outputs of the summing amplifier 15 and the summing amplifier 16 are shown in FIG. Thus, periodic signals c and h having a constant voltage difference are obtained. The first comparator 12 compares the voltage signal d, which is the output of the addition amplifier 9b, which is proportional to the difference between the write timing and the read timing, with the positive stuff threshold signal c, which is the output of the addition amplifier 15, When the read phase advances with respect to the write phase, that is, when the phase difference decreases, the addition amplifier 9b
Output voltage d decreases. On the other hand, when the output voltage d of the addition amplifier 9b is lower than the positive stuff threshold signal c which is the output of the addition amplifier 15, the output is determined to have a positive stuff request. That is, the positive stuff determination is performed based on the positive stuff threshold signal c. Also in the second comparator 17,
The voltage signal d proportional to the difference between the write timing and the read timing, which is the output of the addition amplifier 9b, is compared with the negative stuff threshold signal h, which is the output of the addition amplifier 16, and the read phase is compared with the write phase. When the delay occurs, that is, when the phase difference increases, the output voltage d
Will be higher. When the output voltage d of the addition amplifier 9b is higher than the negative stuff threshold signal h which is the output of the addition amplifier 16, the output is determined to have a negative stuff request. That is, the negative stuff determination is performed based on the negative stuff threshold signal h. In the timing generation / control circuit 5, when there is a positive stuff request which is the output of the first comparator 12, the read clock is controlled, the read phase from the elastic store 3 is delayed by one bit, I do. Since the reading phase is delayed, the phase difference between reading and writing increases, and the output voltage d of the addition amplifier 9b is increased.
Becomes higher, the positive stuff request, which is the output of the first comparator 12, is released. On the other hand, in the timing generation / control circuit 5, when there is a negative stuff request which is the output of the second comparator 17, the read clock is controlled, the read phase from the elastic store 3 is advanced by one bit, and the negative Do staff. Since the read phase is advanced, the phase difference between read and write becomes small, and the output voltage d of the addition amplifier 9b becomes low.
The negative stuff request output of 7 is released.

In the above-mentioned stuff synchronous system, the main part when the speed of the asynchronous input signal a, that is, the frequency of the write clock to the elastic store 3 synchronized with the asynchronous input signal a is slightly higher than the frequency of the read clock. 6 is shown in FIG. The horizontal axis represents time, and the vertical axis represents the magnitude of the difference between the write timing and the read timing for the elastic store 3 by voltage. The output of the waveform generator 14 has a continuous saw-tooth shape, and the cycle is eight times the cycle of the stuffable timing signal e. Also, the amplitude of the output voltage signal c of the addition amplifier 15 which is a positive stuff threshold signal, the amplitude of the output voltage signal h of the addition amplifier 16 which is a negative stuff threshold signal, and the output voltage signal c of the addition amplifier 15 The voltage difference between the output voltage signals h of the summing amplifier 16 is 1
The amount of change in the output voltage signal d of the addition amplifier 9b with respect to the amount of change in the difference between the write timing and the read timing due to the stuffing operation is the same.

In the above stuff synchronization system, positive stuff is performed eight times and negative stuff is performed nine times at substantially equal intervals during a period 80 times the cycle of the stuff enable timing signal e. In the stuff synchronization method having the above, the stuff is performed at a cycle shorter than the cycle at which the stuff is performed. Therefore, the frequency of the destuffing jitter on the receiving side becomes higher, so that the PLL can be used to suppress the destuffing jitter.

[0010]

The conventional positive / negative stuff synchronization system is configured as described above, and can reduce the destuff jitter of the recovered clock on the receiving side. However, the stuff control means on the transmitting side sets a threshold value that fluctuates for each of the positive and negative stuffs and independently performs a phase comparison to generate a stuff request signal. There is also a problem that there are variations and fluctuations, and also when a configuration is made using only digital elements without using analog elements, the circuit scale is increased and power consumption is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is possible to reduce the destuff jitter of the recovered clock on the receiving side with a simple configuration, and to reduce variations and fluctuations in element characteristics. It is an object of the present invention to obtain a positive / negative stuff synchronization system having a small circuit size and low power consumption.

[0012]

In order to achieve the above object, a positive / negative stuff synchronization system according to the first aspect of the present invention synchronizes and transmits an asynchronous digital signal, and receives and outputs the synchronized digital signal. On the transmitting side of the stuff synchronous system for reproducing the asynchronous digital signal, a memory section for temporarily storing an asynchronous digital signal input signal, write control means for sequentially writing the input signal to the memory section, Read control means for sequentially reading the input signal; stuff control means for executing positive / negative stuff in accordance with a frequency difference between a reproduction clock extracted from the asynchronous digital signal and a clock of a synchronization signal; Synthesizing means for synthesizing a signal and the above-mentioned positive / negative stuff signal and outputting a synchronized digital signal The stuff control means always generates a negative stuff request signal at a constant cycle, detects a phase difference between a reproduction clock extracted from an asynchronous digital signal and a clock of a synchronization signal, and detects the magnitude of the phase difference and a constant value. A positive stuff request signal is generated by comparing the threshold value of the periodic signal with the threshold value, and the positive and negative stuff is executed. The positive / negative stuff synchronous system according to the second aspect is characterized in that the stuff control means of the positive / negative stuff synchronous system according to the first aspect always generates a positive stuff request signal at a fixed cycle and reproduces the signal extracted from an asynchronous digital signal. The phase difference between the clock and the clock of the synchronization signal is detected, the magnitude is compared with a threshold value of a fixed periodic signal, a negative stuff request signal is generated, and the positive and negative stuff is executed. is there. Further, the positive / negative stuff synchronization system according to the third aspect is the first or second aspect.
Of the staff control means of the positive / negative staff synchronization method related to
The cycle in which the stuff request signal is generated matches the cycle of the threshold periodic signal. According to a fourth aspect of the present invention, there is provided a positive / negative stuff synchronizing method, wherein the stuff control means of the positive / negative stuff synchronizing method according to the first or third aspect fixes a negative stuff request signal constantly generated at a constant cycle. When the magnitude of the phase difference between the asynchronous digital signal and the signal to be synchronized is larger than the threshold value, the negative stuff is continuously performed. According to a fifth aspect of the present invention, there is provided a positive / negative stuff synchronization system wherein the stuff control means of the positive / negative stuff synchronization system according to the second or third aspect fixes a positive stuff request signal constantly generated at a constant cycle. When the magnitude of the phase difference between the asynchronous digital signal and the signal to be synchronized is smaller than the threshold value, the positive stuff is executed continuously. The positive / negative staff synchronization method according to claim 6 is as follows.
The stuff control means of the positive / negative stuff synchronization system according to claim 1 or 3 provides a fixed threshold value for a negative stuff request signal which is always generated at a constant cycle, and a signal which synchronizes with an asynchronous digital signal. If the magnitude of the phase difference between is smaller than the threshold value, the negative stuff is not executed. Further, in the positive / negative stuff synchronization system according to claim 7, the stuff control means of the positive / negative stuff synchronization system according to claim 2 or 3 fixes a positive stuff request signal constantly generated at a fixed cycle to a positive stuff request signal. When the magnitude of the phase difference between the asynchronous digital signal and the signal to be synchronized is larger than the threshold value, the positive stuff is not performed.

[0013]

According to the stuff control means of the positive / negative stuff synchronous system according to the first and second aspects of the present invention,
Rather than providing a threshold value that fluctuates for each of the positive and negative stuff and performing independent phase comparison and executing the positive and negative stuff,
Negative or positive stuff is always executed on one side at a fixed period, and the phase difference between the asynchronous digital signal and the synchronization signal is detected, and the magnitude is compared with the threshold value of the fixed period signal to be positive or negative. By executing the stuffing on the other side, the destuffing jitter of the recovered clock on the receiving side can be reduced with a simple configuration. Also,
In the stuff control means of the positive / negative stuff synchronous system according to the third aspect, the cycle of generating the stuff request signal and the cycle of the threshold cycle signal are made to coincide with each other, so that the configuration is further simplified. Can be. Further, in the stuff control means of the positive / negative stuff synchronous system according to the fourth aspect, in addition to the operation of the invention according to the first or third aspect, the stuff control means is fixed to a negative stuff request signal having a stuff request at a fixed cycle. When a threshold value is provided and the difference between the write timing to the elastic store 3 and the read timing is larger than the threshold value, the negative stuff is continuously executed, so that even when the timing difference is extremely large, Thus, the timing difference can be promptly determined as appropriate. Further, in the stuff control means of the positive / negative stuff synchronous system according to the fifth aspect, in addition to the operation of the invention according to the second or third aspect, a positive stuff request signal having a stuff request at a fixed cycle is fixed. When a threshold value is provided, and the difference between the write timing and the read timing for the elastic store 3 is smaller than the threshold value, by executing the positive stuff continuously, when the difference in the timing is extremely small, However, it is also possible to promptly make an appropriate timing difference. In the stuff control means of the positive / negative stuff synchronous system according to claim 6, in addition to the operation of the invention according to claim 1 or 3, the stuff control means is fixed to a negative stuff request signal always generated at a constant cycle. If a threshold value is provided and the magnitude of the phase difference between the asynchronous digital signal and the signal to be synchronized is smaller than the above threshold value, by performing no negative stuff, the appropriate timing difference can be promptly obtained. It can be. Claim 7
In the stuff control means of the positive / negative stuff synchronous system according to the present invention, in addition to the effect of the invention according to claim 2 or 3, a fixed threshold value is provided for a positive stuff request signal constantly generated at a constant cycle, If the magnitude of the phase difference between the asynchronous digital signal and the signal to be synchronized is larger than the threshold value, correct timing can be promptly obtained by not executing the positive stuffing. .

[0014]

[Embodiment 1] FIG. 1 is a block diagram showing a first embodiment of the positive / negative stuff synchronization system according to the first aspect.
FIG. 2 is a diagram for explaining the operation of FIG. In FIG.
1 is a clock regenerator, 2 is a write address generator, 3
Is an elastic store as a memory unit, 4 is a multiplexer as a synthesizing unit, 5 is a timing generator / controller, 6
Is a read address generator, 7a is a clock phase comparator, 8 is a digital phase comparator, 9a is a phase comparison signal synthesizer, 10 is a first periodic signal generator, 11 is a second periodic signal generator, 12 is It is a comparator. A is an input signal, b is a synchronization signal, c is a positive stuff threshold signal, d
Is a difference signal between write timing and read timing to the elastic store 3, e is a stuffable timing signal, f is a positive stuff request signal, g is a negative stuff request signal, h is a negative stuff threshold signal, and i is an elastic stuff threshold signal. A difference signal between a write address and a read address for the store 3 and j represents a phase difference signal between a write clock and a read clock for the elastic store 3.

Next, the operation of the first embodiment shown in FIG. 1 will be described with reference to FIGS. In the clock regenerator 1, a clock component is extracted from the asynchronous input signal a,
Elastic store 3 synchronized with asynchronous input signal a
Generate a write clock to The write address generator 2 divides the frequency of the write clock to generate a write address for the elastic store 3. The asynchronous input signal a is sequentially written to the elastic store 3 in accordance with the write address. The timing generator / controller 5 outputs a read clock from the elastic store 3 and a stuff signal. The read address generator 6 divides the frequency of the read clock to generate a read address from the elastic store 3. The contents of the elastic store 3 are read in the order in which they were written in accordance with the read address. The multiplexer 4 combines the signal read from the elastic store 3 and the stuff signal to generate a synchronization signal b.

The clock phase comparator 7a compares the phase of the write clock to the elastic store 3 with the phase of the read clock from the elastic store 3, and detects the time difference between the rising edges of the two clocks. The result of the phase comparison is output as a signal j proportional to the phase difference between the write clock and the read clock. The phase difference between the write clock and the read clock fluctuates in a sawtooth manner, and the frequency of the change is equal to the frequency difference between the write clock and the read clock. In the digital phase comparator 8, a phase comparison between the write address to the elastic store 3 and the read address from the elastic store 3, that is, a comparison between the write address and the read address represented by a binary number, is performed. Is output as the difference between the write address and the read address represented by. In the phase comparison result synthesizer 9a, the phase difference signal j between the write clock and the read clock output from the clock phase comparator 7a and the difference signal i between the write address and the read address output from the digital phase comparator 8 are calculated. The signal is synthesized and a difference signal d between the write timing and the read timing for the elastic store 3 is obtained. As in the conventional example, when the stuff operation is not performed as shown in FIG. 6A, the difference between the write timing and the read timing changes in a sawtooth shape. Although not shown, when the write clock is slower than the read clock, the phase difference decreases, and the output voltage signal j fluctuates in a saw-tooth shape having a slope falling to the right.

In this example, the first periodic signal generator 10 generates a sawtooth signal as a positive stuff threshold signal c having a constant period as shown in FIG.
Note that the positive stuff threshold signal needs to be a continuous signal at least partially in its cycle. In the comparator 12, the value of the difference signal d between the write timing and the read timing, which is the output of the phase comparison result synthesizer 9a,
Is compared with the value of the positive stuff threshold signal c which is the output of the periodic signal generator 10 of FIG. When the read phase advances with respect to the write phase, that is, when the phase difference decreases, the value of the output signal d of the phase comparison result synthesizer 9a decreases. If the value of the output signal d of the phase comparison result synthesizer 9a is smaller than the value of the positive stuff threshold signal c which is the output signal of the first periodic signal generator 10, the positive stuff which is the output of the comparator 12 It is assumed that the request signal f has a positive stuff request. That is, the positive stuff determination is performed based on the positive stuff threshold signal c. The second periodic signal generator 11 periodically generates a negative stuff request signal g which always indicates a negative stuff request regardless of the timing condition of the elastic store 3.

In the timing generation / control circuit 5, when there is a positive stuff request which is the output of the comparator 12, the read clock is controlled to delay the read phase from the elastic store 3 by one bit, I do. Since the read phase is delayed, the difference between the write timing and the read timing increases, and the value of the output signal d of the comparison result synthesizer 9a increases, so that the positive stuff request output from the comparator 12 is released. on the other hand,
In the timing generation / control circuit 5, when there is a negative stuff request which is the output of the second periodic signal generator 11,
The read clock is controlled, the read phase from the elastic store 3 is advanced by one bit, and negative stuff is performed.
Since the read phase is advanced, the difference between the write timing and the read timing is reduced, and the comparison result synthesizer 9a
Also becomes smaller.

In the positive / negative stuff synchronization system according to the first embodiment, the speed of the asynchronous input signal a, that is, the frequency of the write clock to the elastic store 3 synchronized with the asynchronous input signal a is slightly higher than the frequency of the read clock. FIG. 2 shows a signal of a main part when the signal is high. The horizontal axis represents time, and the vertical axis represents the magnitude of the difference between the write timing and the read timing for the elastic store 3 by voltage.
Here, the output signal c of the first periodic signal generator 10, which is a positive stuff threshold signal, is a continuous saw-tooth signal having a slope rising to the right as shown in FIG. Eight times the period of the timing signal e, and
The amplitude is made equal to the amount of change in the value of the output signal d of the phase comparison result synthesizer 9a with respect to the amount of change in the difference between the write timing and the read timing due to one stuff operation. That is, the positive stuff threshold signal c has a sawtooth shape that continuously changes at a cycle eight times the cycle of the stuff enable timing signal e, and has an amplitude of one clock. Also,
The period in which the negative stuff request signal g generated in the second periodic signal generator 11 is determined to have a negative stuff request is equal to the output signal of the first periodic signal generator 10 and is eight times the period of the stuff enable timing signal e. Period. Further, the time required for the difference between the write timing to the elastic store 3 and the read timing to change by one write clock is set to 80 times the cycle of the stuff enable timing signal e.

In FIG. 2, since the frequency of the write clock to the elastic store 3 is slightly higher than the frequency of the read clock, the difference between the write timing and the read timing gradually increases. Accordingly, the output of the phase comparison result synthesizer 9a, that is, the difference signal d between the write timing and the read timing to the elastic store 3
Rises to the right. At the point A, since the phase difference signal d becomes smaller than the positive stuff threshold signal c, the positive stuff is performed at the stuffable timing immediately thereafter.
The positive stuff increases the phase difference by one clock. B
At this point, the negative stuff is performed by the negative stuff request signal g generated in the second periodic signal generator 11. The negative stuff reduces the phase difference by one clock. Thereafter, the same operation is performed, and the positive stuff and the negative stuff are alternately performed. After the negative stuff is performed at the point C by the negative stuff request signal g, the negative stuff is also performed at the point D. Therefore, while the difference between the write timing and the read timing changes by one write clock,
The number of times the negative staff is executed
One time more than the number of times. Further, the variation range of the difference between the write timing and the read timing is substantially between the maximum value of the negative stuff threshold signal and the minimum value of the positive stuff threshold signal.

In the stuff synchronization method of the first embodiment, the period is 80 times the cycle of the stuff enable timing signal e, that is, while the difference between the write timing to the elastic store 3 and the read timing changes by one write clock. Nine positive stuffs are performed nine times and negative stuffs are performed ten times at substantially equal intervals, and stuffing is performed in a cycle shorter than the stuffing cycle in the stuff synchronization method having a fixed positive / negative stuff threshold. While the difference between the write timing to the elastic store 3 and the read timing changes by the amount of change due to one stuff operation, the negative stuff is constant due to the negative stuff request output from the second periodic signal generator 11. It is performed in a cycle, and the positive stuff, one less than the negative stuff, is performed almost equally. Accordingly, in the stuff synchronization method of the present invention, the frequency of the destuff jitter is increased, and thus the PLL can be sufficiently suppressed. In other words, the low frequency component of the destuff jitter is converted to a frequency higher than the low cutoff frequency of the easily configured low-pass filter. When the positive stuffing is performed, the phase difference is increased by one clock, and when the negative stuffing is performed, the phase difference is reduced by one clock. Therefore, the actual phase over which the difference between the writing timing and the reading timing changes by one writing clock is changed. The amount of variation is one clock, and is equal to the amount of phase variation in the stuff synchronization scheme having a fixed positive / negative stuff threshold.

Embodiment 2 FIG. FIG. 3 is a configuration block diagram showing a second embodiment of the positive / negative stuff synchronization system according to the second aspect. FIG. 4 is a diagram for explaining the operation of FIG. 3 differs from FIG. 1 in that the output signal of the first periodic signal generator 10 is a negative stuff threshold signal h, the output signal of the second periodic signal generator 11 is a positive stuff request signal f, Table 12
Is the negative stuff request signal g,
Others are the same as FIG. FIG. 4 shows essential signals when the speed of the asynchronous input signal a, that is, the frequency of the write clock to the elastic store 3 synchronized with the asynchronous input signal a is slightly higher than the frequency of the read clock.
Here, as shown in FIG. 4A, the negative stuff threshold signal h which is the output signal of the first periodic signal generator 10 is output.
Is a continuous saw-tooth shape having a downward slope, the cycle is set to eight times the cycle of the stuffable timing signal e, and the amplitude is determined by the amount of change in the difference between the write timing and the read timing by one stuff operation. The amount of change in the value of the output signal d of the phase comparison result combiner 9a is made equal to the output signal h of the first periodic signal generator 10 as described above, and negative stuff determination is performed using the negative stuff threshold value. Further, the second periodic signal generator 11 generates a positive stuff request signal f which always has a positive stuff request with a period equal to the output signal of the first periodic signal generator 10. In the positive / negative staff synchronization method of the second embodiment,
80 times the period of the stuff enable timing signal e,
In other words, the positive stuff is performed 10 times and the negative stuff is performed 11 times at substantially equal intervals while the difference between the write timing and the read timing for the elastic store 3 changes by one write clock, which is the same effect as in the first embodiment. Is obtained.

Embodiment 3 FIG. In the first and second embodiments of the positive / negative stuff synchronization system of the present invention, the example in which the stuff control means uses the first periodic signal generator 10 and the second periodic signal generator 11 has been described. By making the signal periods equal, the output signal of one periodic signal generator can be shared, and the configuration is simplified. Furthermore, in the above embodiment, an example was described in which an independent clock source of the periodic signal generator was used as the clock source of the periodic signal.
The clock for writing to or reading from the elastic store can be used as the clock source,
The configuration can be simplified.

Embodiment 4 FIG. In the first and third embodiments of the positive / negative stuff synchronization system of the present invention, the stuff control means fixes the negative stuff request signal g output from the second periodic signal generator 11 and having a stuff request at a constant cycle. When the difference between the timing of writing to the elastic store 3 and the timing of reading is larger than the above threshold, the negative stuff is continuously executed to provide the threshold. Even when the difference is remarkably large, an appropriate timing difference can be quickly obtained.

Embodiment 5 FIG. In Embodiments 2 and 3 of the positive / negative stuff synchronization system of the present invention, the stuff control means fixes the positive stuff request signal f, which is output from the second periodic signal generator 11 and has a stuff request at a constant period, to the stuff request. When the difference between the timing of writing to the elastic store 3 and the timing of reading is smaller than the above threshold value, the configuration is such that the normal stuff is executed continuously, thereby providing the above threshold value. Even when the difference is extremely small, an appropriate timing difference can be quickly obtained.

Embodiment 6 FIG. In the first and third embodiments of the positive / negative stuff synchronization system of the present invention, the stuff control means fixes the negative stuff request signal g output from the second periodic signal generator 11 and having a stuff request at a constant cycle. When the difference between the write timing to the elastic store 3 and the read timing is smaller than the threshold value, the second periodic signal generator is configured not to execute the negative stuff. It is possible to promptly set an appropriate timing difference without performing unnecessary staffing in response to a staff request from 11 and further reducing the timing difference.

Embodiment 7 FIG. In Embodiments 2 and 3 of the positive / negative stuff synchronization system of the present invention, the stuff control means fixes the positive stuff request signal f, which is output from the second periodic signal generator 11 and has a stuff request at a constant period, to the stuff request. When the difference between the write timing to the elastic store 3 and the read timing is larger than the threshold value, the second periodic signal generator is configured not to execute the positive stuffing. It is possible to promptly set an appropriate timing difference without further increasing unnecessary the above-mentioned timing difference by performing unnecessary staff in response to a staff request from 11.

In the first to seventh embodiments, the transmission side of the positive / negative stuff synchronization system has been described. However, the reception side can be realized with the same configuration as that of the stuff synchronization system having a fixed stuff threshold. .

[0029]

As described above, according to the first, second, and third aspects of the present invention, with a simple configuration, the destuffed jitter of the recovered clock on the receiving side can be reduced, and variations and variations in element characteristics are reduced. And a positive / negative stuff synchronization system with a small circuit size and low power consumption can be obtained. Further, according to the inventions according to the fourth and fifth aspects,
In addition to the effects of the inventions according to the second and third aspects, when the difference between the write timing to the elastic store and the read timing is extremely large and extremely small, respectively, the appropriate timing difference can be quickly obtained. According to the sixth and seventh aspects of the present invention, in addition to the effects of the first, second and third aspects, the difference between the timing of writing to the elastic store and the timing of reading the elastic store is fixed. When the difference is smaller than the threshold value or when the difference is larger than the fixed threshold value provided, the difference between the timings can be promptly determined.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of a positive / negative stuff synchronization system according to the present invention.
FIG. 3 is a block diagram showing the configuration.

FIG. 2 is a diagram illustrating the operation of FIG.

FIG. 3 shows a positive / negative stuff synchronization system according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration.

FIG. 4 is a diagram for explaining the operation of FIG. 3;

FIG. 5 is a configuration block diagram showing a conventional stuff synchronization method.

FIG. 6 is a diagram illustrating the operation of FIG.

FIG. 7 is a diagram illustrating the operation of FIG.

[Description of Signs] 1 Clock regenerator 2 Write address generator 3 Memory unit (elastic store) 4 Synthesizing unit (multiplexer) 5 Timing generator / controller 6 Read address generator 7a Bit phase comparator 8 Digital phase comparator 9a Phase comparison signal synthesizer 10 periodic signal generator 11 periodic signal generator 12 comparator 20 write control means 21 read control means 22 stuff control means a asynchronous input signal b synchronization signal c positive stuff threshold signal d phase difference signal e Stuffable timing signal f Positive stuff request signal g Negative stuff request signal h Negative stuff threshold signal i Difference signal between write address and read address j Phase difference signal between write clock and read clock

Claims (7)

(57) [Claims] An asynchronous digital signal input signal is temporarily stored in a stuff-synchronous transmission side for synchronizing and transmitting an asynchronous digital signal and receiving the synchronized digital signal to reproduce an original asynchronous digital signal. A memory unit; write control means for sequentially writing the input signal to the memory unit; read control means for reading the input signal in the order in which the input signals are written from the memory unit; and synchronization with a reproduction clock extracted from the asynchronous digital signal A stuff control means for executing a positive / negative stuff in accordance with a frequency difference between signal clocks; and a synthesizing means for synthesizing the signal read from the memory unit and the positive / negative stuff signal to output a synchronized digital signal. It is assumed that the stuff control means always generates a negative stuff request signal at a constant cycle. Then, the phase difference between the recovered clock extracted from the asynchronous digital signal and the clock of the synchronization signal is detected, the magnitude is compared with a threshold signal having a fixed period, and a positive stuff request signal is generated. Positive / negative stuff synchronization method characterized by executing positive / negative stuff. 2. A stuff control means which constantly generates a positive stuff request signal at a constant period, detects a phase difference between a reproduction clock extracted from an asynchronous digital signal and a clock of a synchronization signal, and detects the magnitude of the phase difference. 2. The method according to claim 1, further comprising: comparing a predetermined periodic signal with a threshold value; generating a negative stuff request signal;
The positive / negative staff synchronization method described. 3. The positive / negative stuff synchronization according to claim 1, wherein a cycle of the stuff control means for generating the stuff request signal coincides with a cycle of the threshold periodic signal. method. 4. A stuff control means for setting a fixed threshold value for a negative stuff request signal which is always generated at a fixed period, and a phase difference between an asynchronous digital signal and a signal to be synchronized is determined. 2. The method according to claim 1, wherein when the value is larger than the threshold value, the negative stuff is executed continuously.
Alternatively, the positive / negative stuff synchronization method according to claim 3. 5. The stuff control means sets a fixed threshold value for a positive stuff request signal which is always generated at a constant cycle, and determines a magnitude of a phase difference between an asynchronous digital signal and a signal to be synchronized. 3. The method according to claim 2, wherein when the value is smaller than the threshold value, the main stuff is executed continuously.
Alternatively, the positive / negative stuff synchronization method according to claim 3. 6. A stuff control means for setting a fixed threshold value for a negative stuff request signal which is always generated at a constant period, and a magnitude of a phase difference between an asynchronous digital signal and a signal to be synchronized is determined. 4. The positive / negative stuff synchronization method according to claim 1, wherein the negative stuff is not executed when the threshold value is smaller than the threshold value. 7. The stuff control means sets a fixed threshold value for a positive stuff request signal which is always generated at a constant period, and determines a magnitude of a phase difference between an asynchronous digital signal and a signal to be synchronized. 4. The positive / negative stuff synchronization method according to claim 2, wherein the positive stuff is not executed when the threshold value is larger than the threshold value.