JPH04365285A - Time base corrector - Google Patents

Abstract

PURPOSE:To suppress the horizontal compression and extension of images by providing a follow-up clock generation circuit equipped with a phase control circuit composed of a voltage controlled oscillator (VCO), phase detector, phase selector and delay equipment. CONSTITUTION:A follow-up clock generator 5 is equipped with a voltage generator 51 to generate plural voltage levels, a selector 52 to select the voltage level inputted from the voltage generator 51 according to a reproducing control signal C, a VCO 53 to control the frequency at the voltage level outputted from the selector 52, delay equipment 54, phase detector 55 and phase selector 56. The selector 52 selects the voltage level to control the frequency of the VCO 53 so as to satisfy a fixed condition from the plural voltage levels inputted from the voltage generator 51 while being controlled by the reproducing control signal C as a signal showing the reproducing direction and reproducing speed of a magnetic recording device (VTR). Therefore, the horizontal scan frequency of a regenerative signal is almost coincident with the frequency of a clock CK outputted by the follow-up clock generator 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis corrector, and more particularly to a time axis corrector that supplies a reference signal for a servo system of a magnetic recording apparatus (hereinafter referred to as a VTR).

0002

2. Description of the Related Art A time axis corrector is a function for correcting time axis fluctuations due to VTR jitter and maintaining the image quality of reproduced images.

Conventional time base correctors (TBCs) of this type include, for example, "time base collectors for consumer VTRs";
This is reported in the Technical Report of the Television Society of Japan, Volume 13, 1989, No. 38, pages 17 to 22, and its configuration is shown in FIG.

In FIG. 3, the conventional time axis corrector has an A/D converter 1 which inputs the reproduced signal R, a memory 2 which inputs the output of the A/D converter 1, and an output of the memory 2. A D/A converter 3 as an input, a synchronous separator 4 as an input, a synchronous separator 4 as an input, a follow-up clock generator 9 as an input, a reference clock generator 7, and a reference clock as an input. A synchronous generator 8 receives the output of the generator 7 as an input, and a memory controller 6 receives the outputs of the follow-up clock generator 9 and the reference clock generator 8 as inputs,
The output of the memory control 6 was used as the control input of the memory 2, the output of the D/A converter 3 was outputted with time base correction (hereinafter referred to as TBC), and the reference V was outputted from the synchronization generator 8.

[0005] Here, an example of the configuration of the follow-up clock generator 9 is shown in FIG. In FIG. 5, the tracking clock generator 9 includes an oscillator 93, a delay device 54 which receives the output of the oscillator 93, a phase detector 55 which receives the output S of the synchronous separator 4 and the output of the delay device 54, and a phase detector 55 which receives the output S of the synchronous separator 4 and the output of the delay device 54. Output of detector 55 and delay device 5
4, and the output of the phase selector 56 is used as the output CK of the follow-up clock generator 9.

Next, the operation of the conventional time base corrector will be explained.

The input reproduced signal R is converted into a digital signal by an A/D converter 1 and written into a memory 2. The memory 2 functions as a suitable variable delay element depending on the write clock and read clock output from the memory control 6. Then, by converting the digital signal outputted from the memory 2 back to an analog signal using the D/A converter 3, a signal having a different time axis from that of the reproduced signal can be obtained.

Here, as a method of obtaining a signal corrected for the time axis error included in the reproduced signal as the TBC output, a clock that follows the time axis error included in the reproduced signal is used as the write clock of the memory 2, and a constant frequency is used. It is known to use the clock as the read clock for the memory 12. Therefore, the synchronization separator 4 separates the horizontal synchronization signal S from the reproduction signal R, and outputs this as a reference for the time axis error included in the reproduction signal. A follow-up clock generator 9 generates a clock CK that follows the output of the synchronous separator 4, and uses this as a write clock for the memory 2 via a memory control 6.

On the other hand, the reference clock generator 7 generates a clock of a constant frequency and uses it as a read clock for the memory 2 via the memory control 6. With the above, the time axis correction function is realized.

In the follow-up clock generator 9, the oscillator 93 first generates a clock of a constant frequency, and the delay device 54 generates a plurality of clocks by delaying the clock by a constant amount. These can be considered as multiple clocks with constant frequencies but different phases. Then, the phase detector 55 compares the phases of these clocks and the output of the synchronous separator 4, and the phase selector 55 selects and outputs the clock having the closest phase. (Hereinafter, such a follow-up clock generator will be referred to as a phase-selective type.) Another method for configuring the follow-up clock generator 9 is to use a phase-locked loop (hereinafter, this will be referred to as a phase-locked loop type). A method is used in which oscillation/stop of an oscillator is controlled by the output of a synchronous separator or a synchronous separator (hereinafter referred to as an oscillation/stop type). By the way, by generating the reference V from the read clock of the memory 2 and feeding it back as a phase reference signal for the drum servo, the average frequency of the write clock and the read clock of the memory 2 are synchronized, and the memory 2 has a memory amount of more than a certain amount. It is known that if there is such an effect, writing and reading will not be overtaken or overtaken.

Therefore, in the time axis corrector shown in FIG.
The synchronization generator 8 generates a reference vertical synchronization signal (VR), which is fed back to the drum servo to control the average frame frequency of the reproduced signal.

[0012] VTR generally used for quick reviews etc.
During high-speed reproduction, the number of lines within one frame of the reproduced signal changes. For example, in the case of an NTSC signal, the number of lines L is expressed by the following equation, where n is a multiple of the normal playback speed.

[0013] L≒262.5-(n-1)
(Book) For example, if n = 10, the ratio of the number of lines in one frame during high-speed playback and normal playback is 0.9
This is a 96-fold increase, which corresponds to a change of about 3.4%.

[0014]

[Problems to be Solved by the Invention] In the above-described conventional time axis corrector, the horizontal scanning frequency of the reproduced signal during high-speed reproduction is different from the frequency of the clock output by the follow-up clock generator. There was a problem in that the images were compressed or expanded in the horizontal direction.

[0015]

[Means for Solving the Problems] The time axis corrector of the present invention includes a memory circuit that stores a digital playback signal obtained by converting a playback signal from a magnetic recording device into an analog-to-digital format, and a memory circuit that stores the playback direction and playback speed of the playback signal. a clock generation circuit that generates a clock having a frequency controlled by a reproduction control signal that is a signal indicating the horizontal A tracking clock generation circuit that generates a tracking clock that follows the phase of a synchronization signal, and a reference clock generation circuit that generates a reference clock of a predetermined frequency, the digital reproduction using the tracking clock as a write clock of the memory circuit. The signal is stored in the memory circuit, and the digital reproduction signal stored in the memory circuit is read out using the reference clock as a readout clock, thereby correcting the time axis of the reproduction control signal.

[0016]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the time base corrector of the present invention.

As shown in FIG. 1, the time axis corrector of this embodiment includes an A/D converter 1, a memory 2, and a D/A converter 3.
, a synchronous separator 4 , a follow-up clock generator 5 , a memory control 6 , a reference clock generator 7 , and a synchronous generator 8 . Among the above-mentioned components, the components are the same as those of the prior art example described above, except that the follow-up clock generator 5 is replaced with the follow-up clock generator 9 of the prior art example, and therefore, their operations are also the same.

As shown in FIG. 2, the follow-up clock generator 5 includes a voltage generator 51 that generates a plurality of voltage levels, and a selector that selects the voltage level input from the voltage generator 51 based on a reproduction control signal C. 52, and a voltage controlled oscillator whose frequency is controlled by the voltage level output from the selector 52 (
VCO) 53, a delay device 54 similar to the conventional example, a phase detector 55, and a phase selector 56.

Next, the operation of this embodiment will be explained.

The reproduction control signal C is a signal indicating the reproduction direction and reproduction speed of the VTR. For example, if the playback direction is forward, it is represented by a positive sign, and if it is backward, it is represented by a negative sign, and a digital value indicating a multiple n of the normal playback speed is used as the playback control signal C. The selector 52 is controlled by the reproduction control signal C and selects a voltage level from among the plurality of voltage levels input from the voltage generator 51 to control the frequency of the VCO 53 so as to satisfy the following conditions. That is, control is performed so that the frequency fn when the reproduction speed is n is as shown in the following equation with respect to the frequency f1 when the reproduction speed is normal (n=1).

fn={262.5−(n−1)/262.5} As a result, the horizontal scanning frequency of the reproduced signal and the frequency of the clock CK output from the follow-up clock generator 5 almost match.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments and can be modified in various ways. For example, in this embodiment, a desired voltage level is selected from a plurality of voltage level inputs using a reproduction control signal, and
Although the phase-selective type that controls the CO has been described, it goes without saying that a phase-locked type that uses a phase-locked loop can also be applied as long as it does not depart from the spirit of the present invention.

[0024]

As explained above, the time axis corrector of the present invention can make the clock frequency almost match the horizontal scanning frequency of the reproduced signal using the reproduction control signal indicating the reproduction direction and reproduction speed. This has the effect of suppressing compression or expansion of the image in the horizontal direction due to the correction output signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a time base corrector of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a follow-up clock generator of the time axis corrector according to the present embodiment.

FIG. 3 is a block diagram showing an example of a conventional time base corrector.

FIG. 4 is a block diagram showing a configuration example of a follow-up clock generator of a conventional time axis corrector.

[Explanation of symbols]

1 A/D converter 2. Memory 3 D/A converter 4 Sync separator 5,9 Tracking clock generator 6. Memory control 7. Reference clock generator 8 Synchronization generator 51 Voltage generator 52 Selector 53 VCO 54 Delay device 55 Phase detector 56 Phase selector 93 Oscillator

Claims (1)

[Claims] 1. A memory circuit that stores a digital playback signal obtained by converting a playback signal from a magnetic recording device into an analog-to-digital format, and a memory circuit that stores a digital playback signal obtained by converting a playback signal from a magnetic recording device into an analog-to-digital format. A tracking circuit that generates a tracking clock that follows the phase of the horizontal synchronization signal, comprising a clock generation circuit that generates a clock and a phase control circuit that controls the phase of the clock to match the phase of a horizontal synchronization signal that is synchronously separated from the reproduced signal. a clock generation circuit; and a reference clock generation circuit that generates a reference clock with a predetermined frequency; stores the digital reproduction signal in the memory circuit using the follow-up clock as a write clock of the memory circuit; A time axis corrector, characterized in that the time axis of the reproduction control signal is corrected by reading out the digital reproduction signal stored in the memory circuit as a read clock.