JP2630871B2 - Video signal time base correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for correcting fluctuations of a reproduced signal in a time axis direction when reproducing a video signal in a magnetic recording / reproducing apparatus such as a video tape recorder (hereinafter referred to as VTR). is there.

[0002]

2. Description of the Related Art In a magnetic recording / reproducing apparatus such as a VTR, a reproduced video signal undergoes a time axis fluctuation due to factors such as uneven running of a tape running system and expansion and contraction of a tape. (Jitter).
As a method of correcting the time base fluctuations, (hereinafter referred to as TBC) de _Lee digital time base collector circuit is employed.

FIG. 2A is a principle diagram of a time axis correction circuit, and FIG. 2B is a schematic diagram for explaining signal correction. In the figure, de the _y digital TBC, the ADC1 to convert the reproduced video signal to the de _Lee digital signal, a memory 2 for storing該De _Lee digital signal, a horizontal sync separator for separating a horizontal synchronizing signal of the reproduced video signal 3, a clock pulse generating circuit 4 for generating a sampling clock for the ADC 1 using the horizontal synchronization signal, a write pulse generating circuit 6 for generating a write pulse for a memory control circuit 5 for controlling writing to the memory 2, de _Lee digital signal stored in the memory 2 is converted into an analog signal, and DAC7 to be corrected output of the fluctuation, the memory control circuit 5 from the oscillation frequency of the fixed cycle of the local oscillator 8
And a read clock pulse generating circuit 9 for generating a read clock pulse for controlling the DAC 7. Incidentally, reference numerals 10 and 11 are an input terminal and an output terminal of the reproduced video signal, respectively.

[0004] The circuit configuration described above, the reproduced video signal S ₀ with irregular H (horizontal sync period) as shown in FIG. 2 (b), the output signals S ₁ of the TBC circuit having a standard 1H
Then, a reproduced video signal whose time axis has been corrected is obtained at the output terminal 11. Therefore, the performance of the TBC circuit is
It is determined depending on how the clock written to the memory corresponds to the time axis fluctuation of the reproduced video signal. In general, a PLL (Phase Lo
cked Loop) and FF (Feed Forward) methods are awarded.

FIG. 3A is a block diagram of a clock generating circuit of the PLL system, and FIG. 3B is an equivalent circuit diagram thereof. In the figure, a reproduced video signal input from an input terminal 10 is separated into a synchronization signal by a horizontal synchronization separation circuit 3 and is input to a phase comparison circuit 12 at the next stage. Then LPF (Low
After the high frequency components are removed by the Pass Filter 13 and the waveform is shaped, the VCO (Voltage Control Oscillator) 1
Modulate the oscillation frequency of 4. After the output signal of the VCO 14 is frequency-divided by the frequency dividing circuit 15, it is fed back to the phase comparing circuit 12 and compared with the horizontal synchronizing signal. Therefore, VCO14
Then, a clock pulse including a time axis fluctuation component included in the original reproduced video signal is output to the output terminal 16.

The transfer function of the phase error indicating the phase tracking characteristic of the above-described PLL clock pulse generating circuit is shown in FIG.
As shown in (b), it becomes a first-order lag function and depends on the transfer function F (s) of the LPF 13. In the figure, F (s) is LPF
13 is a transfer function, kd is a conversion gain coefficient (V / rad) of the phase comparison circuit 12, and ko is a conversion gain coefficient (rad / vs) of the VCO 14.
It is. Now, the phase error theta _e; the phase of the reproduced video signal theta _i; When the phase of the feedback signal and _{θ o, θ e = θ i} -θ o

[0007]

(Equation 1)

[0008]

(Equation 2)

In general, the LPF deteriorates in the high frequency band as compared with the transfer characteristic in the low frequency band. As a result, as shown in FIG. Disappears. Therefore, although the phase at the time of writing to the memory with respect to the low frequency component in the PLL system follows the time axis fluctuation of the reproduced video signal, the phase at the time of writing with respect to the high frequency component becomes unstable. Has disadvantages. (For general 1K _HZ or more frequency components, the action of the TBC becomes impossible.) Next, the FF mode clock pulse generating circuit will be described with reference to FIG. The FF method is a method for compensating for the deterioration of the phase following characteristic of the clock pulse with respect to the high frequency components in the PLL method. The basic clock pulse generated by the local oscillator 17 is passed through a delay tap circuit 18 composed of a plurality of delay elements, whereby n delayed clocks are generated and input to the latch circuit 19. The latch circuit 19 latches n delayed clock pulses with the horizontal synchronizing signal separated from the reproduced video signal. The latched clock pulse detects a change (High or Low) of the clock pulse latched by the selection signal generation circuit 20, and generates a control signal. The n delayed clock pulses are also input to the clock selection switch circuit 21, and the control signal from the selection signal generation circuit 20 causes the clock selection switch circuit 21 to output the first of the n delayed clocks as the horizontal synchronization signal. One nearby delayed clock pulse is selectively output. FIG.
(B) shows a time chart of the signal of each part.

In this FF system, since a logic circuit can be used, a write clock pulse corresponding to the time axis fluctuation of the reproduced video signal can be obtained. correction (Beroshite _Lee Era correction) can not.

[0011]

The TBC circuit has a problem that the frequency response characteristic in the high frequency range in the PLL system employed in the above-mentioned write clock generation circuit is deteriorated, and the FF system cannot cope with the fluctuation of the time axis within 1H in the TBC circuit. Performance degradation 1
There are two factors. The present invention provides a circuit for solving the above problems.

[0012]

A time axis correction circuit for controlling a sampling clock of an A / D converter and a writing clock to a memory using a horizontal synchronizing signal of a reproduced video signal. First zero-order hold means for holding the time axis fluctuation during the horizontal synchronization period of
The hold signal of the second zero-order hold means for holding the time axis fluctuation of the horizontal synchronization period after delaying the reproduced video signal by 1H (H; horizontal synchronization period), and the hold signals of the first and second zero-order hold means are linearized. A first hold signal, a second zero-order hold signal and the first hold signal, and a VCO (voltage controlled oscillator) for generating a first clock signal using the added signal as a control voltage. ), And a predetermined write clock signal is obtained from the first clock signal via an FF (feed forward) type clock signal generating means including a plurality of delay elements.

[0013]

[Action] the construction described above, the time axis variation amount contained in the horizontal synchronizing signal of the reproduced video signal, i.e. to obtain a control voltage having a Beroshite _Lee Era, responsive to the voltage controlled time base variation of the VCO in the control voltage Obtained clock pulse. The clock pulses by passing the clock pulse generating circuit of the FF scheme, a write clock pulse including a time base fluctuation in 1H is created, a time axis correction by de _Lee digital TBC is performed.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
FIG. 1 is a circuit block diagram of the present invention. In the figure, the same parts as those of the conventional example are denoted by the same reference numerals, and description thereof will be omitted. In the figure, 22 is a 1H delay circuit, 23 is a horizontal sync separation circuit, 24 and 25 are first and second zero-order hold circuits, 26 is a primary hold circuit, 27 is an adder circuit, and 28 is a VC.
An O circuit, 29 is a trapezoidal wave generation circuit, and 30 is a servo phase circuit.

A horizontal synchronizing signal is generated by the horizontal synchronizing / separating circuit 3 from the reproduced video signal input from the input terminal 10 and is input to the first zero-order hold circuit 24. Further, after the reproduced video signal is delayed by the 1H delay circuit 22, the horizontal synchronization signal is separated by the horizontal synchronization separation circuit 23 and input to the second zero-order hold circuit 25. These two horizontal synchronizing signals are used as sample signals, and the first and second zero-order hold circuits 2 are used, respectively.
At 4 and 25, the time axis fluctuation is held DC. Said 0
The reference signal applied to the next hold circuits 24 and 25 is a trapezoidal wave signal created by the trapezoidal wave creation circuit 29 based on the basic clock signal generated by the local oscillator 17.

The basic clock signal of the local oscillator 17 is also the basis of a read clock signal and a synchronizing signal of the read clock signal, and defines the phase relationship between the zero-order hold circuits 24 and 25. The hold signals of the 0-order hold circuits 24 and 25 are input to the primary hold circuit 26, respectively, and
The change of the fluctuation amount during the period is approximated to a primary straight line and held (primary hold). In other words, this primary hold signal corresponds to the AC component of the time axis fluctuation every 1H.

A 0th-order hold signal (output signal of the second 0th-order hold circuit 25) which is a DC component of a time axis variation for each 1H
When By Type addition and calculating an output signal of the first-order hold circuit 26 to the adding circuit 27, the time base variation signal including time base fluctuations in 1H (Beroshite _b Era) is obtained.
Using the time axis fluctuation signal as a control signal, the next VC
By controlling the oscillation frequency of the O circuit 28, the oscillation frequency is converted into an FM signal.

By using the clock pulse output from the VCO circuit 28 as an input clock pulse to the above-mentioned FF system clock pulse generating circuit, a VCO clock delay pulse which is temporally closest to the horizontal synchronizing signal can be obtained. The clock delay pulse can be used as a write clock pulse for the memory control circuit 5. The FF system clock pulse generation circuit is as described above, but again, the delay tap circuit 18 and the latch circuit 1
9, a selection signal generation circuit 20 and a clock pulse selection switch circuit 21. The latch timing to the latch circuit 19 is performed in the cycle of the horizontal synchronization signal after a 1H delay.

[0019] de _Lee digital TBC circuit of the present invention, the reproduced video signal after delayed by 1H, and enter into the ADC circuit 1,
Converts an analog signal to the de _Lee digital signal,
A conventional example (FIG. 2) uses a 1H delay reproduction video signal.
See).

[0020]

By adopting the write clock pulse generating circuit of the present invention, the phase tracking characteristic with respect to the frequency fluctuation in the high frequency band can be improved, and the fluctuation of the time axis within 1H can be corrected. A high-performance time axis correction circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of the present invention.

FIG. 2 is a circuit block diagram and a diagram for explaining time axis correction of a conventional example.

FIG. 3 is a circuit block diagram and an equivalent circuit diagram of a conventional example, and a frequency-to-phase error characteristic diagram thereof.

FIG. 4 is a circuit block diagram of another conventional example and a time chart of a waveform of each part thereof.

[Explanation of symbols]

1 ADC (Analog Devices _y digital converter) 2 memory circuit 3 horizontal sync separator 5 the memory control circuit 7 DAC (digital-to-analog converter) 18 delay tap circuit 19 latch circuits 20 select signal generating circuit 21 a clock selection switch circuit 22 1H delay element 23 Horizontal sync separation circuit 24 First zero-order hold circuit 25 Second zero-order hold circuit 26 Primary hold circuit 27 Adder circuit 28 VCO (voltage controlled oscillator)

Claims (2)

(57) [Claims] 1. A time axis correction circuit for controlling a sampling clock of an A / D converter and a writing clock to a memory using a horizontal synchronization signal of a reproduced video signal, wherein the horizontal synchronization of the reproduced video signal is controlled. First zero-order hold means for holding a time-axis variation of a period, and second zero-order hold means for holding a time-axis variation of a horizontal synchronization period after a 1H (H; horizontal synchronization period) delay of the reproduced video signal. Primary hold means for linearly holding the hold signals of the first and second zero-order hold means, adder means for adding and calculating the second zero-order hold signal and the primary hold signal, A VCO (Voltage Controlled Oscillator) for generating a first clock signal using the addition signal as a control voltage, wherein the FF includes a plurality of delay elements for the first clock signal.
A video signal time axis correction circuit, wherein a predetermined write clock signal is obtained via a (feed forward) type clock signal generating means. 2. The FF system clock signal generating means,
A delay tap circuit including a plurality of delay elements, a clock selection switch circuit for selecting a delay signal of the delay tap circuit, a latch circuit for latching the delay signal, and the clock selection switch circuit using an output signal of the latch circuit. 2. The video signal time axis correction circuit according to claim 1, further comprising a selection signal generation circuit for controlling, wherein the latch circuit is latched at a leading edge or a trailing edge of the horizontal synchronization signal after the 1H delay.