JPH0267885A - Jitter cancel circuit - Google Patents

Abstract

PURPOSE:To correct jitter even in a high frequency by providing a delay means to delay by a prescribed quantity a video signal to be inputted to a time axis control means controlled by the output of a PLL circuit so as to compensate a phase delay in the high frequency of the follow-up of the PLL circuit. CONSTITUTION:A digital time base collector has a delay circuit 22, an A/D converter 10, a memory 12, D/A converter 14, a memory control circuit 16, a horizontal synchronization separating circuit 18 and a PLL circuit 20, and here, the memory 12 and the memory control circuit 16 constitute the time axis control means. Since an input video signal is given to the A/D converter 10 through the delay circuit 22, the input video signal is delayed by the delay circuit 22, inputted to the A/D converter 1 and the phase delay is generated. There, the delay quantity of the delay circuit 22 is set so as to cancel the phase delay of the follow-up characteristic of the PLL circuit 20. Thus, the jitter of a VTR reducing signal can be improved even in the high frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a jitter cancellation circuit in a video tape recorder (VTR), and particularly to a jitter cancellation circuit for a time base collector (VTR).
TBC) and color signal automatic phase control circuits (APC).

(Prior Art) Various circuits are known as circuits that cancel jitter components of video signals reproduced from a VTR.A digital time base collector that digitally processes video signals and cancels jitter by controlling memory is known. As an example, the fifth
As shown in the figure. This digital time base collector is an A/D
It has a converter 10, a memory 12, a D/A converter 14, a memory control circuit 16, a horizontal synchronization separation circuit 18, and a PLL circuit 20, and operates as follows.

Horizontal synchronization signal (H5V) containing jitter from the input video signal
nC) in the horizontal sync separation circuit 18, and then this H
In synchronization with H5ync, the sawtooth wave generator 20a in the PLL circuit 20 generates a sawtooth wave with an H5ync period (63.5 μsec). VCO20d of PLL20 is 4
f. (910 fH>), this signal is frequency-divided by 1/910 by the counter 20e, and this frequency-divided signal is given to the sample/hold circuit 20b to sample/hold the sawtooth wave. Sample/ The held signal passes through the loop filter 20C and becomes the control voltage of the VCO 20d.The PLL is configured in this way, and 4fsc, which is phase-locked to H5ync of the input video signal,
Generated at CO20d. This 4f. The signal contains a jitter component, and this signal is applied to the A/D converter 10 and the memory control circuit 16 and used as a write clock that is the timing for writing to the memory 12. Therefore, the A/D converted video signal is stored in the memory 12 with its jitter canceled. The stored data is read out using a stable read clock that does not contain jitter components and is applied to the D/A converter 14, resulting in a stable video signal with a corrected time base.

[Invention or problem to be solved]

In the digital time base collector shown in FIG. 5, jitter is improved as shown in FIG. 6. Furthermore, the sixth
Figure a shows the characteristics of the PLL.

As can be seen from the graph in Figure 6, the degree of jitter improvement in the high frequency range around 1 kHz is low, and even in the high frequency range 3.
~5 kHz2, the jitter is not improved and deteriorates.

Therefore, an object of the present invention is to provide a jitter canceling circuit that can improve the jitter of the reproduced signal even in high frequencies.

(Means and effects for solving the problems) In order to achieve the above object, the present invention provides means for controlling the time axis of a video signal according to the PLL circuit output in order to compensate for the phase delay in the tracking characteristics of the PLL circuit. A delay means is provided in the path for inputting the video signal.

That is, according to the present invention, there is provided a PLL circuit that responds to a horizontal synchronization signal or a color burst signal in a reproduced video signal of a VTR, and a time axis that controls the time axis of the reproduced video signal or its components in accordance with the output of the PLL circuit. There is provided a jitter cancellation circuit having a control means, characterized in that the jitter cancellation circuit is provided with a delay means for delaying the reproduced video signal or its components input to the time axis control means by a predetermined period of time.

(Example) An example of the present invention will be described below with reference to the drawings.
The figure is a block diagram showing a first embodiment of the jitter cancellation circuit of the present invention. This first embodiment is a digital time base collector similar to FIG. 5, and includes a delay circuit 22, an A/D
It has a converter 10, a memory 12, a D/A converter 14, a memory control circuit 16, a horizontal synchronization separation circuit 18, and a PLL circuit 20. Here, the memory 12 and the memory control circuit 16 constitute time axis control means.

That is, in the conventional circuit shown in FIG. There is. Therefore, the PLL circuit 20 generates a 4fsc signal phase-locked to the input video signal containing jitter components, and this signal is used as a write clock that is the timing for writing to the memory 12, as in FIG.

The process of improving the jitter Killen cell in the circuit of FIG. 1 will be explained with reference to FIGS. 2a-C.

2a to 2C show the frequency characteristics of gain and phase, FIG. 2a shows the transfer characteristic regarding the jitter component of the video signal delayed by the delay circuit 22, and FIG. , C shows the jitter improvement characteristics. Since the input video signal is delayed by the delay circuit 22 and input to the A/D converter 10, a phase lag as shown in FIG. 2a occurs.

The improved characteristics shown in FIG. 2C can be obtained by setting the delay amount of the delay circuit 22 to offset the phase delay in the tracking characteristics of the PLL circuit 20 shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

In this second embodiment, the input video signal is applied as an analog signal to the C0D24, and the output signal of the PLL20 is used as the C0D24.
The C0D 24 is used as a variable delay circuit, that is, as a time axis control means. Since the input video signal is applied to the C0D 24 via the delay circuit 22, the phase delay of the PLL 20 can be compensated for.

The other configurations are the same as in the first embodiment.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

This third embodiment uses automatic phase control (APC) of reproduced color signals.
This is a jitter cancellation circuit as a circuit. In Figure 4, 26 is an LPF, 28 is a delay circuit, and 30.38 is an AC
C circuit, 32, 40° 58 is a frequency converter, 34, 42
．． 60 is BPF, 36.44 is comb filter, 46 is A
CC detector, 48 APC phase comparator, 50 crystal oscillator, 52 filter, 54 VCo, 56 PS or P
This is an I-type phase switching section, of which circuits 40 to 44 including the VCO 54 and a loop of 48 to 60 constitute a PLL. In the figure, the parts other than circuits 28 to 36 are the same as the conventional ones, and a delay circuit 28 and subsequent circuits 30 to 36 are newly added in the present invention. BPF that is part of PLL
The output of BPF 60 is given to two frequency converters 32 and 34, and since the output of BPF 60 includes a jitter component, the jitter component is canceled out from the output of frequency converter 32 and 40. Here, the frequency converter 32 is the delay circuit 2
8 is responding to a signal delayed by a predetermined time, so the previous 2
As in the two embodiments, the phase delay in the tracking characteristics of the PLL circuit is compensated. In this embodiment, the frequency converter 32 serves as time axis control means.

(Effects of the Invention) As explained in detail above, in the present invention, in a jitter canceling circuit using a PLL circuit, the time is controlled by the output of the PLL circuit in order to compensate for the phase delay in the high tracking degree range of the PLL circuit. Since the delay means for delaying the video signal input to the axis control means by a predetermined amount is provided, it is possible to correct jitter up to high frequencies.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the jitter cancellation circuit of the present invention, and FIG. 2 is a graph explaining its operation.
3 and 4 are block diagrams showing the second and third embodiments of the jitter cancellation circuit of the present invention, respectively, and FIG.
The figure is a block diagram showing a conventional jitter cancellation circuit, and FIG. 6 is a graph explaining its operation. 10...A/D converter, 12...memory, 14...
・D/A converter, 16... memory control circuit,
18...Horizontal synchronization separation circuit, 20...PLL circuit,
22.28...Delay circuit, 24...CC0126・
...LPF, 30.38...ACC, 32,40,5
8...Frequency converter, 34,42.60...BPF
. 36.44... Comb filter, 46... ACC detector, 4B... Phase comparator, 50... Crystal oscillator, 5
2... Filter, 54... VCo, 56... Phase switching section. Figure 1 Inventor: Nobuyuki Mori Patent applicant: Victor Japan Co., Ltd.

Claims (1)

[Claims] A jitter canceller comprising: a PLL circuit that responds to a horizontal synchronization signal or a color burst signal in a reproduced video signal of a VTR; and a time axis control means that controls the time axis of the reproduced video signal or its components according to the output of the PLL circuit. A jitter canceling circuit comprising: a delay means for delaying the reproduced video signal or its components inputted to the time axis control means by a predetermined period of time.