JPH04114592A - Time base fluctuation correction circuit - Google Patents

Abstract

PURPOSE:To reduce a residual offset voltage by sampling a disk rotation speed error caused in a 1H just before a vertical blanking period, deciding its absolute value and polarity, integrating the signal for the vertical blanking period to obtain an equivalent voltage and adding the voltage as an error voltage of a PLL loop. CONSTITUTION:A result of integration of a bipolar integration circuit 22 based on the result of detection of a speed error detection circuit 21 is given to an input of a voltage controlled oscillator (VCO) 14 via a changeover circuit 24. The bipolar integration circuit 22 samples a speed error in disk rotation caused in 1H just before, e.g. a vertical blanking period to decide its absolute value and polarity. A voltage equivalent to an error voltage for the vertical blanking period is obtained by integrating a signal for the vertical blanking period based on them. The locking of the PLL is facilitated just after the vertical blanking period by adding the voltage to an error voltage input of the PLL loop. Thus, a residual offset voltage is reduced and jitter in a reproduced picture is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a time axis fluctuation correction circuit that corrects eccentric speed errors and the like during playback of a laser disk (LD), for example.

(Prior Art) For example, information on a laser disk is obtained as an electrical signal by photoelectrically converting a modulated laser beam that is diffracted by its bits and reflected back using an 0EIC (optoelectronic integrated circuit).

This electric signal includes an FM modulated video signal with a frequency deviation width of 1.7 MH2 and a center frequency of 2.3 MH2 and 2.8 MH2.
MH21 frequency deviation width ±100 KH2 (7) Contains two types of FM modulated audio signals. The reproduced video signal obtained from the laser disc is processed by an FM collector to correct variations in spatial frequency characteristics depending on the disc playback position, and after only the video FMIII transmission wave is separated by a bandpass filter with a band of 3.5M to 15M H2. , the video signal is modulated by 1JI by an FM demodulator.

By the way, correction of eccentric velocity errors and the like during reproduction of a laser disc is performed by, for example, a time axis fluctuation correction circuit shown in FIG.

That is, the reproduced video signal read from the laser disk is taken into the sample hold circuit 3 via the gate circuit 1 and the phase comparator 2. At this time, a color burst gate signal is extracted from the reproduced video signal by the synchronization separation circuit 4, and this is also taken into the summble hold circuit 3 as a control signal.

Then, the sample and hold circuit 3 holds the error voltage between the color burst output from the phase comparator 2 and the reference signal fsc. The signal passed through the sample hold circuit 3 is given to a VCO (voltage controlled oscillator) 6 via an equalizer 5. Thereby, the frequency at which the VCO 6 should oscillate itself is controlled.

When the output of vcoe is applied to the sync generator 7, the sync generator 7 outputs various drive signals for correcting time axis fluctuations and the like.

At this time, the signal rSC from the sync generator 7 is
Since it is fed back to the phase comparator 2 by the PLL loop, it is always synchronized with the phase of the input reproduced video signal. Here, the drive signal includes a horizontal synchronization signal and a vertical synchronization signal.

(Problem to be Solved by the Invention) For example, when a PLL loop is used to generate a clock synchronized with a color burst of a video signal including a speed error component, as shown in FIG. It is necessary to take into account that there is a blanking interval. For this reason, the error voltage immediately before the color burst blanking section is generally held, and in this case, due to the actual speed error component, the residual offset is 2.3 when the PLL is pulled in immediately after blanking. It happens over and over again.

As a result, excessive vibration occurs and the bowing time is delayed.

Furthermore, as shown in FIG. 10, for example, when PCM audio is superimposed as an external signal in the vertical blanking section, the color burst signal for the PLL disappears and a run-in signal for the PLL is added instead. Ru. Even in this case, since the residual offset voltage is large, the PLL linking may extend into the video section and may not be established as a clock. Furthermore, by adding a run-in signal for PLL, the utilization rate in the vertical blanking section decreases.

As a result, in both the former and the latter, the residual offset voltage becomes high when the PLL is pulled in.

If the residual offset voltage becomes uneven in this way, jitter will occur in the reproduced image.

The present invention was made in response to these circumstances, and
It is an object of the present invention to provide a time base fluctuation correction circuit that can reduce residual offset voltage when a PLL is pulled in.

(Means for Solving the Problems) In order to achieve the above object, the time axis fluctuation correction circuit of the present invention includes a synchronous clock generation means for generating a clock synchronized with the phase of a reproduced signal, and an error correction circuit immediately before vertical blanking. The apparatus is characterized by comprising an error signal integrating means for integrating a signal, and an integral result adding means for adding an integration result from the error signal integrating means during a vertical blanking period to the synchronous clock generating means.

(Function) In the time axis fluctuation correction circuit of the present invention, when the synchronization clock generation means generates a clock synchronized with the phase of the reproduced signal,
The error signal integrating means integrates the error signal immediately before vertical blanking, and the integration result adding means adds the integration result from the error signal integrating means during the vertical blanking period to the synchronous clock generating means.

That is, for example, a disk rotation speed error occurring within the IH immediately before the vertical blanking interval is sampled and its absolute value and polarity are determined.

Then, by integrating the vertical blanking section based on these, an equivalent voltage can be obtained. By adding this to the PLL loose error voltage (at this time, the vertical blanking is in the hold mode), the PLL can be easily pulled in immediately after vertical blanking.

Furthermore, when digital data such as audio is inserted into the vertical blanking, it is easier to pull in the PLL run-in signal, so a stable clock can be obtained from the beginning of the immediately following video section. Furthermore, since the period of the PLL run-in signal can be shortened, it is also possible to effectively use the vertical blanking section.

(Example) Hereinafter, details of an example of the present invention will be described based on the drawings.

FIG. 1 shows an embodiment of the time axis fluctuation correction circuit of the present invention.

As shown in the figure, the time axis fluctuation correction circuit includes a gate circuit 101, a phase comparator 11, a sample hold circuit 12,
An equalizer 13, a VCO (voltage controlled oscillator) 14, and a sync generator I5 are provided. In addition, the time axis fluctuation correction circuit includes a l/4 frequency divider 16.80 degree phase detection circuit 17, a lock detector 18, a synchronization separation circuit 19, an inhibitor 20, a speed error detection circuit 21, a bipolar integration circuit 22, A logic circuit 23 and a switching circuit 24 are provided.

The gate circuit IO extracts the color burst signal from the reproduced video signal.

The phase comparator ll compares the phase of the color burst signal extracted by the gate circuit 10 and the phase of the reference signal fed back from the sync generator 15 via the 1/4 frequency divider 16.

The sample and hold circuit 12 holds the error voltage from the phase comparator 11.

The equalizer 13 functions to smooth the error voltage.

The VCO 14 oscillates at a frequency controlled by the voltage smoothed by the equalizer 13.

The sync generator 15 is a commonly used TV synchronization signal generator. For example, when a 14.318MH2 clock is input, the sync generator 15 generates HS & nCN HD s VDl.
Outputs drive signals such as BL.

Note that in the external synchronization mode, 14.318 MHz locked to the reproduced color burst is output.

In addition, when an HD or VD signal synchronously separated from the playback video signal is input, the fsc locked to the playback video signal
A signal such as s Hsyncs V D is output.

The 1/4 frequency divider I6 divides the frequency of the reference clock signal from the sync generator I5 by 174.

The 90 degree phase detection circuit 17 detects a phase shift every 90 degrees.

The lock detector 18 operates as shown in FIG. 2, for example.

In other words, it is assumed that a sine wave comparison type is used for the phase comparator 11, and this phase comparator 11
When locked, the reproduced color burst and the fsc from the VCOI 4 are shifted by 90 degrees as shown in FIG. 2 (2).

Therefore, when the phase is locked at 90 degrees, the error voltage becomes zero.

In addition, since the phase of fBC delayed by 90 degrees is compared with the reproduced color burst in the lock detector I8, the phase comparator 1
The output from 1 is the maximum negative value (■ in Figure 2).

If we temper this negative voltage with an appropriate threshold value, we get
A lock/unlock signal is obtained.

The synchronization separation circuit 19 separates horizontal (H) and vertical (V) synchronization signals from the reproduced video signal.

The inhibitor 20 stops the operation of the speed error detection circuit 21 during the color burst blanking period.

The speed error detection circuit 21 holds the speed error voltage while its operation is stopped by the inhibitor 20.

The bipolar integration circuit 22 samples the rotational speed error of the disk that occurs in the IH immediately before the vertical blanking interval, determines its absolute value and polarity, and integrates the vertical blanking interval based on these. .

The logic circuit 23 generates a pulse pulse for switching the voltage obtained through the error voltage integration period from the beginning of the vertical synchronization signal of the reproduced color burst in the switching circuit 24 when the color burst is in the locked state.

When there is a normal color burst, the switching circuit 24
■It can be switched to the side.

FIG. 3(a) shows the details of the speed error detection circuit 21. For example, as shown in (■) in FIG. 4(a), 15.
75 KH2 frequency'! & When the quasi-oscillator 21a oscillates, the sawtooth wave generation circuit 21b generates a signal as shown in FIG.
) Outputs the sawtooth wave shown in ■. Next, the sample hold circuit 21c takes in the detection results from the sawtooth wave and edge detection circuit 21d, and then outputs a speed error signal.

Note that the configuration of the speed error detection circuit 21 may be as shown in FIG. 3(b), for example.

That is, when the rising edge detection circuit 21f outputs the sawtooth wave I noset pulse ■ based on PB and H■ in FIG. 4(b) that have been waveform-shaped by the waveform shaping circuit 21e,
The sawtooth wave generation circuit 21b outputs a sawtooth wave ■.

Also, when the falling detection circuit 21g outputs a sawtooth voltage sample pulse ■ based on PB and H■,
The sample and hold circuit 21c outputs a speed error signal based on the sawtooth wave (2) and the sawtooth voltage sample pulse (2).

FIG. 5 shows details of the sync generator 15. When 4fsc is input, the frequency divider 15a divides the frequency into 1/
The frequency is divided into 455 and further divided into 1152 by the frequency divider 15b.
After being divided by 5, the vertical synchronization signal is obtained. On the other hand, the horizontal synchronization signal is obtained after being frequency-divided into 1/2 by the frequency divider 15c.

Next, the operation of the time axis fluctuation correction circuit having the above-described configuration will be explained using FIG.

First, when a reproduced video signal read from, for example, a laser disk is taken into the gate circuit IO, the gate circuit I
A color burst signal is extracted by O. When the color burst signal from the gate circuit mto is input to the phase comparator 11, the phase comparator 11 calculates the phase of the color burst signal and the reference signal fed back from the sync generator 15 via the 1/4 frequency divider 16. Compare with.

When the error voltage from the phase comparator 11 is held by the sample and hold circuit 12, the equalizer 13 smoothes the error voltage. At this time, the equalizer 13 receives the detection result from the lock detector 18 .

Here, the lock detector 18 operates as shown in FIG. 2, for example.

In other words, it is assumed that a sine wave comparison type is used as the phase comparator 11, and this phase comparator II
The output from the sync generator 15 is the reproduced color burst and the fsc from the sync generator 15 as shown in Figure 2 (■) when locked.
and are shifted by 90 degrees.

Therefore, when the phase is locked at 90 degrees, the error voltage becomes zero.

In addition, since the lock detector 18 compares the phase of rSC delayed by 90 degrees with the reproduced color burst, the phase comparator 1
The output from 1 is the maximum negative value (■ in Figure 2).

By comparing this negative voltage with an appropriate threshold value, a lock/ascillator signal is obtained.

Here, the locked state is as follows.

■... fsc output from the sync generator 15
is phase-locked to the playback color burst.

■...Horizontal and vertical sync phases are locked.

2... From 2 and 3, the reproduced video signal can be A/D converted or used to create a timing signal.

Further, the state in which the lock is not locked is as follows.

If ■...■ and ■ hold true, the A/D clock will flow and the accurate timing of the reproduced video signal will become unusable in the system.

Here, the purpose of lock detection is to widen the pull-in range of the PLL, which shortens the settling time, but reduces the amount of time required to suppress jitter in the reproduced color burst. If the loop filter band of the PLL is made narrow and the gain is made high, the amount of fsc jitter will be considerably suppressed compared to the jitter of the reproduced color burst.

However, since it is contradictory to satisfy the former and the latter at the same time, the characteristics of the loop filter (equalizer 13) are switched to high gain in the high snoring range during pull-in and high gain in the narrow band after locking.

The error signal smoothed by the equalizer 13 is
Controls the oscillation frequency of O14. The controlled frequency is
It is given to the sync generator I5.

At this time, the integration result of the bipolar integration circuit 22 based on the detection result of the speed error detection circuit 21 is added to the input side of the VCO 14 via the switching circuit 24.

That is, the function of the bipolar integration circuit 22 is to sample the disk rotation speed error that occurs within the IH immediately before the vertical blanking interval, and determine its absolute value and polarity. Then, by integrating the vertical blanking interval characteristics based on these, a voltage equivalent to the error voltage within that interval is obtained.

By adding this to the error voltage of the PLL loop (at this time, the vertical blanking is in the hold mode), the PLL can be easily pulled in immediately after vertical blanking.

Furthermore, when digital data such as audio is inserted into the vertical blanking, it is easier to pull in the PLL run-in signal, so a stable clock can be obtained from the beginning of the immediately following video section. Furthermore, since the period of the PLL run-in signal can be shortened, it is also possible to effectively use the vertical blanking section.

As described above, in this embodiment, the speed error of the rotation of the disk occurring within the IH immediately before the vertical blanking section is sampled, and its absolute value and polarity are determined. Then, by integrating the vertical blanking interval characteristics based on these, an equivalent voltage is obtained, so add this to the error voltage of the PLL loop (at this time, the vertical blanking is in hold mode). did. As a result, the residual offset voltage can be reduced, which allows the playback 1i! 1i(l jitter can be prevented.

Furthermore, when digital data such as audio is inserted into the vertical blanking, it is easier to pull in the PLL run-in signal, so a stable clock can be obtained from the beginning of the immediately following video section. Furthermore, since the period of the PLL run-in signal can be shortened, it is also possible to effectively use the vertical blanking section.

Note that, for example, as shown in FIG. 7, it is also possible to use the average speed error or eccentric acceleration component of multiple lines immediately before vertical blanking instead of the IH speed error.
It is also possible to accurately correct even near the inflection point of the speed error curve.

(Effects of the Invention) As explained above, according to the time axis fluctuation correction circuit of the present invention, the absolute value and polarity of the rotational speed error of the disk that occurs within lH immediately before the vertical blanking interval is sampled. , integrate the vertical blanking interval based on them to obtain an equivalent voltage, and add this to the error voltage of the PLL loop (at this time, the vertical blanking is in hold mode). did.

As a result, the residual offset voltage when the PLL is pulled in can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the time axis fluctuation correction circuit of the present invention, FIG. 2 is a diagram showing an example of a linear waveform by the multiplier in FIG. 1, and FIG. A block diagram showing details of the speed error detection circuit in FIG. 1,
Fig. 4(a) is a diagram showing the output waveform of the speed error detection circuit of Fig. 3(a), and Fig. 3(b) is a diagram showing the output waveform of the speed error detection circuit of Fig. 3(a) when the configuration is changed. A block diagram showing another example, FIG. 4(b) is a diagram showing the output waveform in the speed error detection circuit of FIG. 3(b), FIG. 5 is a block diagram showing details of the sync generator of FIG. 1, FIG. 6 is a diagram for explaining the operation of the time axis variation correction circuit in FIG. 1, FIG. 7 is a diagram for explaining another application example of the present invention, and FIG. 8 is a diagram for explaining the conventional time axis variation correction circuit. A block diagram showing an example of the circuit, FIG. 9 and FIG. 1O are diagrams for explaining the operation of the time axis fluctuation correction circuit of FIG. 8. 10... Gate circuit, ll... Phase comparator, 12.
...Sample hold circuit, 13...Equalizer, 1
4...VCO C voltage controlled oscillator), 15...Sink generator, 16...1/4 frequency divider, 17...
90 degree phase detection circuit, 18...lock detector, 19.
...Synchronization separation circuit, 20...Inhibitor, 21...
・Speed error detection circuit, 22...Bipolar integration circuit, 2
3...Logic circuit, 24...Switching circuit.

Claims (1)

[Claims] (1) Synchronous clock generation means that generates a clock synchronized with the phase of the reproduced signal, error signal integration means that integrates the error signal immediately before vertical blanking, and integration from the error signal integration means during the vertical blanking period. A time axis fluctuation correction circuit comprising: integral result adding means for adding the result to the synchronous clock generating means.