JPH0530476A - Video signal time base correcting circuit - Google Patents

Abstract

PURPOSE:To improve the phase following-up characteristic of a write clock pulse by applying a signal including <=1H time base variance (velocity error) to a delay clock generating circuit of the FF (feed forward) system in a digital TBC (time base corrector). CONSTITUTION:The circuit which generates the sampling clock of an A/D converter and the write clock to a memory in the digital TBC circuit constitution is provided with a first 0th order hold circuit 24 which holds the time base variance of the reproduced video signal with respect to DC, a second Oth order hold circuit 25 which holds it after 1H delay 22, a 1st order hold circuit 26 which linearly holds signals of first and second 0th order hold circuits, a circuit 27 which adds the second 0th order hold signal and the 1st order hold signal, and a VCO 28 controlled by this addition signal, and the clock output signal of the VCO 28 passes an FF system clock signal generating means consisting of plural delay elements to obtain a prescribed write clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for correcting fluctuations of a reproduction signal in a time axis direction when reproducing a video signal in a magnetic recording / reproducing apparatus such as a video tape recorder (hereinafter referred to as VTR). is there.

[0002]

2. Description of the Related Art In a magnetic recording / reproducing apparatus such as a VTR, the reproduced video signal is subject to time-axis fluctuation due to factors such as uneven running of the tape running system and expansion / contraction of the tape, and the screen bends on the monitor screen. Appears as (jitter).
As a method of correcting the time base fluctuations, (hereinafter referred to as TBC) de _Lee digital time base collector circuit is employed.

FIG. 2A is a principle diagram of a time axis correction circuit, and FIG. 2B is a schematic diagram for explaining signal correction. In the figure, de the _y digital TBC, the ADC1 to convert the reproduced video signal to the de _Lee digital signal, a memory 2 for storing該De _Lee digital signal, a horizontal sync separator for separating a horizontal synchronizing signal of the reproduced video signal 3, a clock pulse creating circuit 4 for creating a sampling clock of the ADC 1 using the horizontal synchronizing signal, and a write pulse creating circuit 6 for creating a write pulse to a memory control circuit 5 for controlling writing to the memory 2. de _Lee digital signal stored in the memory 2 is converted into an analog signal, and DAC7 to be corrected output of the fluctuation, the memory control circuit 5 from the oscillation frequency of the fixed cycle of the local oscillator 8
And a read clock pulse creation circuit 9 for creating a read clock pulse for controlling the DAC 7. Incidentally, 10 and 11 are an input terminal and an output terminal of the reproduced video signal, respectively.

With the above circuit configuration, the reproduced video signal S ₀ having irregular H (horizontal synchronization period) as shown in FIG. 2B is the output signal S _{1 of the} TBC circuit having the standard 1H.
The time-axis corrected reproduction video signal is obtained at the output terminal 11. Therefore, the performance of the TBC circuit is
It is determined by how the clock written to the memory corresponds to the time base fluctuation of the reproduced video signal. Generally, a PLL (Phase Lo
The cked Loop) method and the FF (Feed Forward) method are used as prizes.

FIG. 3A is a block diagram of a PLL clock generation circuit, and FIG. 3B is an equivalent circuit diagram thereof. In the figure, the reproduced video signal input from the input terminal 10 is separated into a sync signal by the horizontal sync separation circuit 3, and is input to the phase comparison circuit 12 at the next stage. Then LPF (Low
After the high frequency components are removed by the Pass Filter) 13 and the waveform is shaped, the VCO (Voltage Controller Oscillator) 1
Modulates the oscillation frequency of 4. The output signal of the VCO 14 is frequency-divided by the frequency dividing circuit 15 and then fed back to the phase comparison circuit 12 for phase comparison with the horizontal synchronizing signal. Therefore, VCO14
A clock pulse containing a time-axis fluctuation component included in the original reproduced video signal is output from the output terminal 16.

The transfer function of the phase error showing the phase tracking characteristic of the above-mentioned PLL type clock pulse generation circuit is shown in FIG.
It becomes a first-order lag function as shown in (b) and depends on the transfer function F (s) of the LPF 13. In the figure, F (s) is LPF
13 is a transfer function, kd is a conversion gain coefficient (V / rad) of the phase comparison circuit 12, and ko is a conversion gain coefficient (rad / vs) of the VCO 14.
Is. Now, if the phase error is θ _e ; the phase of the reproduced video signal is θ _i , and the phase of the feedback signal is θ _o , then θ _e = θ _i −θ _o

[0007]

[Equation 1]

[0008]

[Equation 2]

In general, the LPF deteriorates in the high frequency region as compared with the low frequency transmission characteristic, and as a result, the phase tracking characteristic of the PLL circuit has a low frequency characteristic in the high frequency region as shown in FIG. 3C. Lost. Therefore, the phase when writing to the memory for the low frequency component in the PLL system corresponds to the time base fluctuation of the reproduced video signal, but the phase when writing for the high frequency component becomes unstable. Has a drawback. (Generally, the TBC cannot operate for frequency components of 1 _KHZ or higher.) Next, the FF type clock pulse generation circuit will be described with reference to FIG. The FF method is a method for compensating for deterioration of the phase tracking characteristic of the clock pulse with respect to the high frequency components in the PLL method. A basic clock pulse generated by the local oscillator 17 is passed through a delay tap circuit 18 composed of a plurality of delay elements to generate n delay clocks, which are input to a latch circuit 19. The latch circuit 19 latches n delayed clock pulses with the horizontal synchronizing signal separated from the reproduced video signal. The latched clock pulse detects a change (High or Low) of the clock pulse latched by the selection signal generation circuit 20, and generates a control signal. The n delayed clock pulses are also input to the clock selection switch circuit 21, and the control signal from the selection signal generation circuit 20 causes the clock selection switch circuit 21 to output the first horizontal synchronization signal among the n delayed clock pulses. One delayed clock pulse in the vicinity is selectively output. Figure 4
(B) shows a time chart of signals of each part.

Since this FF system can be constructed by a logic circuit, a write clock pulse corresponding to the time base fluctuation of the reproduced video signal can be obtained, but with respect to the time base fluctuation within 1H (H; horizontal synchronization period). correction (Beroshite _Lee Era correction) can not.

[0011]

The TBC circuit has a problem in that the frequency response characteristic in the high frequency range is deteriorated in the PLL system adopted in the write clock generation circuit described above, and the time axis fluctuation within 1H in the FF system cannot be coped with. Of performance deterioration of
There are two factors. The present invention provides a circuit for solving the above problems.

[0012]

A time axis correction circuit for controlling a sampling clock of an A / D converter and a writing clock to a memory by using a horizontal synchronizing signal of a reproduced video signal, which is a reproduced video signal. First 0th-order holding means for holding time-axis fluctuations during the horizontal synchronization period of
The second 0th-order holding means for holding the time axis fluctuation of the horizontal synchronization period after delaying the reproduction video signal by 1H (H; horizontal synchronization period) and the hold signals of the first and second 0th-order holding means are linear. Primary hold means for holding the first zero hold signal, an adder means for adding and calculating the second zero order hold signal and the primary hold signal, and a VCO (voltage controlled oscillator) for creating a first clock signal using the added signal as a control voltage. ), And a predetermined write clock signal is obtained from the first clock signal through an FF (feed forward) clock signal generating means composed of a plurality of delay elements.

[0013]

[Action] the construction described above, the time axis variation amount contained in the horizontal synchronizing signal of the reproduced video signal, i.e. to obtain a control voltage having a Beroshite _Lee Era, responsive to the voltage controlled time base variation of the VCO in the control voltage Get the clock pulse. The clock pulses by passing the clock pulse generating circuit of the FF scheme, a write clock pulse including a time base fluctuation in 1H is created, a time axis correction by de _Lee digital TBC is performed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction of the present invention will be described below with reference to the drawings.
FIG. 1 is a circuit block diagram of the present invention. In the figure, the same parts as those in the conventional example are designated by the same reference numerals, and the description thereof is omitted. In the figure, 22 is a 1H delay circuit, 23 is a horizontal sync separation circuit, 24 and 25 are first and second zero-order hold circuits, 26 is a first-order hold circuit, 27 is an adder circuit, and 28 is VC.
An O circuit, 29 is a trapezoidal wave forming circuit, and 30 is a servo phase circuit.

The reproduced video signal inputted from the input terminal 10 is made into a horizontal synchronizing signal by the horizontal synchronizing separation circuit 3 and inputted to the first 0th order hold circuit 24. The reproduced video signal is delayed by the 1H delay circuit 22, and then the horizontal sync signal is separated by the horizontal sync separation circuit 23 and input to the second zero-order hold circuit 25. These two horizontal synchronizing signals are used as sample signals, and the first and second zero-order hold circuits 2 are respectively provided.
At 4 and 25, the time-axis fluctuation amount is held as a direct current. The 0
The reference signal applied to the next hold circuits 24 and 25 is a trapezoidal wave signal created by the trapezoidal wave creating circuit 29 based on the basic clock signal generated by the local oscillator 17.

The basic clock signal of the local oscillator 17 is also the basis of the read clock signal and the synchronizing signal of the read clock signal, and defines the phase relationship of the 0th-order hold circuits 24 and 25. The hold signals of the 0th-order hold circuits 24 and 25 are input to the 1st-order hold circuit 26, respectively, for 1H.
The change in the variation amount during the period is approximated to a linear line and held (primary hold). That is, this primary hold signal corresponds to the AC component of the time axis fluctuation for each 1H.

Zero-order hold signal (output signal of the second zero-order hold circuit 25), which is a DC component of time-axis fluctuation for each 1H.
When By Type addition and calculating an output signal of the first-order hold circuit 26 to the adding circuit 27, the time base variation signal including time base fluctuations in 1H (Beroshite _b Era) is obtained.
This time axis fluctuation signal is used as a control signal for the VC of the next stage.
By controlling the oscillation frequency of the O circuit 28, the oscillation frequency is converted into an FM signal.

By using the clock pulse which is the output of the VCO circuit 28 as the input clock pulse of the above-mentioned FF system clock pulse generation circuit, the VCO clock delay pulse which is closest in time to the horizontal synchronizing signal can be obtained. The clock delay pulse can be used as a write clock pulse for the memory control circuit 5. Although the FF system clock pulse generation circuit is as described above, the delay tap circuit 18 and the latch circuit 1 are described again.
9. A selection signal generation circuit 20 and a clock pulse selection switch circuit 21 are provided. The latch timing of the latch circuit 19 is performed in the cycle of the horizontal synchronizing signal after 1H delay.

[0019] de _Lee digital TBC circuit of the present invention, the reproduced video signal after delayed by 1H, and enter into the ADC circuit 1,
Converts an analog signal to the de _Lee digital signal,
A conventional example is that a 1H delayed playback video signal is used (see FIG. 2).
See)).

[0020]

By adopting the write clock pulse generation circuit of the present invention, the phase tracking characteristic with respect to the frequency fluctuation in the high frequency band can be improved, and the fluctuation of the time axis within 1H can be corrected. A high-performance time base correction circuit can be provided.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of the present invention.

FIG. 2 is a circuit block diagram of a conventional example and a diagram for explaining time axis correction.

FIG. 3 is a circuit block diagram and an equivalent circuit diagram of a conventional example and a frequency versus phase error characteristic diagram thereof.

FIG. 4 is a circuit block diagram of another conventional example and a time chart diagram of waveforms of respective parts thereof.

[Explanation of symbols]

1 ADC (Analog Devices _y digital converter) 2 memory circuit 3 horizontal sync separator 5 the memory control circuit 7 DAC (digital-to-analog converter) 18 delay tap circuit 19 latch circuits 20 select signal generating circuit 21 a clock selection switch circuit 22 1H delay element 23 Horizontal sync separation circuit 24 First zero-order hold circuit 25 Second zero-order hold circuit 26 Primary hold circuit 27 Adder circuit 28 VCO (voltage controlled oscillator)

Claims (2)

[Claims] 1. A time axis correction circuit for controlling a sampling clock of an A / D converter and a writing clock to a memory by using a horizontal synchronization signal of a reproduced video signal, wherein the horizontal synchronization of the reproduced video signal is performed. First 0th order holding means for holding the time axis fluctuation of the period, and second 0th order holding means for holding the time axis fluctuation of the horizontal synchronizing period after 1H (H; horizontal synchronizing period) delay of the reproduced video signal. A primary hold means that linearly holds the hold signals of the first and second zero-order hold means; and an adder means that performs an addition operation on the second zero-order hold signal and the primary hold signal. A VCO (voltage controlled oscillator) that creates a first clock signal using the added signal as a control voltage, and the first clock signal is an FF including a plurality of delay elements.
A video signal time axis correction circuit, characterized in that a predetermined write clock signal is obtained through a (feed forward) system clock signal generating means. 2. The FF system clock signal generating means,
A delay tap circuit including a plurality of delay elements, a clock selection switch circuit for selecting a delay signal of the delay tap circuit, a latch circuit for latching the delay signal, and an output signal of the latch circuit for the clock selection switch circuit. 2. The video signal time base correction circuit according to claim 1, wherein the latch circuit is latched at a leading edge or a trailing edge of the horizontal synchronizing signal after the 1H delay.