JPH0258774A - System for controlling re-reading - Google Patents

Abstract

PURPOSE:To modify the followup ability of a clock so as to improve the recording information reading performance by switching the offset voltage value for deciding the conversion characteristics of a voltage-current conversion circuit to the voltage value corresponding to a control voltage. CONSTITUTION:Four-bit data from a register 13 and a Retry signal which becomes active at the time of re-reading are inputted to a multiplexer 8 in addition to 4-bit data from a fixed switch 7. When the Retry signal becomes active, the 4-bit data to be outputted to a D/A converter 9 are switched to the data from the register 13 at the multiplexer 8. Four-bit data which are produced by converting a control voltage passed through a buffer amplifier 10 and low-pass filter 11 into digital data by means of an A/D converter 12 are inputted to and held by the register 13. At the time of re-reading, the data from the register 13 are converted into the voltage value by means of the D/A converter 9 and inputted to a voltage-current conversion circuit 4. Therefore, the followup ability of a clock can be modified and the reading performane can be improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a reread control method in a phase-locked loop circuit of a magnetic tape device that synchronizes a read data pulse with a clock for determining recorded information. With the aim of improving tracking performance and increasing the reading performance of recorded information, we have developed a phase comparator, a current drive circuit that outputs a control voltage, a voltage-current conversion circuit, and a current-controlled oscillator that outputs a clock. The phase-locked loop circuit is configured to switch an offset voltage value that determines conversion characteristics of the voltage-current conversion circuit to a voltage value corresponding to the control voltage when a reading error occurs and re-reading is performed. do.

[Industrial application field]

The present invention relates to a reread control method in a magnetic tape device that stores digital information, and in particular to a phase-locked loop (hereinafter abbreviated as PLL) that synchronizes read data pulses and a clock for determining recorded information. ) Concerning a reread control method in a circuit.

FIGS. 2 and 3 are block diagrams and signals of a general data reading system of a magnetic tape device that stores digital information. Signals read out by the magnetic head (Fig. 3(a)
)) is converted into a read data pulse corresponding to the peak of the waveform as shown in FIG. 3(b) by a pulsing circuit including a differentiator, a zero-volt comparator, a Hals shaper, etc. In the PLL circuit, a clock with a duty ratio of 50% (Figure 3 (C
)) is generated, and in the recording data discrimination circuit, recording information of "0 pass" or "'1 pass" is discriminated based on the clock and the read data pulse. The condition for discrimination of recorded data in this recorded data discrimination circuit is that the clock is synchronized with the input read data pulse, and if there is a phase shift, correct data discrimination will not be performed.

In magnetic tape devices, data recording conditions on the tape often differ due to variations in tape running speed from device to device, differences in environment such as temperature, and the like.

Therefore, the cycle of the read data pulse varies, and in order to obtain information with a low data read error rate in the read system, it is important to have followability to synchronize the clock with the read data pulse in the PLL circuit. It has become.

[Conventional technology]

FIG. 4 shows a conventional PLL circuit. In the figure, 1 is a phase comparator that compares the phase of a read data pulse obtained by pulsing a read signal from a magnetic head with a clock described later and outputs a signal according to the phase difference, and 2 is a phase comparator for the phase comparison. 3 is a low-pass filter, 4 is a voltage-current conversion circuit that converts the control voltage output from current drive circuit 2 into a current value, and 5 is the voltage. This is a current controlled oscillator that outputs a clock with a frequency corresponding to the current value output from the current conversion circuit 4. The clock output from this current controlled oscillator is input to the recording data discrimination circuit described above, and is also fed back to the phase comparator 1.

The phase comparator 1 outputs an Up times signal when the clock is delayed with respect to the read data pulse, and the current drive circuit 2 increases the control voltage based on this Up times signal. As a result, the output current value of the voltage-current conversion circuit 4 increases, and the frequency of the clock output from the current control oscillator 5 increases.
IB is controlled to match the phase. Also, if the clock is ahead of the successive data pulses,
A Down signal is output from the phase comparator I, and this Do
In response to the wn signal, the current drive circuit 2 lowers the control voltage.

As a result, the output current value of the voltage-current conversion circuit 4 decreases, and the frequency of the clock output from the current control oscillator 5 decreases, and control is also performed to match the phases.

In this way, the PLL circuit detects the instantaneous phase difference between the fluctuating read data pulse and the clock, and outputs a clock synchronized with the read data pulse.

In the PLL circuit with the above configuration, the frequency of the clock output from the current controlled oscillator 5 is adjusted so that it can follow the frequency within the permissible fluctuation range of the read data pulse. At times, the offset voltage value, which determines the conversion characteristics between the control voltage input to the voltage-current conversion circuit 4 and the output current value, is adjusted by adjusting the range of variation using a variable resistor 6 or a tap, etc., as shown in FIG. The value was fixed.

[Problem to be solved by the invention]

However, in the above-mentioned conventional P L, L circuit, the conversion characteristics from the control voltage to the output current value deteriorate due to fluctuations in the offset voltage due to changes in the variable resistor over time, and deterioration of the 1-transistor etc. that constitute the voltage-current conversion circuit. changes, and the frequency of the clock output from the current controlled oscillator cannot follow the fluctuation in the period of the read data pulse.
The disadvantage is that the error rate in data reading is high.

The present invention was created in view of these problems, and
It is an object of the present invention to provide a reread control method that can improve the followability of a clock to read data pulses and improve the read performance of recorded information.

[Failure to solve the problem]

” - Means in the present invention for solving the problem is to compare the phases of a read data pulse obtained by pulsing a read signal of a magnetic head and an output clock of a current controlled oscillator described later, and generate a signal according to the phase difference. a current drive circuit that outputs a control voltage in response to the signal from the phase comparator; a voltage-current conversion circuit that converts the control voltage into a current value; In the PLL circuit of a magnetic tape device equipped with a current-controlled oscillator that outputs a frequency clock, when a read error occurs and re-reading is performed, the offset voltage value that determines the conversion characteristics of the voltage-current converter is This is based on a PLL circuit rereading control method that switches to a voltage value corresponding to the control voltage.

[Effect]

The present invention utilizes the fact that in a PLL circuit, a control voltage, which is the output of a current driver, changes in proportion to the recording density of data on a magnetic tape to be read. In other words, when the recording density is high, the clock phase lags behind the read redata pulse, and the control voltage increases.
In addition, if the recording density is low, the clock phase advances with respect to the read data pulse, and the control voltage decreases, so this control voltage is used to respond to the fluctuation and input it to the voltage-current conversion circuit. This changes the offset voltage value.

In other words, the off-cell voltage input to the voltage-current conversion circuit is initially set to a fixed value during normal reading, but due to deterioration due to aging etc., for example, when the clock is delayed with respect to the read data pulse. , If the output frequency of the current controlled oscillator cannot follow up and a reading error occurs, the offset voltage value is changed to a fixed value at the time of re-reading, and the offset voltage value is changed to a fixed value to correspond to the increased control voltage value.
Input a voltage value that is larger than the fixed value. Thereby, the output current value in the voltage-current conversion circuit can be made larger, and the clock output from the current-controlled oscillator can be made to follow up to a higher frequency. Also,
With the clock ahead of the read data pulse,
If the output frequency of the current controlled oscillator cannot follow up and a reading error occurs, the offset voltage value is changed to a fixed value at the time of re-reading, and a voltage smaller than the fixed value corresponding to the decreased control voltage value is set. Humanize the value.

As a result, the output current value in the voltage-current conversion circuit can be made smaller, and the clock output from the current-controlled oscillator can be made to follow up to a lower frequency.

Therefore, even if reading becomes unable to follow data recorded on another device under different conditions such as tape running speed, the follow-up performance when re-reading is improved, so data can be read reliably. be able to.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a PLL circuit according to an embodiment of the present invention. In the figure, the same components as those of the conventional device explained in FIG. 4 are denoted by the same reference numerals, and the explanation thereof will be omitted. As shown in FIG. 1, the voltage-current conversion circuit 4 includes a transistor 4a, which converts the control voltage into a current value. The offset voltage value input to the base of the transistor 4a, which determines the conversion characteristics, is a fixed value as in the conventional case.
D/A) is set by the converter 9. The fixed value of the voltage to this off-celler 1 is set by each switch (SW) of the fixed switch 7 during the unit test of the printer 1 to the board.
Settings are made and fixed by creating 4-bit data. This 4-bit data is input to the D/A converter 9 via the multiplexer 8, and the output voltage corresponding to the 4-bit data is input to the base of the transistor 4a as an offset voltage value.

In this embodiment, the offset voltage value input to the voltage-current conversion circuit 4 described above is switched to a voltage value corresponding to the control voltage output from the current drive circuit 2 by the multiplexer 8 during re-reading.

That is, in addition to the 4-bit data from the fixed switch 7, the multiplexer 8 receives 4-bit data from the register 13 and the Retry signal that becomes active when rereading.
A signal is being input. When this Retry signal becomes active, the multiplexer 8 switches the 4-bit data output to the D/A converter 9 to the data from the register 13. This register 13 always receives and holds 4-bit data obtained by converting a control voltage that has passed through a buffer amplifier 10 and a low-pass filter 11 by an analog-to-digital (A/D) converter 12. When rereading, the data from the register 13 is converted into a voltage value by the D/A converter 9 and input to the base of the transistor 4a of the voltage-current conversion circuit 4.

To explain in detail the operation during rereading in the PLL circuit with the above configuration, in the rereading state, there is a difference in phase between the read data pulse input to the phase comparator 1 and the clock output from the current controlled oscillator 5. Therefore, the control voltage output from the current drive circuit 2 has a voltage value that is higher or lower than the output voltage when there is no phase difference.

That is, if the clock is delayed with respect to the read data pulse, the control voltage is increased. This control voltage value is converted into a current value in the voltage-current conversion circuit 4, but at the same time, the buffer amplifier 10. Low pass filter 11. After passing through the A/D converter 12 and the D/A converter 9, it becomes a voltage value larger than the offset voltage value set by the fixed switch 7, and is inputted to the base of the transistor 4a as an offset voltage value of the voltage-current conversion circuit 4. Ru.

As a result, the output current value of the voltage-current conversion circuit 4 increases more than when using the off-cerat voltage of the initially set fixed value. Therefore, the frequency of the clock output from the current controlled oscillator 5 becomes high and can be synchronized with the read data pulse, thereby avoiding read errors.

In addition, if the clock is ahead of the read data pulse, the control voltage is lowered and the offset voltage value to the voltage-current conversion circuit 4 becomes a smaller value than the initially set fixed value. . As a result, the voltage-current conversion circuit 4
The output current value of is reduced compared to when the offset voltage is a fixed value. Therefore, the frequency of the clock can be lowered and synchronized to the read data pulse, thus avoiding read errors.

In this way, in this embodiment, the offset voltage value is fixed according to the control voltage by once digitizing the control voltage with the A/D converter and converting it into a voltage value again with the D/A converter to make the offset voltage. It can be made larger or smaller than the value, and the clock can be made to track the read data pulse.

〔Effect of the invention〕

As explained above, according to the present invention, when reading a magnetic tape or the like on which data has been recorded under extremely different write conditions, the output clock of the PLL circuit cannot follow the read data pulse. Even if an error occurs, the conversion characteristics of the voltage-current conversion circuit can be changed using the offset voltage value based on the data recording state when rereading, making it possible to follow the clock and improve reading performance. Can be done.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention; Fig. 2 is a block diagram of a reading system of a general magnetic tape device; Fig. 3 is a reading system signal; Fig. 4 is a configuration of a conventional PLL circuit. It is a diagram. 1; Phase comparator; ; Current drive circuit; 11; Low-pass filter; ; Voltage-current conversion circuit; ; Current-controlled oscillator; ; Variable resistor; ; Fixed switch; ; Multiplexer; ; Digital-to-analog (D/A) converter , 0; buffer amplifier, 2; analog-to-digital (A/D) converter, 3; register.

Claims (1)

[Claims] A phase comparator that compares the phase of a read data pulse obtained by pulsing a read signal of a magnetic head with an output clock of a current control oscillator (5) described later, and outputs a signal according to the phase difference. (1), a current drive circuit (2) that outputs a control voltage in response to a signal from the phase comparator (1), and a voltage-current conversion circuit (4) that converts the control voltage into a current value; In a phase-locked loop circuit of a magnetic tape device equipped with a current controlled oscillator (5) that outputs a clock with a frequency corresponding to the current value, when a read error occurs and re-reading is performed, the voltage-current conversion A rereading control method for a phase-locked loop circuit, characterized in that an offset voltage value that determines the conversion characteristics of the circuit (4) is switched to a voltage value corresponding to the control voltage.