JPH06309810A - Clock reproduction circuit - Google Patents

Abstract

PURPOSE:To obtain a stable reproduction clock even in a variable-speed reproducing operation. CONSTITUTION:A reproduction signal is supplied to an HPF 5, and only a high-frequency component is output. A level discrimination circuit 6 outputs a discriminated output at HIGH when the output of the HPF 5 is at a prescribed level or higher, i.e., during a perid in which a reproduction head is scanning a track in the same azimuth, and an ordinary PLL operation is realized when a switch 7 is closed. When the output of the HPF 5 is at the prescribed level or lower, i.e., in a period in which the reproduction head is scanning a track in a reverse azimuth, the level discrimination circuit outputs a discriminated output at LOW, the output of an integrator 3 is held in a previous state when the switch 7 is opened, and the output of a VCO 1 is fixed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock reproduction circuit suitable for a digital VTR capable of variable speed reproduction.

[0002]

2. Description of the Related Art Conventionally, a digital VTR capable of variable speed reproduction
The PLL circuit for reproducing the clock in, for example, the Television Society Technical Report v, issued in June 1989.
ol. 13, No. 31, PP1-6. This configuration is shown in FIG. That is, since the center frequency of the reproduction data with respect to the tape running speed is known in advance, the oscillation frequency of the voltage controlled oscillator (hereinafter referred to as VCO) 1 is determined by the tape running speed information (DC voltage) obtained from the capstan servo system. Controlled. Furthermore,
A phase error between the output of the VCO 1 and the reproduction data pulse obtained from the reproduction signal is detected by the phase comparator 2 and converted into a DC control voltage by the integrator 3. The adder 4 adds the tape traveling speed information and feeds it back to the VCO 1 to obtain a clock synchronized with the reproduction signal, and data is detected from the reproduction signal based on this clock.

[0003]

By the way, in the helical scan type VTR, when variable speed reproduction is performed at a tape speed different from that at the time of recording, the envelope of the reproduced signal becomes as shown in FIG. Here, high-level periods A and C
Is a reproducing level when the reproducing head crosses a track recorded by the reproducing head of the same azimuth and is a valid signal. On the other hand, a period B where the level is low is a reproduction level when a track of reverse azimuth is crossed and is a low frequency ineffective signal.

As shown in FIG. 3B, the reproduction data pulse obtained from the reproduction signal has a frequency and a phase which are significantly different from those of the reproduction data pulse obtained from the period A. Therefore, when the PLL circuit synchronizes with the incorrect reproduction data pulse in the period B, it takes time until the correct reproduction data pulse is synchronized with the period C next.

Therefore, there is a drawback that the reproduction clock and the reproduction signal are out of phase with each other at the beginning of the period C and normal data cannot be detected.

The present invention solves the above-mentioned drawbacks.
(EN) A clock recovery circuit capable of performing normal data detection even during variable speed reproduction.

[0007]

According to the present invention, there is provided a phase comparing means for phase comparing a reproduced data pulse obtained from a reproduced signal with an output of a voltage controlled oscillator, an integrating means for integrating the output of the phase comparing means, and this integrating means. Means for outputting a signal proportional to the tape running speed, and a clock reproducing circuit for obtaining a reproduction clock by controlling the voltage-controlled oscillator with the output of the adding means. Is a clock reproducing circuit provided with means for holding the output of the integrating means when scanning a track of azimuth different from that during recording.

[0008]

According to the present invention, during variable speed reproduction, when the reproducing head scans the same azimuth track as during recording,
The PLL loop operates and the clock synchronized with the reproduction signal is reproduced.

Further, when the reproducing head is scanning a track of azimuth different from that at the time of recording, the output of the integrating means is maintained in the previous state until the next time the reproducing head scans a track of the same azimuth as at the time of recording. It

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the circuit of this embodiment, and the same parts as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, part of the reproduced signal is H
It is supplied to PF5. The HPF 5 allows the reproduction signal to pass in the periods A and C when the reproduction head scans the track of the same azimuth because it is a high frequency signal. The component cannot be obtained and the output level decreases. And
The level discrimination circuit 6 outputs a high discrimination output when the HPF output is above a predetermined level, and outputs a low discrimination output when the HPF output is below a predetermined level. This discrimination output controls the switch 7 arranged between the phase comparator 2 and the integrator 3.

Next, the operation of the circuit of this embodiment will be described. First, while the reproducing head is scanning a track of the same azimuth (period A), the HPF5 output level is large and the discrimination output of the level discriminating circuit 6 is high. The switch 7 is closed by this high output, and the phase comparison output is supplied to the integrator 3, so that a clock synchronized with the reproduction signal is obtained from the VCO 1.

On the other hand, while the reproducing head is scanning the reverse azimuth track (period B), the HPF5 output is small and the discrimination output is low. This low output opens the switch 7, and the phase comparison output is not supplied to the integrator 3. At this time, since the input impedance of the integrator 3 becomes high, the output of the integrator 3 is held at the output in the period A. Therefore, in the period B, the VCO1 output is fixed to the oscillation frequency and phase in the period A.

When the reproducing head again scans the track of the same azimuth (period C), the switch 7 is closed and the phase comparison output is supplied to the integrator 3, so that the VCO1 output is synchronized with the reproduction signal. Controlled to do so. Here, the reproduction data pulse in the period A and the period C
At this time, the frequency of the reproduced data pulse is the same and the phases are not significantly different, so that the PLL circuit immediately locks and outputs a normal clock. Therefore, if this reproduced clock is used, the data can be normally detected from the beginning of the period C.

[0015]

As described above, according to the present invention, since a proper reproduction clock can be obtained even during variable speed reproduction and normal data detection can be performed, a good special reproduction image can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a clock recovery circuit in a conventional example.

FIG. 3 is a waveform diagram of a main part during variable speed reproduction.

[Explanation of symbols]

 1 VCO 2 Phase Comparison Circuit 3 Integrator 4 Adder 5 HPF 6 Level Discrimination Circuit 7 Switch

Claims (1)

[Claims] 1. A phase comparison means for comparing the phase of a reproduction data pulse obtained from a reproduction signal with the output of a voltage controlled oscillator,
An integrating means for integrating the output of the phase comparing means, an output of the integrating means, and an adding means for adding a signal proportional to the tape running speed are provided, and the output of the adding means controls the voltage controlled oscillator to generate a reproduction clock. In the clock reproducing circuit to be obtained, the clock reproducing circuit is provided with a means for making the output of the integrating means constant during variable speed reproduction when the reproducing head is scanning a track of azimuth different from that during recording.