JP2591881B2 - Sampled video signal recording disk playing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a MUSE (Multiple Sub-Nygui
The present invention relates to a recording disk playing device for playing a recording disk such as an optical disk on which a sampled video signal such as st Sampling Encoding is recorded.

[0002]

2. Description of the Related Art Such a recording disk playing device is disclosed, for example, in Japanese Patent Application Laid-Open No. 3-44868. This recording disk playing device has a time axis control based on a frame pulse signal and a control code signal extracted from a read MUSE signal, in addition to a first servo loop which performs time axis control based on a horizontal synchronization signal extracted from a read MUSE signal. And a time axis control is performed by the second servo loop while the first servo loop is in the unlocked state. In any case, such a time axis control device performs time axis control based on a synchronization signal obtained from the read MUSE signal. Accordingly, when the read MUSE signal is A / D converted, resampling is performed at the transmission sampling frequency. Therefore, it is preferable to manage the reproduction timing of the MUSE signal in the player.

[0003]

However, scanning,
In a so-called special reproduction operation involving a jump operation of a reading point such as still or frame feed, the reading MUSE signal becomes discontinuous, and during that time, the time axis servo by the reading synchronization signal becomes impossible. As a result, the screen reproduced through the MUSE decoder is greatly disturbed, which is not preferable.

[0004]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a sampled video signal recording disk playing apparatus capable of avoiding a disorder of a playback screen when performing a special playback operation.

[0005]

A recording disk playing apparatus according to the present invention has a first synchronization signal having a predetermined level point as a phase reference point of a sampling timing signal, and N times (N is a natural number) times the first synchronization signal. A recording disk playing device for playing a recording disk carrying a sampled video signal in which a control code is inserted at the same period as the second synchronization signal in addition to the second synchronization signal generated at a period, the device comprising: A first spindle servo loop for controlling the rotation speed of the recording disk based on a first synchronizing signal in a read signal obtained from a reading point on the recording disk; Each time a control code in the read signal is detected, a detection signal is generated, and the recording data is generated based on a time interval between the detection signal and a second synchronization signal in the read signal. A second spindle servo loop for controlling the time axis by controlling the rotation speed of the disc, a tracking servo means for performing a jump operation for the read point in response to a jump command, and a sampled video signal in the read signal for a unit section thereof. A memory means for sequentially taking in each time in synchronization with a write clock and sequentially reading in accordance with a read clock, and a write clock generating means for generating the write clock based on one of the timing of a reference clock and the first synchronization signal Means for issuing the second command in place of the first command during the trick play mode, and issuing the jump command during the lock period of the second spindle servo. Control means for causing a write clock generation means to generate a write clock based on the first synchronization signal. It is a recording disk playing apparatus according to claim.

[0006]

According to the recording disk playing apparatus of the present invention having such a configuration, during the special reproduction mode, the spindle servo is executed according to the second synchronizing signal, that is, the frame pulse and the control code, that is, the so-called disk code, and at the same time, to the memory. Is the first synchronization signal, that is, H
It is generated at a timing based on the D signal.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. In FIG.
Is rotationally driven by a spindle motor 2. On the disk 1, a MUSE signal in which a disk code as shown in FIG. 2 is inserted in a portion from the sample number 19 to 474 of the 564th line is recorded.

The disc code is modulated by a bi-phase modulation method, and includes an 8-bit synchronization pattern code, a 4-bit area identification code, an 8-bit chapter number code, a 24-bit frame number code, and a 20-bit disc status code. It consists of a code and a 12-bit user code. Each of these codes is composed of a BCD code, and the area identification code is a code for identifying any one of a lead-in, a program, and a lead-out. The chapter number code and the frame number code are codes representing a chapter number and a frame number, respectively. The disk status code is a code indicating a recording mode (CLV, CAV), a disk size, and the like.

The transmission rate of this disk code is 6 clocks / bit (= 2.7 Mbps). The value of the transmission rate is determined in consideration of the disk code read allowance at the time of startup or scanning and the amount of recorded information. That is, although it is possible to lower the transmission rate by taking only the read margin into account, the amount of information decreases. Further, the value of the transmission rate is different from the control code (2 clocks / baud) and the FP pulse of the MUSE signal, so that the detection accuracy during normal reproduction can be improved.

The spindle motor 2 has a built-in frequency generator 3 for generating an FG signal having a frequency corresponding to the rotation speed of the spindle motor 2. The FG signal output from the frequency generator 3 is supplied to an F / V conversion circuit 4 including a differentiating circuit and the like, and is converted into a signal having a level corresponding to the frequency of the FG signal. The output of the F / V conversion circuit 4 is supplied to an addition / subtraction circuit 5. The addition / subtraction circuit 5
The output of the reference voltage generation circuit 6 is supplied. A potentiometer connected to the reference voltage generating circuit 6 to generate a voltage corresponding to, for example, a relative position (hereinafter, referred to as a radial position) of a slider (not shown) carrying the pickup 7 with respect to the disk 1 in the radial direction. (Not shown)
Output voltage vP is supplied. Reference voltage generation circuit 6
Is configured to generate a reference voltage corresponding to the radial position of the pickup 7 by the output voltage vP of the potentiometer.

In the addition / subtraction circuit 5, the output of the F / V conversion circuit 4 is subtracted from the output of the reference voltage generation circuit 6, and an error signal is generated. The output of the addition / subtraction circuit 5 is input to a switch 9 via a control signal generation circuit 8 including a loop filter, a loop gain adjustment amplifier, and the like. The changeover switch 9 is connected to the system controller 10
In this configuration, one of the outputs of the control signal generation circuit 8, the changeover switch 11, and the acceleration signal generation circuit 12 is selectively output in accordance with the control signal S _A output from the control signal generator _A. Further, the acceleration signal generation circuit 12 includes the system controller 1
In response to an ON command signal i supplied from 0, a drive signal of a predetermined level for accelerating the spindle motor 2 is generated. The output of the changeover switch 9 is supplied as a drive signal to the spindle motor 2 via the drive amplifier 13, and the rotation speed of the disk 1 is controlled.
When the output of the control signal generation circuit 8 is selectively output from the changeover switch 9 at the time of starting or the like, the frequency generator 3
When the servo loop (hereinafter referred to as FG servo loop) formed by the F / V conversion circuit 4, the addition / subtraction circuit 5, the control signal generation circuit 8, the changeover switch 9, the drive amplifier 13, and the spindle motor 2 is turned on, the disk 1 The drive control of the spindle motor 2 is performed so that the rotation speed of the spindle motor 2 converges to the specified speed at the radial position of the pickup 7. A tracking servo circuit 7b for performing tracking servo of an information reading point 7a on the disk 1 of the pickup 7
Is provided. And the tracking servo circuit 7
The servo loop b is turned on / off by a command from the control circuit 10.

On the other hand, the RF (high frequency) signal output of the pickup 7 is amplified by an RF amplifier 15 and
MUSE is supplied to a demodulation circuit 16 comprising an M demodulator and the like.
The signal is demodulated. A slider motor for driving the slider carrying the pickup 7 in the radial direction to control the reading position of the pickup, a motor drive circuit, and the like are provided, but are not shown in the figure.

The MUSE signal output from the demodulation circuit 16 is supplied to a clamp circuit 18 and a disk code reading circuit 20 via an LPF (low-pass filter) 17. The clamp pulse is supplied from the synchronization detection circuit 30 to the clamp circuit 18 via the switch 19. Switch 19 is configured to be turned on in response to the control signal S _B outputted from the system controller 10. The clamp circuit 18 reproduces a DC component by clamping a predetermined portion of the MUSE signal to, for example, a 128/256 level by the supplied clamp pulse. This clamp circuit 1
The MUSE signal DC-reproduced by 8 is supplied to an A / D (analog / digital) conversion circuit 21. Also, the disk code reading circuit 20 has an MU as described later.
A control disk code inserted in a portion corresponding to the 564th line of the SE signal is detected to generate a disk code detection pulse p2, while reading the disk code and outputting data DC representing the contents of the disk code. It is configured.

The A / D conversion circuit 21 further includes a PLL circuit 2
3 output pulses c are supplied. A / D conversion circuit 2
1, the output pulse c of the PLL circuit 23 causes M
The USE signal is sampled, and the obtained sample values are sequentially converted into digital data. The sample data output from the A / D conversion circuit 21 is stored in the memory 2
9 and the synchronization detection circuit 30. Synchronous detection circuit 3
The output pulse c of the PLL circuit 23 is supplied to 0. The synchronization detection circuit 30 detects the frame pulse point and outputs the FP detection pulse p1 as described later, while the HD phase corresponding to the phase difference between the 128-level HD point which is the phase reference point of the synchronization signal and the pulse c is output. In addition to outputting the error signal e1, an HD detection signal e that is not necessarily synchronized with the HD point by detecting the HD signal based on the HD signal waveform
2 is output and the clamp pulse f is generated. Further, the synchronization detection circuit 30 outputs the signals e1,
An HD detection OK signal d is generated by the occurrence of e2.

On the other hand, the disk code detection pulse p2 output from the disk code reading circuit 20 and the FP detection pulse p1 output from the synchronization detection circuit 30 are supplied to a frequency discrimination circuit 25. The frequency discriminating circuit 25 outputs a signal between the two detection pulses p1 and p2 or p2 and p2 by a count clock pulse k output from the frequency dividing circuit 32, for example.
The data obtained by counting in the period between
A / A conversion is performed to output a frequency discrimination signal, and when the value of the D / A conversion input is stabilized, a servo lock detection signal 1 is generated. The frequency discrimination signal output from the frequency discrimination circuit 25 is
6 is one input of the changeover switch 11. The servo lock detection signal 1 is supplied to the system controller 10.

The HD detection signal e2 output from the synchronization detection circuit 30 is supplied to the system controller 10, the phase comparison circuit 31, the frequency discrimination circuit 33, and the reset circuit 40. The phase comparison circuit 31 compares the phase of the HD detection signal e2 with the reference HD signal output from the frequency dividing circuit 32 to generate a phase difference signal m corresponding to the phase difference between the two signals. When the level of m becomes equal to or less than a predetermined value, an HD servo lock detection signal n is generated. The frequency discriminating circuit 33 counts the frequency of the HD detection signal e2 by the count clock pulse k output from the frequency dividing circuit 32 and converts the data obtained by D / D into
It is configured to perform A conversion and output as a frequency discrimination signal q. The frequency dividing circuit 32 divides the reference clock a output from the reference clock generating circuit 24 by 4 to generate a count clock pulse k, and simultaneously divides the reference clock a by 48
The reference HD signal is generated by dividing the frequency by zero.

The reset circuit 40 is controlled by the control signal sF output from the system controller 10 to output the HD signal.
The reset signal is supplied to the frequency dividing circuit 32 at the same timing as when the detection signal e2 is generated. When the reset signal is output from the reset circuit 40, the frequency dividing circuit 32 sets the reference clock a to 480, for example.
The 480-base counter for frequency division is reset, the counting operation of the 480-base counter is newly started from the generation of the reset signal, and the phase of the reference HD signal is reset. Therefore, when the first HD detection signal e2 is generated after the reset signal is output from the reset circuit 40, the phase error between the reference HD signal and the HD detection signal e2 is:
At most, it is almost equal to the disk eccentricity. Therefore, the lock of the servo loop using the phase difference signal m corresponding to the phase difference between the HD detection signal e2 and the reference HD signal as an error signal by the reset circuit 40 can be advanced.

The phase difference signal m output from the phase comparison circuit 31 and the frequency discrimination signal q output from the frequency discrimination circuit 33 are supplied to a loop filter 39. The loop filter 39 is composed of, for example, an analog active filter for compensating the phase of the phase difference signal m and the frequency discrimination signal q, as described later. The analog active filter is a control signal sE output from the system controller.
To generate a control center value of the output. The output of this loop filter 39 is
It is another input of the changeover switch 11.

The changeover switch 11 is configured to selectively output one of the output of the loop amplifier 26 and the output of the loop filter 39 according to a control signal sD output from the system controller 10. When the output of the changeover switch 11 is selectively output from the changeover switch 9 and the output of the loop amplifier 26 is selectively output from the changeover switch 11, the pickup 7, the RF amplifier 1
5, a servo loop composed of a demodulation circuit 16, an LPF 17, a disk code reading circuit 20, a frequency discrimination circuit 25, a loop amplifier 26, changeover switches 11, 9, a drive amplifier 13, and a spindle motor 2 (hereinafter referred to as an FP / DC servo loop) ) Is closed, the rotation speed of the spindle motor 2 is controlled in accordance with the frequencies of the FP detection pulse p1 and the disc code detection pulse p2, and coarse adjustment of the time axis is performed by these detection pulses p1 and p2.

Further, the changeover switch 9 is changed to the changeover switch 1
1 is selectively output and the output of the loop filter 39 is selectively output from the changeover switch 11 when the pickup 7, RF amplifier 15, demodulation circuit 16, LP
F17, clamp circuit 18, A / D conversion circuit 21, synchronization detection circuit 30, phase comparison circuit 31, frequency discrimination circuit 3
3. A servo loop (hereinafter, referred to as an HD servo loop) including the loop filter 39, the changeover switches 11, 9, the drive amplifier 13, and the spindle motor 2 is closed,
The rotation speed of the spindle motor 2 is controlled in accordance with the frequency of the HD detection signal e2 and the phase difference between the HD detection signal e2 and the reference HD signal, and the time axis is roughly adjusted by the HD signal. The reason why the frequency system is added to the HD servo loop is to take damping of the loop, and it is possible to configure only the phase system.

The HD phase error signal e1 output from the synchronization detection circuit 30 is input to one input of a changeover switch 34 in the PLL circuit 23. The changeover switch 34 is supplied with a phase error signal output from the phase comparison circuit 35 as another input. The phase comparing circuit 35 includes a frequency dividing circuit 32
By the reference HD signal output from the
The output of the VCO 37 divided by 80 is supplied.
A phase difference signal corresponding to the phase difference between these two signals is generated. The changeover switch 34 outputs the HD phase error signal e according to the control signal s = output from the system controller 10.
1 and one of the phase error signals from the phase comparison circuit 35 is selectively output. The output of the changeover switch 34 is output to the VCO via a control signal generation circuit 38 including a loop filter, a loop gain adjustment amplifier, and the like.
37 is supplied as a control input to form a PLL loop. Then, the VCO 37 outputs a variable timing signal having a center frequency of 16.2 MHz whose oscillation is controlled by the HD phase error signal e1 or the phase error signal with the reference HD signal. The output of this VCO 37 is the PLL circuit 2
3 is supplied to the A / D conversion circuit 21, the write address controller 29a, and the synchronization detection circuit 30 as an output c.

The memory 29 is, for example, a two-frame memory, and sequentially writes sample data output from the A / D conversion circuit 21 to a designated write address in synchronization with a write pulse from the write address controller 29a. .
Here, the control signal S _C from the system controller 10 is used.
When the HD phase error signal e1 is selectively output from the changeover switch 34, the PLL circuit 23 outputs a variable timing signal c having a center frequency of 16.2 MHz synchronized with the HD detection signal e1. Accordingly, the variable timing signal c has the same time axis fluctuation as the MUSE signal, and the sample data is written into the memory 29 by the variable timing signal c, and the written data is transferred to the reference clock a having no time axis fluctuation. In synchronization with the read pulse generated from the controller 29b, the read is performed from the designated read address, and the time axis is finely adjusted.
By this fine adjustment of the time axis, jitter caused by eccentricity of the disk or the like is removed. A series of sample data read from the memory 29 is supplied to a decoder (not shown) and the like. Note that the write address controller 29a
While the write operation is stopped in response to the write stop signal WDE,
When the writing of the first frame of the read MUSE signal is completed, the first
A frame write completion pulse W1 is generated, and a second frame write completion pulse W2 is generated when the writing of the second frame is completed. When receiving the read mode change command R2, if the read address at that time corresponds to the first frame, the read address controller 29b finishes reading the read address, and then continuously reads the second and subsequent frames in frame units. If the read address corresponds to the second frame at the time of R2 reception, after reading this, the first frame is read once, and then only the second frame is read continuously.

The system controller 10 is formed of, for example, a microcomputer including a processor, a ROM, a RAM, a timer for time management, and the like. The system controller 10 includes an output voltage vP of the potentiometer and an HD detection O generated by the synchronization detection circuit 30.
K signal d, HD detection signal e2, FP detection pulse p1,
The disk code detection pulse p2, the output data DC of the disk code reading circuit 20, the FP / DC servo lock detection signal 1, the HD servo lock detection signal n, a command corresponding to a key operation of an operation unit (not shown), and the like are input. You. In the system controller 10, the processor processes the input signal according to a program stored in the ROM in advance, and controls each unit by the control signals sA to sF and the like.

FIG. 3 shows a specific configuration of the frequency discrimination circuit 25 to which the disc code detection pulse p2 output from the disc code reading circuit 20 and the FP detection pulse p1 output from the synchronization detection circuit 30 are supplied. As shown in FIG. 3, the FP detection pulse p1 is supplied directly to the control circuit 251 and the disk code detection pulse p2 is supplied to the control circuit 251 via the delay circuit 252. The delay circuit 252 adjusts the timing between the detection pulses p1 and p2 by delaying the detection pulse p2 by a predetermined time.

In the control circuit 251, the detection pulse p1
And the detection pulse p2 delayed by the delay circuit 252
Are the D-type flip-flops 253 and 254, respectively.
It is input. D-type flip-flops 253, 25
4 is supplied with a count clock k. Therefore, the detection pulse p1 and the delay circuit 252
Each time the detection pulse p2 delayed by the above is supplied to the control circuit 252, the pulse p existing during the period from the rising edge of the count clock k to the next rising edge
1 'and p2' are output. These pulses p1 ', p
2 'is supplied to a latch pulse generation circuit 256 and a load pulse generation circuit 257 via an OR (logical sum) gate 255. At the same time, the pulse p1 'is R-S
Supplied to the set input terminal of the flip-flop 258,
p2 'is supplied to the reset input terminal of RS flip-flop 258.

The latch pulse generating circuit 256 is composed of, for example, a delay circuit for delaying an input pulse by a predetermined time and a monostable multivibrator triggered by the output of the delay circuit, and is one pulse from the time when the pulse p1 'or p2' is generated.
The configuration is such that the latch pulse pA existing over a time T2 [where (T1 + T2) <1 clock period] is outputted after a time T1 shorter than the / 2 clock period. Note that the latch pulse generation circuit 265 outputs a latch stop command LD.
The generation of the latch command output is stopped according to E. Further, the load pulse generation circuit 257 includes the latch pulse generation circuit 2
56, and the pulse p1 'or p2'
T3 [where T3> (T1 + T2)] from the occurrence of
Later, time T4 [however, (T1 + T2 + T3 + T4)> 1
[Clock period] is output. The Q output of the RS flip-flop 258 is supplied to the load data generation circuit 259 as a load data switching control signal p =.

When the load data switching control signal pC is at a high level, the load data generation circuit 259 outputs, for example, "12".
The load data generation circuit 259 generates data corresponding to "0" and generates data corresponding to "0" when the load data switching control signal pC is at a low level. The counter 260 presets the output data of the load data generation circuit 259 as count data by the rising edge of the count clock k during the existence period of the load pulse pB, and counts up by the count clock k. The output data of the counter 260 is supplied to a latch circuit 261. A latch pulse pA is supplied to a clock input terminal of the latch circuit 261.
The output data of 60 is held in the latch circuit 261.

The data held in the latch circuit 261 is D / A
The signal is converted into an analog signal by the conversion circuit 262 and output as a frequency discrimination signal. The operation of the frequency discrimination circuit 25 having such a configuration is described in detail in Japanese Patent Application Laid-Open No. 3-44868, and will not be described here. The operation of the processor of the system controller 4 in the above configuration will be described with reference to the flowchart of FIG.

When a start command is issued by a key operation of the operation unit during execution of the main routine or the like, the processor performs initial setting of each switch by control signals S _{A to} S _E , and switches from the changeover switch 9 to the acceleration signal generation circuit 12. Is selectively output, the switch 19 is turned off, the loop filter 39 is initialized, the output of the loop amplifier 26 is selectively output from the changeover switch 11, and the reference HD signal is output from the changeover switch 34. Is selectively output (step S1). By this step S1, the loop filter 39 enters the clamp state.

Next, the processor sends a drive command to the drive circuit of the slider motor for moving the slider carrying the pickup 7 in the radial direction to move the pickup 7 to the start position of the play operation (step S2), and starts up. An ON command signal i is sent to the signal generation circuit 12 to accelerate the spindle motor 2 and start a timer for time management (step S3).

Next, the processor determines whether or not the disk code detection pulse p2 and the FP detection pulse p1 are output from the disk code reading circuit 20 and the synchronization detection circuit 30, respectively (step S4), and determines whether or not time is over, that is, time management. And whether or not the detection data p1 and p2 are output within a predetermined time from the start-up is determined by alternately determining whether or not the output data of the timer for use has exceeded a predetermined value (step S5). Make a decision. The detection pulses p1 and p2 are obtained by steps S4 and S5.
Is determined to have been output within a predetermined time, the processor causes the output of the loop amplifier 26 via the changeover switch 9 through the changeover switch 11 to be selectively output from the changeover switch 9 in accordance with the control signal S _A so as to selectively output the FP / DC servo loop. Is turned on and the timer for time management is restarted (step S6).

Next, the processor determines whether or not the FP / DC servo lock detection signal 1 and the HD detection signal e2 are output within a predetermined time after the FP / DC servo loop is turned on (steps S7 and S8). Step S7, S8
When it is determined that the FP / DC servo lock detection signal 1 and the HD detection signal e2 have been output within the predetermined time, the processor supplies the control signal sF to the reset circuit 40 to reset the frequency dividing circuit 32 (step S9),
The time when the HD phase error is output from the phase comparison circuit 31 is detected by the next HD detection signal e2, and the output of the loop filter 39 is selectively output from the changeover switch 11 by the control signal sD. Is turned on, the timer for time management is restarted, and the switches 51 and 54 of the loop filter 39 are turned on and the switch 56 is turned off by the control signal sE to release the clamp state (step S10). Thereafter, the processor determines whether the HD servo lock detection signal n is output within a predetermined time after the HD servo loop is turned on (steps S11 and S12). Step S11, S1
When it is determined that the HD servo lock detection signal n has been output within the predetermined time by 2, the processor resumes the execution of the routine executed immediately before shifting to step S <b> 1. If it is determined in steps S11 and S12 that the HD servo lock detection signal n has not been output within the predetermined time, the processor determines that the detection pulses p1 and p2
Is output (step S1).
3). If it is determined in step S12 that the detection pulses p1 and p2 have been output, the processor proceeds to step S6 again.

At steps S4 and S5, the detection pulse p
If it is determined that 1, p2 has not been output within the predetermined time, the processor causes the changeover switch 9 to selectively output the output of the control signal generation circuit 8 by the control signal s =, and executes the FG servo loop. Turn on (step S14). After this, the processor detects the detection pulses p1,
The determination as to whether or not p2 is output is repeatedly performed (step S15), and the process proceeds to step S6 only when it is determined that the detection pulses p1 and p2 have been output.

In steps S7 and S8, FP /
When it is determined that the DC servo lock detection signal 1 and the HD detection signal e2 have not been output within the predetermined time, and when it is determined in step S13 that the detection pulses p1 and p2 have not been output, the processor also executes step S1.
Move to 4. The rotation operation of the spindle motor 2 is started by step S3 in the above operation, and the rotation speed of the disk 1 is gradually increased. When the rotation speed of the disk 1 approaches a specified rotation speed and falls within a predetermined range determined by the transmission rate of the disk code, the disk code in the MUSE signal output from the demodulation circuit 16 can be read, and the disk code can be read. The reading circuit 20 outputs a disk code detection pulse p2. At the same time, the synchronization detection circuit 30 detects a frame pulse by pattern recognition, and outputs a detection pulse p1.

When the detection pulses p1 and p2 are output within a predetermined time from the start, the FP is determined in steps S4 to S6.
/ DC servo loop is turned on. At this time, in the frequency discrimination circuit 25, a time interval between the output of the detection pulse p1 and the output of the detection pulse p2 and a time interval between the output of the detection pulse p2 and the output of the detection pulse p1. Is measured, an error signal having a level corresponding to the obtained value is generated, and frequency discrimination is performed. The FP / DC servo loop operates by the error signal output from the frequency discrimination circuit 25. FP
Since the / DC servo loop is a frequency control loop using the detection pulses p1 and p2, it is possible to widen the loop band as compared with the case where the detection pulse p1 or p2 alone forms a loop, Both quick response and stability can be improved. If necessary, phase control can be applied.

With this FP / DC servo loop, the rotation speed of the disk 1 can be set to a value within a range of ± several% of the specified rotation speed. When the FP / DC servo loop is locked, HD detection in the synchronization detection circuit 30 becomes possible, and an HD detection signal e2 is output. FP / D
This FP / DC servo loop is locked within a predetermined time after the C servo loop is turned on, and the HD
When the detection signal e2 is output, the FP / DC servo loop is turned off in steps S7 to S10, and
The D servo loop is turned on, and coarse adjustment of the time axis by the HD signal is started.

Since the HD signal has a higher frequency rate than the disc code, the HD servo loop is turned on to improve the loop characteristics such as broadening the loop band of the spindle servo loop. Good stability. Also, the detection pulses p1,
When p2 is not output within a predetermined time from the start-up and within a predetermined time after the FP / CD servo loop is turned on, the FP / CD servo loop is locked and the HD detection signal e2 is output. If not, and if the lock state is not established within a predetermined time after the HD servo loop is turned on and the detection pulses p1 and p2 are not output, the FG servo loop is turned on in step S13. This FG servo loop is for protection in the event that disk code detection and FP detection cannot be performed, and when the FG servo loop is turned on,
The rotation speed of the spindle motor 2 is controlled so that the output voltage of the F / V conversion circuit 4 becomes equal to the reference voltage output from the reference voltage generation circuit 6.

The operation at the time of startup has been described above. The operation of the controller 10 in one scan mode of the special reproduction mode and the operation of each unit associated therewith will be described with reference to the flowchart of FIG. Controller 10
Receives the scan mode command from the operation unit and executes the subroutine of FIG. 5 by interrupting the main routine.
In this subroutine, first, the second frame write completion pulse W2 from the write address controller 29a
(Step S20), and when this is received, the write stop command WDE flag is set and the memory read mode change command R2 flag is set (step S21). When the R2 flag is set, the read address controller 29b repeatedly reads only the second frame after reading the first frame once.

Next, in response to a command SD, the spindle servo is switched to the FP / DC loop side and a slider (not shown)
(Step S22). Then LD
The E (Latch Disable) command is sent to the frequency discrimination circuit 25
To cause the frequency discrimination circuit 25 to hold the immediately preceding frequency discrimination result, and to issue a VC
The oscillation control of O37 is switched to the PLL using the reference clock (step S23). Then, the tracking servo loop is turned off for about 10 ms (steps S24 and S2).
5, S26), causing the reading point 7a to perform a track jump operation, that is, a jump operation. After that, the LDE command is released and the frequency discriminating operation of the frequency discriminating circuit 25 is restarted (step S27). Next, a servo lock detection signal 1 from the frequency discrimination circuit 25 is waited (step S2).
8) When this is received, the oscillation control of the VCO 37 is switched to be performed by the HD signal (step S2).
9). While the FP / DC servo is locked, the HD signal can be detected from the read signal. The switching of the oscillation control is performed by detecting the first p1 pulse after receiving the signal l.

Next, when the HD detection OK signal d is detected (step S30), it is determined that the PLL servo for the VCO 37 is locked, and the WDE command is reset or released based on the next p1 detection timing (step S31). ). As a result, the memory 29 starts writing the reproduced signal data after the A / D conversion in order from the first frame. When the W1 flag is issued from the write address controller 29a, this is detected (step S32), and R
2 flag is reset, that is, released (step S3)
3). As a result, the read address controller 29b specifies the read address so as to also perform the read for the first frame. When the W2 flag is confirmed (step S34), it is determined that the writing of the second frame has been completed, and the R2 flag for designating a reading mode in which the first frame is read once and then only the second frame is repeatedly read is set. At the same time, a WDE instruction is given to the write address controller 29a to inhibit the write operation (step S35). If it is determined that the scan mode has not been completed, the operation from step S23 is repeated (step S36).

According to the above-described memory read control by the R2 flag, the discontinuous portion of the read signal due to the jump operation in the scan mode is immediately before the memory 29.
Since the second frame of the two frames of the video signal read in is output repeatedly, a clear reproduced image can be obtained. Of course, the first and second frames may be repeatedly read.

Although the A / D converter 21 is used in the circuit of FIG. 1, the A / D converter 21 becomes unnecessary when the sampled video signal is recorded as a digital signal. In addition, the D / A
An analog output may be provided by providing a converter. Further, in order to cope with the pause mode as another special reproduction mode, step S in the flowchart of FIG.
It is sufficient to delete the slider fast-forwarding of No. 22 and change it to perform the one-track jump-back operation in step S25. Furthermore, for the frame feed mode, the slider fast-forward in step S22 may be deleted, and the waiting operation in step S25 may be changed to, for example, a jump-back operation of about 10 frames.

[0043]

As is apparent from the above description, in the recording disk playing apparatus according to the present invention, during the special reproduction mode, the spindle servo is performed by the FP / DC loop while the read signal is written to the memory. Is controlled by the HD signal in the read signal, so that the servo lock of the spindle servo system can be obtained in a short time, while two frames for the memory for compensating for the discontinuity of the read signal. Is written correctly, and a quick special reproduction mode operation is performed, while a reproduced image without disturbance is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a format of a disc code in a MUSE signal.

FIG. 3 is a block diagram illustrating a circuit example of a frequency discrimination circuit in the device of FIG. 1;

FIG. 4 is a flowchart illustrating an operation of a processor in the apparatus of FIG. 1;

FIG. 5 is a flowchart illustrating an operation of a processor in the apparatus of FIG. 1;

[Description of Signs of Main Parts]

 2 Spindle motor 9, 11, 34 Changeover switch 10 System controller 20 Disk code reading circuit 25, 33 Frequency discrimination circuit 30 Synchronization detection circuit 31 Phase comparison circuit 40 Reset circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Nagaki 4-2610 Hanazono, Tokorozawa-shi, Saitama Pioneer Corporation Inside the Tokorozawa Plant (72) Inventor Tetsuya Tenma 4-2610 Hanazono, Tokorozawa-shi, Saitama Pioneer Corporation Inside Tokorozawa Plant (72) Inventor Masami Oishi 4-2610 Hanazono, Tokorozawa City, Saitama Prefecture Pioneer Corporation Inside Tokorozawa Plant (56) References JP-A-2-210664 (JP, A) JP-A-3-44868 (JP) , A)

Claims (1)

(57) [Claims] A first synchronization signal having a predetermined level point as a phase reference point of a sampling timing signal; and a second synchronization signal generated at a cycle N (N is a natural number) times the first synchronization signal. A recording disk playing device for playing a recording disk carrying a sampled video signal in which a control code is inserted at the same cycle as a second synchronizing signal, wherein the recording disk playing device is turned on in response to a first command to read a reading point on the recording disk. A first spindle servo loop for controlling the rotation speed of the recording disk based on a first synchronizing signal in the read signal obtained from the controller, and a control code in the read signal which is turned on in response to a second command and detected A second signal for controlling the time axis by controlling the rotation speed of the recording disk based on the time interval between the detection signal and the second synchronization signal in the read signal. A pindle servo loop, tracking servo means for performing a jump operation on the read point in response to a jump command, and sequentially taking in a sampled video signal in the read signal in synchronism with a write clock for each unit section to a read clock. Memory means for sequentially reading data in response to the first clock signal;
Write clock generation means for generating the clock based on one of the timings of the synchronization signal, and during the special reproduction mode, the second clock is used instead of the first command.
While issuing the jump command, the second
A recording disk playing device, comprising: control means for causing said write clock generation means to generate a write clock based on said first synchronization signal during a lock period of a spindle servo.