JPH05314647A - Device for playing sampled video signal recording disk - Google Patents

Abstract

PURPOSE:To surely execute special reproduction and to obtain a reproducing image without disturbance by executing a spindle with an FP/DC loop at the time of special reproducing and executing phase control immediately after Jump with an HD signal in a read signal. CONSTITUTION:At the special reproducing mode, by a system controller 10, the spindle motor of a spindle motor 2 is operated by the FP/DC servo loop. Thus, the rotation of a disk 1 is made within the range of + or - several %. Then the clock of the read signal for writing in a memory is phase-controlled by the HD signal in the read signal. Thus, the servo lock of a spindle servo system is obtained in a short time and the write, as well by 2 frames to the memory for compensating the discontinuity of the read signal is executed correctly and rapid special reproducing mode operation is executed and the reproducing image without disturbance is obtained.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to MUSE (Multiple Sub-Nygui).
The present invention relates to a recording disk playing device for playing a recording disk such as an optical disk in which a sampled video signal such as st Sampling Encoding) is recorded.

[0002]

2. Description of the Related Art Such a recording disk playing device is disclosed, for example, in Japanese Patent Laid-Open No. 3-44868. This recording disk playing device has a time axis control based on a frame pulse signal and a control code signal extracted from a read MUSE signal in addition to a first servo loop which performs time axis control based on a horizontal synchronizing signal extracted from a read MUSE signal. The second servo loop is formed, and the time axis control is performed by the second servo loop while the first servo loop is in the unlocked state. In any case, the time axis control device performs time axis control based on the synchronization signal obtained from the read MUSE signal. Therefore, when the read MUSE signal is A / D converted, resampling is performed at the transmission sampling frequency. Therefore, it is preferable to manage the reproduction timing of the MUSE signal in the player.

[0003]

By the way, the scan,
During a so-called special reproduction operation involving a jump operation of a reading point such as still or frame advance, the read MUSE signal becomes discontinuous, and during that time-axis servo by the read synchronization signal becomes impossible. As a result, the screen reproduced through the MUSE decoder is greatly disturbed, which is not preferable.

[0004]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a sampled video signal recording disk playing device capable of avoiding the disturbance of the reproduction screen during the special reproduction operation.

[0005]

A recording disk playing device according to the present invention has a first sync signal having a predetermined level point as a phase reference point of a sampling timing signal and N times (N is a natural number) times the first sync signal. A recording disk playing device for playing a recording disk carrying a sampled video signal in which a control code is inserted in the same cycle as the second synchronizing signal in addition to a second synchronizing signal generated in a cycle, and which responds to a first command. Is turned on to turn on in response to a second command and a first spindle servo loop that controls the rotational speed of the recording disk based on a first synchronization signal in a read signal obtained from a reading point on the recording disk. Each time the control code in the read signal is detected, a detection signal is generated, and the recording data is recorded based on the time interval between the detection signal and the second synchronization signal in the read signal. A second spindle servo loop that performs time axis control by controlling the rotational speed of the disk, tracking servo means that performs a jump operation with respect to the reading point in response to a jump command, and a sampled video signal in the reading signal that is a unit section thereof. Memory means for sequentially taking in each of them in synchronization with a write clock and sequentially reading in accordance with a read clock; and write clock generation for generating the write clock based on either the reference clock or the first synchronization signal timing. In the special reproduction mode period, the second command is issued instead of the first command, while the jump command is issued, and the write command is issued during the lock period of the second spindle servo. The embedded clock generating means and the control means for generating the write clock based on the first synchronizing signal. It is a recording disk playing apparatus according to claim.

[0006]

According to the recording disk playing device of the present invention having the above-mentioned structure, during the special reproduction mode, the spindle servo is executed in accordance with the second synchronizing signal, that is, the frame pulse and the control code, that is, the so-called disk code, and the data is sent to the memory. The write clock of the first synchronizing signal is H
It is generated at a timing based on the D signal.

[0007]

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 5. In FIG. 1, the disk 1
Is driven to rotate by a spindle motor 2. On the disc 1, a MUSE signal is recorded in which the disc code as shown in FIG. 2 is inserted in the portions of sample numbers 19 to 474 of the 564th line.

The disk code is modulated by a bi-phase modulation method, and is an 8-bit synchronization pattern code, a 4-bit area identification code, an 8-bit chapter number code, a 24-bit frame number code, and a 20-bit disk status. It consists of a code and a 12-bit user code. Each of these codes is composed of a BCD code, and the area identification code is a code for identifying which of lead-in area, program area, and lead-out area. The chapter number code and the frame number code are codes representing the chapter number and the frame number, respectively. The disc status code is a code indicating the recording mode (CLV, CAV), disc size, and the like.

The transmission rate of this disc code is 6 clocks / bit (= 2.7 Mbps). The value of the transmission rate is determined in consideration of the read margin of the disc code at the time of starting or scanning and the amount of recorded information. That is, it is possible to reduce the transmission rate by considering only the read margin, but doing so reduces the amount of information. Further, the value of this transmission rate is different from the control code (2 clocks / baud) of the MUSE signal and the FP pulse, and the detection accuracy during normal reproduction can be improved.

The spindle motor 2 has a built-in frequency generator 3 for generating an FG signal having a frequency corresponding to the rotation speed of the spindle motor 2. The FG signal output from the frequency generator 3 is supplied to the F / V conversion circuit 4 composed of a differentiating circuit or the like and converted into a signal having a level according to the frequency of the FG signal. The output of the F / V conversion circuit 4 is supplied to the addition / subtraction circuit 5. The adder / subtractor circuit 5 has
The output of the reference voltage generation circuit 6 is supplied. A potentiometer connected to the reference voltage generating circuit 6 so as to generate a voltage according to a relative position (hereinafter, referred to as a radial position) of a slider (not shown) carrying a pickup 7 in the radial direction with respect to the disk 1. (Not shown)
Output voltage vP is supplied. Reference voltage generation circuit 6
Is configured to generate a reference voltage according to the radial position of the pickup 7 by the output voltage vP of the potentiometer.

In the addition / subtraction circuit 5, the output of the F / V conversion circuit 4 is subtracted from the output of the reference voltage generation circuit 6 to generate an error signal. The output of the adder / subtractor circuit 5 is one input of a changeover switch 9 via a control signal generating circuit 8 including a loop filter, a loop gain adjusting amplifier and the like. The changeover switch 9 is a system controller 10
The control signal generation circuit 8, the changeover switch 11 and the acceleration signal generation circuit 12 are selectively output according to the control signal S _A output from the control signal S _A. Further, the acceleration signal generation circuit 12 is the system controller 1
In response to the ON command signal i supplied from 0, a drive signal of a predetermined level for accelerating the spindle motor 2 is generated. The output of the changeover switch 9 is supplied as a drive signal to the spindle motor 2 via the drive amplifier 13 to control the rotation speed of the disk 1.
When the output of the control signal generation circuit 8 is selectively output from the changeover switch 9 at the time of start-up, the frequency generator 3,
The servo loop (hereinafter referred to as FG servo loop) formed by the F / V conversion circuit 4, the addition / subtraction circuit 5, the control signal generation circuit 8, the changeover switch 9, the drive amplifier 13 and the spindle motor 2 is turned on and the disc 1 is turned on. The drive control of the spindle motor 2 is performed so that the rotation speed of the above converges to the specified speed at the radial position of the pickup 7. A tracking servo circuit 7b for performing tracking servo of the information reading point 7a on the disk 1 of the pickup 7
Is provided. Then, the tracking servo circuit 7
The servo loop of b is turned on / off by a command from the control circuit 10.

On the other hand, the RF (high frequency) signal output of the pickup 7 is amplified by the RF amplifier 15 and then F
MUSE is supplied to the demodulation circuit 16 including an M demodulator.
The signal is demodulated. A slider motor, a motor drive circuit, and the like for driving the slider carrying the pickup 7 in the radial direction to control the reading position of the pickup are provided, but they are omitted in this figure.

The MUSE signal output from the demodulation circuit 16 is supplied to a clamp circuit 18 and a disc code reading circuit 20 via an LPF (low pass filter) 17. A clamp pulse is supplied to the clamp circuit 18 from the synchronization detection circuit 30 via the switch 19. The switch 19 is configured to be turned on according to the control signal S _B output from the system controller 10. In addition, the clamp circuit 18 clamps a predetermined portion of the MUSE signal to, for example, 128/256 level by the supplied clamp pulse to reproduce the DC component. This clamp circuit 1
The MUSE signal DC-reproduced by 8 is supplied to the A / D (analog / digital) conversion circuit 21. Further, the disc code reading circuit 20 uses the MU as described later.
The disc code for control inserted in the portion corresponding to the 564th line of the SE signal is detected to generate the disc code detection pulse p2, while the disc code is read and the data DC representing the contents of the disc code is output. It is configured.

The A / D conversion circuit 21 further includes a PLL circuit 2
3 output pulses c are supplied. A / D conversion circuit 2
1, the output pulse c of the PLL circuit 23 causes M
The USE signal is sampled, and the obtained sample values are sequentially converted into digital data. The sample data output from the A / D conversion circuit 21 is stored in the memory 2
9 and the synchronization detection circuit 30. Sync detection circuit 3
The output pulse c of the PLL circuit 23 is supplied to 0. The synchronization detection circuit 30 detects the frame pulse point and outputs the FP detection pulse p1 as described later, while the HD phase corresponding to the phase difference between the 128-level HD point which is the phase reference point of the synchronization signal and the pulse c. The HD detection signal e which outputs the error signal e1 and detects the HD signal from the HD signal waveform and is not necessarily synchronized with the HD point
2 is output and the clamp pulse f is generated. Further, the synchronization detection circuit 30 outputs the signals e1 and
The HD detection OK signal d is generated by the generation of e2.

On the other hand, the disc code detection pulse p2 output from the disc code reading circuit 20 and the FP detection pulse p1 output from the synchronization detection circuit 30 are supplied to the frequency discriminating circuit 25. The frequency discriminating circuit 25 uses, for example, the count clock pulse k output from the frequency dividing circuit 32, between two detection pulses p1 to p2 or p2 to p2.
The data obtained by counting in the period between 1 is D
A / A conversion is performed to output as a frequency discrimination signal, and a servo lock detection signal 1 is generated when the value of the D / A conversion input is stable. The frequency discrimination signal output from the frequency discrimination circuit 25 is the loop amplifier 2
It is one input of the changeover switch 11 via 6. Further, the servo lock detection signal 1 is supplied to the system controller 10.

The HD detection signal e2 output from the synchronization detection circuit 30 is supplied to the system controller 10, the phase comparison circuit 31, the frequency discrimination circuit 33 and the reset circuit 40. The phase comparison circuit 31 performs a phase comparison between the HD detection signal e2 and the reference HD signal output from the frequency division circuit 32 to generate a phase difference signal m corresponding to the phase difference between the two signals and the phase difference signal m. The HD servo lock detection signal n is generated when the level of m becomes a predetermined value or less. The frequency discriminating circuit 33 counts the frequency of the HD detection signal e2 by the count clock pulse k output from the frequency dividing circuit 32 and outputs the data obtained by D /
The A-converted signal is output as a frequency discrimination signal q. The frequency dividing circuit 32 divides the reference clock a output from the reference clock generating circuit 24 into four to generate a count clock pulse k, and at the same time, outputs the reference clock a by 48.
It is configured to divide by 0 and generate a reference HD signal.

Further, the reset circuit 40 receives the HD signal according to the control signal sF output from the system controller 10.
The reset signal is supplied to the frequency dividing circuit 32 at the same timing as when the detection signal e2 is generated. When the reset signal is output from the reset circuit 40, the frequency divider circuit 32 outputs, for example, the reference clock a to 480.
The 480-base counter for frequency division is reset, the counting operation of the 480-base counter is newly started when the reset signal is generated, and the phase of the reference HD signal is reset. Therefore, when the first HD detection signal e2 is generated after the reset signal is output from the reset circuit 40, the phase error between the reference HD signal and the HD detection signal e2 is
At maximum, it is almost equal to the disc eccentricity. Therefore, the reset circuit 40 can quickly lock the servo loop using the phase difference signal m corresponding to the phase difference between the HD detection signal e2 and the reference HD signal as an error signal.

The phase difference signal m output from the phase comparison circuit 31 and the frequency discrimination signal q output from the frequency discrimination circuit 33 are supplied to the loop filter 39. The loop filter 39 is composed of, for example, an analog active filter that performs phase compensation of the phase difference signal m and the frequency discrimination signal q as described later, and this analog active filter is a control signal sE output from the system controller.
Is configured to produce a control center value of its output. The output of this loop filter 39 is
The other input of the changeover switch 11.

The change-over switch 11 is configured to selectively output one of the output of the loop amplifier 26 and the output of the loop filter 39 according to the control signal sD output from the system controller 10. When the output of the selector switch 11 is selectively output from the selector switch 9 and the output of the loop amplifier 26 is selectively output from the selector switch 11, the pickup 7 and the RF amplifier 1
5, a demodulation circuit 16, an LPF 17, a disk code reading circuit 20, a frequency discriminating circuit 25, a loop amplifier 26, changeover switches 11 and 9, a drive amplifier 13 and a spindle motor 2 (hereinafter referred to as FP / DC servo loop). ) Is closed, the rotational speed of the spindle motor 2 is controlled according to the frequencies of the FP detection pulse p1 and the disk code detection pulse p2, and the coarse adjustment of the time axis is performed by these detection pulses p1 and p2.

Also, from the changeover switch 9 to the changeover switch 1
When the output of 1 is selectively output and the output of the loop filter 39 is selectively output from the changeover switch 11, the pickup 7, the RF amplifier 15, the demodulation circuit 16, and the LP
F17, clamp circuit 18, A / D conversion circuit 21, synchronization detection circuit 30, phase comparison circuit 31, frequency discrimination circuit 3
3, the loop filter 39, the changeover switches 11 and 9, the drive amplifier 13 and the spindle motor 2 are closed to form a servo loop (hereinafter referred to as an HD servo loop),
The rotation speed of the spindle motor 2 is controlled according to the frequency of the HD detection signal e2 and the phase difference between the HD detection signal e2 and the reference HD signal, and the time axis is roughly adjusted by the HD signal. A frequency system is added to the HD servo loop in order to take damping of the loop, and it is possible to configure the phase system alone.

The HD phase error signal e1 output from the synchronization detection circuit 30 is one input of the changeover switch 34 in the PLL circuit 23. The phase error signal output from the phase comparison circuit 35 is supplied to the changeover switch 34 as another input. The phase comparison circuit 35 includes a frequency divider circuit 32.
4 by the reference HD signal output from the
The output of the VCO 37 divided by 80 is supplied,
A phase difference signal corresponding to the phase difference between these two signals is generated. The change-over switch 34 responds to the control signal s = output from the system controller 10 by the HD phase error signal e.
1 and one of the phase error signals from the phase comparison circuit 35 are selectively output. The output of the changeover switch 34 is passed through a control signal generation circuit 38 including a loop filter, a loop gain adjustment amplifier, etc.
37 is supplied as a control input to 37, forming a PLL loop. Then, the VCO 37 outputs a variable timing signal having a center frequency of 16.2 MHz, which is oscillation-controlled by the HD phase error signal e1 or the phase error signal with the reference HD signal. The output of this VCO 37 is the PLL circuit 2
The output c of 3 is supplied to the A / D conversion circuit 21, the write address controller 29a, and the synchronization detection circuit 30.

The memory 29 comprises, for example, a two-frame memory, and sequentially writes the sample data output from the A / D conversion circuit 21 to designated write addresses in synchronization with the write pulse from the write address controller 29a. ..
Here, the control signal S _C from the system controller 10
When the changeover switch 34 selectively outputs the HD phase error signal e1, the PLL circuit 23 outputs the variable timing signal c having a center frequency of 16.2 MHz which is phase-locked with the HD detection signal e1. Therefore, the variable timing signal c has the same time axis fluctuation as the MUSE signal, the sample data is written in the memory 29 by the variable timing signal c, and the written data is used as the reference clock a having no time axis fluctuation. The designated read address is read in synchronization with the read pulse generated from the controller 29b, and the time axis is finely adjusted.
By this fine adjustment of the time axis, the jitter caused by the eccentricity of the disc or the like is removed. A series of sample data read from the memory 29 is supplied to a decoder (not shown) or the like. The write address controller 29a is
While the write operation is stopped according to the write stop signal WDE,
Upon completion of writing the first frame of the read MUSE signal, the first
A frame writing completion pulse W1 is generated, and a second frame writing completion pulse W2 is generated when the writing of the second frame is completed. Further, when the read address controller 29b receives the read mode change command R2, if the read address at that time corresponds to the first frame, after reading this, the second and subsequent frames are read continuously in frame units. If the read address corresponds to the second frame when receiving R2, the first frame is read once after the read address is read, and then only the second frame is read continuously.

The system controller 10 is formed by a microcomputer including a processor, a ROM, a RAM, a timer for time management and the like. The system controller 10 includes a potentiometer output voltage vP and an HD detection O generated in the synchronization detection circuit 30.
K signal d and HD detection signal e2, FP detection pulse p1,
The disc code detection pulse p2, the output data DC of the disc code reading circuit 20, the FP / DC servo lock detection signal l, the HD servo lock detection signal n, a command according to the key operation of the operation unit (not shown), etc. are input. It In the system controller 10, the processor processes a signal input according to a program stored in advance in the ROM, and controls each unit by the control signals sA to sF.

FIG. 3 shows a specific configuration of the frequency discriminating circuit 25 to which the disc code detecting pulse p2 output from the disc code reading circuit 20 and the FP detecting pulse p1 output from the synchronization detecting circuit 30 are supplied. As shown in FIG. 3, the FP detection pulse p1 is directly supplied to the control circuit 251, and the disk code detection pulse p2 is supplied to the control circuit 251 via the delay circuit 252. The delay circuit 252 delays the detection pulse p2 by a predetermined time to adjust the timing between the detection pulses p1 and p2.

In the control circuit 251, the detection pulse p1
And the detection pulse p2 delayed by the delay circuit 252
Are the D-type flip-flops 253 and 254, respectively.
It is input. D-type flip-flops 253, 25
The count clock k is supplied to the clock input terminal of No. 4. Therefore, the detection pulse p1 and the delay circuit 252
Each time the detection pulse p2 delayed by is supplied to the control circuit 252, the pulse p existing during the period from the rising edge of the count clock k to the next rising edge.
1 ', p2' are output. These pulses p1 ', p
2 ′ is supplied to the latch pulse generating circuit 256 and the load pulse generating circuit 257 via the OR (logical sum) gate 255. Along with that, the pulse p1 'changes to R-S
It is supplied to the set input terminal of the flip-flop 258,
p2 ′ is supplied to the reset input terminal of the RS flip-flop 258.

The latch pulse generating circuit 256 is composed of, for example, a delay circuit for delaying an input pulse by a predetermined time and a monostable multivibrator triggered by the output of this delay circuit, and it is 1 when the pulse p1 'or p2' is generated.
The latch pulse pA existing for the time T2 [(T1 + T2) <1 clock period] is output after the time T1 which is shorter than the / 2 clock period. The latch pulse generation circuit 265 uses the latch stop command LD
The generation of the latch command output is stopped according to E. Further, the load pulse generating circuit 257 is the latch pulse generating circuit 2
It is formed in the same manner as 56 and has a pulse p1 'or p2'.
From the time of occurrence of T3 [however, T3> (T1 + T2)]
After time T4 [however, (T1 + T2 + T3 + T4)> 1
Clock period], the load pulse pB existing over the clock period is output. The Q output of the RS flip-flop 258 is supplied to the load data generation circuit 259 as the load data switching control signal p =.

The load data generation circuit 259 outputs, for example, "12" when the load data switching control signal pC is at a high level.
Data corresponding to "0" is generated, and when the load data switching control signal pC is at a low level, data corresponding to "0" is generated. The output data of the load data generating circuit 259 is a counter. The counter 260 is configured to preset the output data of the load data generation circuit 259 as count data at the rising edge of the count clock k during the existence period of the load pulse pB and count up at the count clock k. The output data of the counter 260 is supplied to the latch circuit 261. A latch pulse pA is supplied to the clock input terminal of the latch circuit 261 and the counter 2 is supplied by this latch pulse pA.
The output data of 60 is held in the latch circuit 261.

The data held in the latch circuit 261 is D / A.
It is converted into an analog signal by the conversion circuit 262 and output as a frequency discrimination signal. The operation of the frequency discriminating circuit 25 having such a configuration is described in detail in Japanese Patent Application Laid-Open No. 3-44868, so it will be omitted here. The operation of the processor of the system controller 4 having the above configuration will be described with reference to the flowchart of FIG.

When a start command is issued by a key operation of the operation unit during execution of the main routine or the like, the processor initializes each switch by the control signals S _{A to} S _E , and the changeover switch 9 causes the acceleration signal generation circuit 12 to operate. Is selectively output, the switch 19 is turned off, the loop filter 39 is initialized, the output of the loop amplifier 26 is selectively output from the changeover switch 11, and the reference HD signal is output from the changeover switch 34. Is selectively output (step S1). By this step S1, the loop filter 39 is in a clamped state.

Next, the processor sends a drive command to the drive circuit of the slider motor that moves the slider carrying the pickup 7 in the radial direction, moves the pickup 7 to the start position of the play operation (step S2), and starts it. An ON command signal i is sent to the signal generation circuit 12 to accelerate the spindle motor 2 and start a timer for time management (step S3).

Next, the processor determines whether or not the disc code detection pulse p2 and the FP detection pulse p1 are respectively output from the disc code reading circuit 20 and the synchronization detection circuit 30 (step S4), and whether the time is over, that is, time management. It is determined whether the detection pulses p1 and p2 are output within a predetermined time from the start-up by alternately determining whether or not the output data of the timer for output is equal to or more than a predetermined value (step S5). Make a decision. The detection pulses p1 and p2 are determined by steps S4 and S5.
Is determined to have been output within a predetermined time, the processor causes the control signal S _A to selectively output the output of the loop amplifier 26 from the change-over switch 9 through the change-over switch 11 so as to output the FP / DC servo loop. Is turned on and the timer for time management is restarted (step S6).

Next, the processor determines whether or not the FP / DC servo lock detection signal 1 and the HD detection signal e2 are output within a predetermined time after the FP / DC servo loop is turned on (steps S7 and S8). Steps S7 and S8
When it is determined that the FP / DC servo lock detection signal 1 and the HD detection signal e2 are output within the predetermined time by the processor, the processor supplies the control signal sF to the reset circuit 40 to reset the frequency dividing circuit 32 (step S9),
The next HD detection signal e2 is used to detect the time when the HD phase error is output from the phase comparison circuit 31, and the control signal sD is used to selectively output the output of the loop filter 39 from the changeover switch 11 so as to output the HD servo loop. Is turned on and the timer for time management is restarted, and the switches 51 and 54 in the loop filter 39 are turned on and 56 is turned off by the control signal sE to release the clamped state (step S10). After that, the processor determines whether the HD servo lock detection signal n is output within a predetermined time after the HD servo loop is turned on (steps S11 and S12). Steps S11 and S1
When it is determined by 2 that the HD servo lock detection signal n is output within the predetermined time, the processor restarts the execution of the routine that was being executed immediately before the shift to step S1. When it is determined in steps S11 and S12 that the HD servo lock detection signal n is not output within the predetermined time, the processor detects the detection pulses p1 and p2.
Is output (step S1)
3). When it is determined in step S12 that the detection pulses p1 and p2 are output, the processor proceeds to step S6 again.

The detection pulse p is determined in steps S4 and S5.
When it is determined that 1 and p2 have not been output within the predetermined time, the processor causes the changeover switch 9 to selectively output the output of the control signal generation circuit 8 by the control signal s =, and sets the FG servo loop. It is turned on (step S14). After this, the processor detects the detection pulse p1,
The determination as to whether or not p2 is output is repeated (step S15), and the process proceeds to step S6 only when it is determined that the detection pulses p1 and p2 are output.

Further, in steps S7 and S8, FP /
When it is determined that the DC servo lock detection signal 1 and the HD detection signal e2 are not output within the predetermined time, and when it is determined in step S13 that the detection pulses p1 and p2 are not output, the processor also executes step S1.
Go to 4. The rotation operation of the spindle motor 2 is started by step S3 in the above operation, and the rotation speed of the disk 1 is gradually accelerated. When the rotation speed of the disk 1 approaches the specified rotation speed and becomes a value within a predetermined range determined by the transmission rate of the disk code, the disk code in the MUSE signal output from the demodulation circuit 16 can be read, and the disk code can be read. A disc code detection pulse p2 is output from the reading circuit 20. At the same time, the synchronization detection circuit 30 detects a frame pulse by pattern recognition and outputs a detection pulse p1.

When the detection pulses p1 and p2 are output within a predetermined time from the start-up, the FP is processed in steps S4 to S6.
/ DC servo loop turns on. Further, at this time, in the frequency discrimination circuit 25, the time interval from the output of the detection pulse p1 to the output of the detection pulse p2 and the time interval from the output of the detection pulse p2 to the output of the detection pulse p1. Is measured, an error signal having a level corresponding to the obtained value is generated, and frequency discrimination is performed. The error signal output from the frequency discriminating circuit 25 operates the FP / DC servo loop. FP
Since the / DC servo loop is a frequency control loop using the detection pulses p1 and p2, it is possible to widen the loop band as compared with a case where the detection pulse p1 or p2 alone constitutes a loop. Both quick response and stability can be improved. If necessary, phase control can be applied.

By this FP / DC servo loop, the rotation speed of the disk 1 can be set to a value within the range of ± several percent of the specified rotation speed. When the FP / DC servo loop is in the locked state, the HD detection in the synchronization detection circuit 30 becomes possible and the HD detection signal e2 is output. FP / D
Within a predetermined time after the C servo loop is turned on, this FP / DC servo loop is locked and the HD
When the detection signal e2 is output, the FP / DC servo loop is turned off and H at the same time in steps S7 to S10.
The D servo loop is turned on, and coarse adjustment of the time axis by the HD signal is started.

Since the HD signal has a higher frequency rate than that of the disk code, it is possible to improve loop characteristics such as widening the loop band of the spindle servo loop by turning on the HD servo loop. Good stability. Further, the detection pulse p1,
When p2 is not output within a predetermined time after startup, and within a predetermined time after the FP / CD servo loop is turned on, the FP / CD servo loop is locked and the HD detection signal e2 is output. If not, and if the HD servo loop is not turned on within a predetermined time after turning on and the detection pulses p1 and p2 are not output, the FG servo loop is turned on in step S13. This FG servo loop is for protection when disc code detection and FP detection cannot be performed, and when the FG servo loop is turned on,
The rotation speed of the spindle motor 2 is controlled so that the output voltage of the F / V conversion circuit 4 becomes equal to the reference voltage output from the reference voltage generation circuit 6.

The operation at the time of activation has been described above. The operation of the controller 10 in one scan mode of the special reproduction mode and the operation of each part associated therewith will be described with reference to the flowchart of FIG. Controller 10
When the scan mode command is received from the operation unit, the interrupts the subroutine of FIG. 5 into the main routine and executes it.
In this subroutine, first, the second frame write completion pulse W2 from the write address controller 29a.
(Step S20), when this is received, the write stop command WDE flag is set and the memory read mode change command R2 flag is set (step S21). When the R2 flag is set, the read address controller 29b repeatedly reads only the second frame after reading the first frame once.

Then, according to the command SD, the spindle servo is switched to the FP / DC loop side and the slider (not shown)
To fast-forward (step S22). Then LD
Frequency discrimination circuit 25 for E (latch disable) command
Is supplied to the frequency discriminating circuit 25 to hold the immediately preceding frequency discriminating result.
The oscillation control of O37 is switched to the PLL based on the reference clock (step S23). Then, the tracking servo loop is turned off for about 10 ms (steps S24 and S2).
5, S26), the reading point 7a is caused to perform a track jump operation, that is, a jump operation. Then, the LDE command is released and the frequency discriminating operation of the frequency discriminating circuit 25 is restarted (step S27). Next, wait for the servo lock detection signal 1 from the frequency discrimination circuit 25 (step S2
8) When this is received, the oscillation control of the VCO 37 is switched to be performed by the HD signal (step S2).
9). The HD signal can be detected from the read signal while the FP / DC servo is locked. The oscillation control is switched by detecting the first p1 pulse after receiving the signal 1.

Next, when the HD detection OK signal d is detected (step S30), it is determined that the PLL servo for the VCO 37 is locked, and the WDE command is reset or released based on the next p1 detection timing (step S31). ). As a result, the memory 29 starts writing the reproduction signal data after A / D conversion in order from the first frame. When the W1 flag is issued from the write address controller 29a, this is detected (step S32), and R
2 Reset or cancel the flag (step S3)
3). As a result, the read address controller 29b specifies the read address so as to read the first frame as well. When the W2 flag is confirmed (step S34), it is determined that the writing of the second frame is completed, and the R2 flag designating the read mode in which the first frame is read once and then only the second frame is repeatedly read is set. At the same time, a WDE command is given to the write address controller 29a to prohibit the write operation (step S35). Then, if it is determined that the scan mode has not ended, the operations after step S23 are repeated (step S36).

According to the memory read control by the R2 flag described above, the discontinuous portion of the read signal due to the jump operation in the scan mode is immediately before the memory 29.
Since the second frame of the two-frame video signal read in is repeatedly output, a clear reproduced image can be obtained. Of course, the first and second frames may be read repeatedly.

Although the circuit of FIG. 1 uses the A / D converter 21, the A / D converter 21 is not necessary when the sampled video signal is recorded as a digital signal. Also, in the latter part of the memory 29, there is
It is also conceivable to provide a converter for analog output. Further, in order to correspond to the pause mode as another special reproduction mode, step S in the flowchart of FIG.
The slider fast-forward of 22 may be deleted, and the one track jump back operation may be performed in step S25. Furthermore, for the frame advance mode, the slider fast-forward in step S22 may be deleted and the waiting operation in step S25 may be changed to a jump-back operation of, for example, about 10 frames.

[0043]

As is apparent from the above description, in the recording disk playing device according to the present invention, during the special reproduction mode, the spindle servo is performed by the FP / DC loop while the read signal is written in the memory. Since the clock phase control of is performed by the HD signal in the read signal, the servo lock of the spindle servo system can be obtained in a short time, while two frames to the memory for compensating the discontinuity of the read signal. Is correctly written, and a quick special reproduction mode operation is performed, while a reproduced image without disturbance can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a format of a disc code in a MUSE signal.

FIG. 3 is a block diagram showing a circuit example of a frequency discriminating circuit in the apparatus of FIG.

4 is a flowchart showing an operation of a processor in the apparatus of FIG.

5 is a flowchart showing an operation of a processor in the apparatus of FIG.

[Explanation of symbols for main parts]

 2 Spindle motor 9, 11, 34 Changeover switch 10 System controller 20 Disk code reading circuit 25, 33 Frequency discrimination circuit 30 Synchronization detection circuit 31 Phase comparison circuit 40 Reset circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Nagaki 4,2610 Hanazono, Tokorozawa, Saitama Pioneer Co., Ltd. Tokorozawa Plant (72) Inventor Tetsuya Tenma 4-2610 Hanazono, Tokorozawa, Saitama Pioneer Co., Ltd. Tokorozawa Plant (72) Inventor Masami Oishi 426-10 Hanazono, Tokorozawa, Saitama Prefecture Pioneer Co., Ltd. Tokorozawa Plant

Claims (1)

[Claims] 1. A first synchronization signal having a predetermined level point as a phase reference point of a sampling timing signal, and a second synchronization signal generated at a cycle N times (N is a natural number) times the first synchronization signal, in addition to the first synchronization signal. A recording disk playing device for playing a recording disk carrying a sampled video signal in which a control code is inserted at the same cycle as a second sync signal, the recording disk playing device being turned on in response to a first command. And a first spindle servo loop that controls the rotational speed of the recording disk based on a first synchronization signal in the read signal obtained from the above, and a control code in the read signal that is turned on in response to a second command. Each time the second scanning is performed, a second signal is generated, and time axis control is performed by controlling the rotation speed of the recording disk based on the time interval between the detection signal and the second synchronization signal in the read signal. A pindle servo loop, a tracking servo means for performing a jump operation on the reading point in response to a jump command, and a sampled video signal in the reading signal is sequentially taken in for each unit section in synchronization with a writing clock and used as a reading clock. Memory means for sequentially reading the data, the write clock as a reference clock, and the first clock
A write clock generating means for generating it based on the timing of either one of the synchronizing signals, and during the special reproduction mode, the second command instead of the first command.
While issuing the command, the jump command is issued and the second command is issued.
A recording disk playing device comprising: control means for causing the write clock generating means to generate the write clock based on the first synchronizing signal during a spindle servo lock period.