JP3028819B2 - Lock / unlock detection circuit of PLL circuit - Google Patents

Lock / unlock detection circuit of PLL circuit

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Publication number
JP3028819B2
JP3028819B2 JP01194115A JP19411589A JP3028819B2 JP 3028819 B2 JP3028819 B2 JP 3028819B2 JP 01194115 A JP01194115 A JP 01194115A JP 19411589 A JP19411589 A JP 19411589A JP 3028819 B2 JP3028819 B2 JP 3028819B2
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Japan
Prior art keywords
circuit
signal
pll
pll circuit
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP01194115A
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Japanese (ja)
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JPH0360291A (en
Inventor
益雄 梅本
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Hitachi Ltd
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Hitachi Ltd
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Publication of JP3028819B2 publication Critical patent/JP3028819B2/en
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  • Engineering & Computer Science (AREA)
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はデイジタルVTRに関し、特に位相同期（Phase
Lock Loop以下、PLLと略す。）回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital VTR, and in particular, to a phase lock (Phase
Hereinafter, PLL is abbreviated as PLL. ) Circuit.

〔従来の技術〕 従来からPLL回路をデイジタルVTRのクロツク抽出回路
に用いる事は多くの提案があり、例えば特公昭62−4737
5に示されている。[Prior art] There have been many proposals to use a PLL circuit for a clock extraction circuit of a digital VTR. For example, Japanese Patent Publication No. Sho 62-4737
Shown in Figure 5.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上記した例の如き従来技術は、PLL回路のデイジタルV
TRへの適用に関する種々の課題（例えば、記録時と異な
る速度で再生するときのPLLの構成，応答性の改善な
ど）に対する対策を提供している。しかし、デイジタル
VTRでは磁気テープと磁気ヘツドが接触した状態で使用
することが前提とされるため、例えば、磁気テープにキ
ズがつく、磁気ヘツドにゴミが付くなどの事故が発生
し、再生信号のS/Nが極端に低下し、再生データからク
ロツク成分が抽出できない状態が発生することがある。The prior art, such as the example described above, uses a digital V
It provides countermeasures against various problems related to application to TR (for example, PLL configuration when reproducing at a different speed from recording, improvement of responsiveness, etc.). But digital
VTRs are assumed to be used with the magnetic tape in contact with the magnetic head.For example, an accident such as scratching the magnetic tape, dust on the magnetic head, etc. occurs, and the S / N Is extremely reduced, and a state in which a clock component cannot be extracted from reproduced data may occur.

従来のPLL回路においてはこれらの対処について充分
な検討がなされておらず、デイジタルVTR全体のシステ
ムとしての使い勝手が低いという問題点があつた。In the conventional PLL circuit, these measures have not been sufficiently studied, and there is a problem that the usability of the entire digital VTR as a system is low.

本発明の目的はこのように、PLLのクロツクと再生デ
ータがアンロツク状態になつた事を検出し、デイジタル
VTR全体を制御するシステムにアラーム信号を発生さ
せ、装置の停止などの処置を取らせるなどの処理を取ら
せ、VTRシステムの信頼性を向上させる１つの手段を提
供することである。The object of the present invention is to detect that the clock of the PLL and the reproduced data are in an unlocked state,
An object of the present invention is to provide a means for improving the reliability of a VTR system by causing a system that controls the entire VTR to generate an alarm signal and take measures such as taking measures such as stopping the apparatus.

〔課題を解決するための手段〕[Means for solving the problem]

上記目的を達成するために、本発明においては磁気テ
ープから得られた再生データはテープヘツド系の周波数
特性を補償され、その後、２値信号とされる。さらにこ
の信号の立上り，立下りで所定のパルス幅を持つパルス
を発生させ、PLL回路で発生させたクロツクを上記パル
スでラツチする。ラツチ出力はデイジタルVTRの全体シ
ステムの要求に従つて加工され、アラーム情報等に利用
される。In order to achieve the above object, in the present invention, reproduced data obtained from a magnetic tape is compensated for frequency characteristics of a tape head system, and then converted into a binary signal. Further, a pulse having a predetermined pulse width is generated at the rise and fall of this signal, and the clock generated by the PLL circuit is latched by the pulse. The latch output is processed according to the requirements of the entire system of the digital VTR and used for alarm information and the like.

〔作用〕[Action]

PLL回路で発生させたクロツクは本来再生データに同
期するように作製されているので、再生データで発生さ
せた所定パルスで、クロツクをラツチすると、正常（ロ
ツク）状態では、ラツチ出力はハイレベルを保つ。一
方、アンロツク状態ではランダムにハイレベル，ローレ
ベルが現われる。よつて、このラツチ出力を用いれば、
容易にPLL出力クロツクと再生データ間のロツク状態を
検出することができる。The clock generated by the PLL circuit is originally made to synchronize with the reproduction data. Therefore, when the clock is latched with a predetermined pulse generated by the reproduction data, the latch output becomes a high level in a normal (lock) state. keep. On the other hand, in the unlocked state, a high level and a low level appear at random. Therefore, if this latch output is used,
The lock state between the PLL output clock and the reproduced data can be easily detected.

上記手段，作用の説明から、本発明は記録に用いた変
調コードと無関係にPLLのロツク，アンロツク状態が検
出できる。From the above description of the means and operation, the present invention can detect the locked or unlocked state of the PLL irrespective of the modulation code used for recording.

〔実施例〕〔Example〕

以下、本発明の一実施例を図によつて説明する。第１
図は実施例における信号系統図であり、第２図は第１図
の各部の波形を示す。Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First
FIG. 2 is a signal system diagram in the embodiment, and FIG. 2 shows waveforms at various parts in FIG.

磁気テープ１に記録されていた信号は磁気ヘツド２に
よつて再生され、再生等化回路３でテープヘツド系の周
波数特性が補正され、２値の信号Ａとなる。信号Ａの立
上り，立下りにおいて、再生データのパルス間隔の半分
に相当するパルス幅を有するパルスＢがパルス発生回路
４で発生させられる。PLL回路11は位相検出回路5,ロー
パスフイルタ6,電圧制御発振回路７で構成される。The signal recorded on the magnetic tape 1 is reproduced by the magnetic head 2, the frequency characteristic of the tape head system is corrected by the reproduction equalizing circuit 3, and the binary signal A is obtained. At the rise and fall of the signal A, the pulse generator 4 generates a pulse B having a pulse width equivalent to half the pulse interval of the reproduced data. The PLL circuit 11 includes a phase detection circuit 5, a low-pass filter 6, and a voltage-controlled oscillation circuit 7.

パルスＢは位相検出回路５に入力され、電圧制御発振
回路７のクロツク出力Ｃとの間の位相が検出される。位
相検出回路５の出力である位相誤差信号はローパスフイ
ルタ６を介して電圧制御発振回路７に入力され、再生デ
ータパルスＢとクロツクＣが同期するようにフイードバ
ツクループが形成される。The pulse B is input to the phase detection circuit 5, and the phase between the pulse B and the clock output C of the voltage controlled oscillation circuit 7 is detected. The phase error signal output from the phase detection circuit 5 is input to the voltage controlled oscillation circuit 7 via the low-pass filter 6, and a feedback loop is formed so that the reproduced data pulse B and the clock C are synchronized.

信号Ｂの立下りでクロツク出力Ｃをラツチ回路８でラ
ツチすると、ラツチ出力Ｄは第２図のように信号Ｂとク
ロツクＣが同期している場合、ハイレベルとなる。When the clock output C is latched by the latch circuit 8 at the falling edge of the signal B, the latch output D becomes high when the signal B and the clock C are synchronized as shown in FIG.

信号ＢとクロツクＣが同期していない場合はＤ′のよ
うな信号となり、ハイレベルとローレベルがランダムに
現われる。When the signal B and the clock C are not synchronized, the signal becomes like D ', and the high level and the low level appear at random.

ローパスフイルタ９を通せば、信号ＤあるいはＤ′の
レベルがそれぞれおよそＶおよび1/2V（ただしＶは信号
Ｄのパルス高）として得られるので、比較回路10の一方
の入力に3/4Vの電圧を与えておけば、比較回路10の出力
はPLL回路が再生データに同期しているかどうかを示す
ことになる。When the signal D or D 'is passed through the low-pass filter 9, the level of the signal D or D' can be obtained as approximately V and 1 / 2V (where V is the pulse height of the signal D). , The output of the comparison circuit 10 indicates whether the PLL circuit is synchronized with the reproduced data.

その他の実施例としては、第３図に示すように信号Ｄ
をデイジタルVTR全体をコントロールするシステム系12
に送り、ラツチ回路12−１で間欠的に信号Ｄをシステム
に取り込む。間欠周期としてはたとえばテレビジヨンの
フイールド周期（約15msec）とすることが適当である。In another embodiment, as shown in FIG.
12 to control the entire digital VTR
And the signal D is intermittently taken into the system by the latch circuit 12-1. As the intermittent cycle, for example, the field cycle of the television (approx. 15 msec) is appropriate.

取り込んだ信号Ｄが連続ｎ回（ｎは10回程度で良い）
ローレベルであれば、PLL回路がアンロツク状態である
と判断できる。勿論ハイレベルが現われている時はロツ
ク状態を表示する命令とする。The captured signal D is continuous n times (n may be about 10 times)
If the level is low, it can be determined that the PLL circuit is in the unlocked state. Of course, when the high level appears, it is an instruction to display the lock state.

なお、VTRを記録時と異なるテープ速度で再生する、
いわゆるシヤトル再生やスロー再生を行なう場合があ
る。この場合、記録トラツクを横切るように再生ヘツド
が移動するので、再生信号はとぎれとぎれになる。この
ため、ノーマル再生以外ではPLL回路のアンロツクはPLL
回路以外の原因で発生する。従つてノーマル再生以外で
はPLL回路のアンロツクを表示しない事にする。また、
ノーマル再生時でしかも連続ｎ回信号Ｄがローレベルに
なつた時にアンロツク表示の命令を出すようにすること
もできる。The VTR is played back at a different tape speed than when recording,
In some cases, so-called shuttle reproduction or slow reproduction is performed. In this case, since the reproduction head moves across the recording track, the reproduction signal is interrupted. Therefore, the unlock of the PLL circuit is the
Occurs due to something other than a circuit. Therefore, the unlock of the PLL circuit is not displayed except for the normal reproduction. Also,
It is also possible to issue an unlock display command during normal reproduction and when the signal D becomes low level continuously n times.

なお、ノーマル再生時の中に同期再生（記録しながら
再生する場合）の状態も含めることができる。Note that the state of synchronous reproduction (when reproducing while recording) can be included in the normal reproduction.

〔発明の効果〕〔The invention's effect〕

本発明によれば、ノーマル再生時や同時再生時におい
て、PLLが正常に動作しているかどうかの情報を容易に
検出でき、それを表示させるシステムが実現できる。こ
のため、異常が発生した場合の故障場所をすばやく限定
することが可能となり、信頼性の高いVTRの操作が可能
となる。According to the present invention, it is possible to realize a system that can easily detect information indicating whether or not the PLL is operating normally during normal reproduction or simultaneous reproduction, and display the information. For this reason, it is possible to quickly limit a failure location when an abnormality occurs, and to operate the VTR with high reliability.

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明の一実施例の検出回路の回路ブロツク
図、第２図は第１図における各部の信号波形図、第３図
は別の実施例のシステムフロー図である。 ３……再生等化回路、８……ラツチ回路、11……PLL回
路。FIG. 1 is a circuit block diagram of a detection circuit according to one embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part in FIG. 1, and FIG. 3 is a system flow diagram of another embodiment. 3 ... Reproduction equalization circuit, 8 ... Latch circuit, 11 ... PLL circuit.

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H04N 5/76 - 5/956 H03L 7/00 - 7/26 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H04N 5/76-5/956 H03L 7 /00-7/26

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】記録媒体からディジタル信号を再生するた
めの手段と、上記再生されたディジタル信号に同期した
クロックを発生するためのPLL回路と、上記ディジタル
信号から生成したラッチ信号に応答して上記PLL回路の
出力クロックをラッチするラッチ回路とを有し、上記再
生されたディジタル信号に応じて、前記ラッチ回路の出
力状態変化を選択的に利用し、所定の再生データによっ
てアンロック状態の有無を表示する手段を備えたことを
特徴とするディジタルVTR。A means for reproducing a digital signal from a recording medium; a PLL circuit for generating a clock synchronized with the reproduced digital signal; and a PLL circuit responsive to a latch signal generated from the digital signal. A latch circuit for latching an output clock of a PLL circuit, and selectively using an output state change of the latch circuit in accordance with the reproduced digital signal to determine presence or absence of an unlock state by predetermined reproduction data. A digital VTR comprising a display means.
JP01194115A 1989-07-28 1989-07-28 Lock / unlock detection circuit of PLL circuit Expired - Lifetime JP3028819B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP01194115A JP3028819B2 (en) 1989-07-28 1989-07-28 Lock / unlock detection circuit of PLL circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01194115A JP3028819B2 (en) 1989-07-28 1989-07-28 Lock / unlock detection circuit of PLL circuit

Publications (2)

Publication Number Publication Date
JPH0360291A JPH0360291A (en) 1991-03-15
JP3028819B2 true JP3028819B2 (en) 2000-04-04

Family

ID=16319173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01194115A Expired - Lifetime JP3028819B2 (en) 1989-07-28 1989-07-28 Lock / unlock detection circuit of PLL circuit

Country Status (1)

Country Link
JP (1) JP3028819B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2788564B2 (en) * 1992-02-10 1998-08-20 ワイケイケイ株式会社 Hook-and-loop fastener assembly for seat cushion
JP2788565B2 (en) * 1992-02-10 1998-08-20 ワイケイケイ株式会社 Hook-and-loop fastener for seat cushion
JP2708084B2 (en) * 1992-03-23 1998-02-04 ワイケイケイ株式会社 Method of attaching hook-and-loop fastener to seat cushion material and foam molding die

Also Published As

Publication number Publication date
JPH0360291A (en) 1991-03-15

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