JPH0541040A - Demodulator - Google Patents

Abstract

PURPOSE:To suppress an excessive voltage fluctuation by fixing the voltage of a voltage controlled oscillator to a reference voltage right after the lead and lag signals which are provided when a phase difference is generated between data pulses and data window clocks. CONSTITUTION:When a phase detecting section 1 detects a phase difference between data pulses and data window clocks, a lock filter section 3 generates a voltage corresponding to the phase difference and inputs it to a switching section 6. Furthermore, a reference voltage generating section 4 generates a fixed reference voltage corresponding to a reference read speed and inputs the voltage to the switching section 6. The switching section 6 switches the voltage from the filter section 3 to the voltage from the generating section 4 for a prescribed duration in accordance with the timing of the lead signals and the lag signals generated by the detecting section 1 and outputs the voltage. Therefore, the voltage of a voltage controlled oscillator 8 becomes a fixed reference voltage. By this, an excessive voltage fluctuation caused by the lead and lag signals is suppressed, a mislock of the data window is eliminated and exact data are read.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator used when reading digital data from, for example, a magnetic recording medium.

[0002]

2. Description of the Related Art It is well known that a magnetic disk device such as a floppy disk has a separator function by a PLL using a VCO as a means for separating digital data in the MFM system. Most magnetic tapes are of the rotary head type because of problems with tape speed and synchronization. In addition, fixed tapes and other tapes with slow tape speeds have hardly been realized due to extreme wow and flutter and frequency characteristics. A conventional MFM is described below with reference to the drawings.
The reading of digital data records will be described.

FIG. 3 is a block diagram thereof. First, the MFM data pulse read from the disk or tape and the data window clock from the voltage controlled oscillator 15 are input to the phase detector 11, where the phase difference is detected and the phase difference data is delayed or advanced. The signal is input to the charge pump unit 12. The charge pump unit 12 supplies a current to the lock filter unit 13 for a time corresponding to the phase difference, and the lock filter unit 13 generates a voltage corresponding to the phase difference. The generated voltage is amplified by the amplifier 14 and sent to the voltage controlled oscillator (VCO) 15 as a command voltage.
In this way, the feedback of the oscillation frequency is applied to the data window clock. Note that such a device is usually called a variable frequency oscillator or VFO.

[0004]

However, in the magnetic tape recording / reproducing apparatus (compact cassette, microcassette, etc.) such as the fixed head described above, the writing position becomes unstable due to wow and flutter, frequency characteristics, etc. during writing ( Phenomena (including peak shift) are likely to occur, and a misclock phenomenon that is stable at a data window clock with an abnormal frequency even during reading is likely to occur.

Moreover, in such a magnetic tape recording / reproducing apparatus such as a fixed head, a variable frequency oscillator (VF) is used.
O) has a wide dynamic range in order to improve followability to speed fluctuations. Therefore, when the data window clock becomes slow due to some reason such as peak shift, there is a problem that the data window clock mislock phenomenon is likely to occur.

A concrete description will be given with reference to the example shown in FIG. This is a case where the read data pulse pattern “4E” in FIG. 4 is to be read. When the data window clock is delayed due to fluctuations in wow, flutter, peak shift, etc., the data window that should become a normal pattern as shown in FIG. 4 (A), for example, has an abnormal pattern state shown in FIG. 4 (B). It locks with. As described above, in the conventional configuration, there is a possibility of mislocking with a down of about 25%. As a result, "4E" is erroneously recognized as "00".

The present invention is intended to solve the above problems,
It is an object of the present invention to provide a demodulation device that can eliminate the data window clock and read data accurately.

[0008]

In order to achieve the above object, the present invention includes a reference voltage generator for generating a fixed reference voltage preset according to a reference read speed, and a phase detector. UP signal and DO
A timing control unit that generates a timing signal for switching the voltage of the lock filter unit and the voltage of the reference voltage generation unit according to the timing of the WN (delay) signal, and an UP (advance) signal or a DOWN (delay) signal by this timing signal.
Immediately after the signal is generated, the voltage controlled oscillator is provided with a switching unit that applies the voltage from the reference voltage generator instead of the voltage from the lock filter unit for a predetermined period.

[0009]

According to the present invention, when the phase difference between the read data pulse and the data window clock occurs, the voltage controlled oscillation immediately after the UP (advance) signal and the DOWN (delay) signal corresponding to the data shift is realized by the above-mentioned structure. Since the input voltage of the unit is forcibly fixed to the fixed reference voltage level, U
It is possible to suppress extreme voltage fluctuations due to P and DOWN.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will be given below of a case where the demodulator of the present invention is used in a magnetic tape reading device as an embodiment.

FIG. 1 is a block diagram showing the configuration of a data separator section of a variable frequency oscillator (VFO) according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a phase detector for detecting a phase difference between MFM modulated digital data (read data pulse) read from a magnetic tape and reproduced and a data window clock for a data separator.
Reference numeral 2 is a charge pump unit that controls the control of the lock time constant based on the phase difference, 3 is a lock filter unit that generates a voltage corresponding to the phase difference based on the lock time constant, and 4 is a fixed reference voltage that corresponds to the reference read speed. The reference voltage generator 5 is a timing controller which generates a control signal for switching the voltages of the lock filter 3 and the reference voltage generator 4 according to the timing of the phase detector 1, and 6 is a switching unit which performs a switching operation according to the timing signal. Is an amplifying unit for amplifying the voltage of the lock filter unit 3 or the reference voltage generating unit 4 washed by the switching unit 6, 8 is a voltage controlled oscillating unit for controlling the cycle of the data window clock by the amplified voltage, and 9 is The data for obtaining the data pulse by the MFM modulated digital data and the data window clock. A data separator unit.

The operation of the VFO data separator unit having the above components will be described with reference to FIGS. 1 and 2.

Considering the case where the "A2" data pulse and the data window clock shown in FIG. 2 are input to the phase detection unit 1, the phase detection unit 1 outputs both phase difference signals UP (advance), It is transmitted to the charge pump unit 2 as DOWN (delay), and the charge pump unit 2 performs UP, DO
An electric current is passed through the lock filter unit 3 only for a time corresponding to WN. As a result, a signal having a voltage waveform corresponding to UP and DOWN is input from the lock filter unit 3 to the switching unit 6. Further, the reference voltage generator 4 generates a fixed reference voltage for obtaining a data window clock speed that matches a basic data rate from a tape or the like. Then, the signal of the fixed reference voltage is also input to the switching unit 6. The switching timing of the switching unit 6 is U obtained from the phase detection unit 1.
It is performed by using the P signal and the DOWN signal as a trigger. Specifically, the UP signal and the DOWN signal generated due to the phase difference between the data pulse and the data window clock are input to the timing control unit 5, and the timing control unit 5 uses UP, D
The switching unit 6 is switched to the reference voltage generating unit 4 side for a time period of 1/2 data window clock width from the falling edge of the OWN signal, and the fixed reference voltage from the reference voltage generating unit 4 is applied to the voltage controlled oscillator 8. As a result, (e) of FIG.
The voltage having the waveform as shown in FIG. The amplifying unit 7 amplifies the voltage so that it becomes a proper voltage with respect to the data window clock, and the amplified voltage is input to the voltage control oscillating unit 8 where the UP and DOWN of the phase detecting unit 1 are performed.
The oscillation frequency is controlled for the signal, and as a result, the data window clock is made to follow the read data pulse.

In the present embodiment, as described above, UP, DOWN signal voltage waveforms corresponding to the phase difference between the read data pulse and the data window clock are compared with UP,
Since it is always clamped to the fixed reference voltage that becomes the center frequency for a fixed time at the falling edge of the DOWN signal, it is possible to prevent the mislock of the conventional example shown in FIG.
It is effective as a data separator for cassette tapes with large flutter.

[0015]

As is apparent from the above embodiments, according to the present invention, a phase detector for detecting a phase difference between digital data and a data window clock for data separation, and a lock time constant control by the phase difference. A reference that generates a fixed reference voltage that corresponds to the reference read speed in a device that includes a charge pump unit that controls the voltage, a lock filter unit that generates a voltage corresponding to the phase difference based on the lock time constant, and a voltage-controlled oscillation unit. The voltage generator, the UP signal generated by the phase detector, and the DO signal
In accordance with the timing of the WN (delay) signal, immediately after the UP (advance) signal or the DOWN (delay) signal is generated, the voltage from the reference voltage generation unit is supplied to the voltage controlled oscillation unit instead of the voltage from the lock filter unit. Since the switching unit for adding the period is provided, immediately after the UP (advance) signal and the DOWN (delay) signal corresponding to the data shift when the phase difference between the read data pulse and the data window clock occurs, the voltage controlled oscillator The input voltage of 1 is forcibly fixed to the fixed reference voltage level, it is possible to suppress an extreme voltage fluctuation due to UP and DOWN, and it is possible to provide a demodulation device that eliminates the mislock of the data window and accurately reads the data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a demodulation device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the demodulator in comparison with a conventional demodulator.

FIG. 3 is a block diagram showing a configuration of a conventional demodulation device.

FIG. 4 is a timing chart showing the operation of a conventional demodulation device.

[Explanation of symbols]

 1 Phase Detection Section 2 Charge Pump Section 3 Lock Filter Section 4 Reference Voltage Generation Section 5 Timing Control Section 6 Switching Section 7 Amplification Section 8 Voltage Control Oscillation Section 9 Data Separation Section

Claims (1)

[Claims] 1. A phase detection unit for detecting a phase difference between digital data and a data window clock for a data separator, a charge pump unit for controlling control of a lock time constant by the phase difference, and a phase difference for the lock time constant. A lock filter unit that generates a corresponding voltage,
A reference voltage generator that generates a fixed reference voltage corresponding to the reference read speed, a timing controller that generates a switching control signal according to the timing of the phase detector, and the lock filter unit and the reference voltage generator based on the switching control signal. A switching unit that switches the output of the unit, an amplification unit that amplifies the voltage of the lock filter unit or the reference voltage generation unit selected by the switching unit, and a speed of the data window clock by the output voltage of the amplification unit. A demodulator comprising a voltage controlled oscillator for controlling and a data separator for obtaining a data pulse by the digital data and the data window clock.