JPH0741217Y2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial field of application The present invention relates to a PLL circuit for extracting a synchronous clock signal from a reproduced signal, and particularly to a synchronous clock suitable for a reproduced signal transmitted intermittently. The present invention relates to a PLL circuit that extracts a signal.

(B) Prior Art Conventionally, a PLL circuit as shown in the block diagram of FIG. 3 has been provided.

In the figure, 1 is an input terminal to which a reproduced signal recorded on a recording medium is amplified and supplied by a reproducing head amplifier (not shown), 2 is a PLL circuit, which is a phase comparison circuit, a low-pass filter (hereinafter referred to as LPF), and a voltage. It is composed of a controlled oscillator (hereinafter referred to as VCO). 3 is a phase comparison circuit that compares the phase of the clock signal in the input reproduction signal with the output signal of the VCO, and 4 is an LP for removing high frequency components and noise.
F and 5 are VCOs which oscillate under voltage control, and 6 is an output terminal of the PLL circuit 2 which outputs a synchronous clock signal.

The reproduction signal applied to the input terminal 1 is supplied to the phase comparison circuit 3. On the other hand, the phase comparison circuit 3 includes the PLL circuit 2
The output signal of VCO5 which is the output signal of is fed back and added.

In the phase comparison circuit 3, the clock signal in the reproduction signal and VCO5
Phase comparison of the oscillation signals is performed, and the compared phase difference is detected and output.

This phase difference signal is supplied to the LPF 4, removes unnecessary high frequency components and noise, and has a lock holding function of the PLL circuit 2 by a filter capacitor.

The phase difference signal is applied to the VCO 5 as a correction signal voltage of the oscillation frequency through the LPF 4, and the VCO 5 is frequency-controlled by the correction signal voltage so as to match the clock signal of the reproduction signal.

This VCO5 frequency control finally outputs the VCO5 output signal to the output terminal 6 accurately in synchronization with the clock signal of the reproduction signal at the lock-up time.

The lock-up time of the PLL circuit 2 is the response speed of the PLL, and the series of these operations is largely due to the filter function of the LPF4 and is generally due to the transfer function of the filter.

That is, the performance until the PLL circuit 2 is locked by the loop is determined by the transfer function.

Also, when there is no signal at the input terminal 1 of the PLL circuit 2 and the loop lock is released, the VCO5 is in the free running state,
VCO5 oscillates at the free-run frequency.

(C) Problems to be solved by the invention An RF signal recorded by a helical scan type magnetic recording / reproducing apparatus (for example, R-DAT) having a rotating magnetic head is a period during which the rotating magnetic head contacts the magnetic tape. Only the reproduction signal is output, and there is no signal during the period when the rotary magnetic head is not in contact with the magnetic tape.

In the above-mentioned conventional PLL circuit that uses such an intermittently generated reproduction signal as an input signal, when the clock signal in the reproduction signal is extracted and the synchronous clock signal is oscillated and output, the PLL circuit The phase is locked and the synchronous clock signal is output during the period when is input, but the VCO oscillates at the free-run frequency of the PLL circuit and outputs the signal at the free-run frequency during the period when there is no signal input.

That is, in the PLL circuit, there are alternately the time of phase-locking to the input signal and the time of free-running with no signal according to the intermittent input signal.

The occurrence of the free-run state in the PLL circuit in this way is not the optimum state for the phase-locked loop operation of the PLL circuit, and the pull-in time becomes long, and the magnetic tape and rotating magnetic head are used for special playback. When the relative speed of the is changed, there is a drawback that it is easy to mislock.

The present invention has been made in view of the above points, and an object thereof is to solve the drawbacks of the conventional example and perform oscillation of an optimum free-run frequency close to phase lock operation even when there is no signal input. It is to provide a PLL circuit that supplies a control voltage to a VCO.

(D) Means for Solving the Problem A PLL circuit of the present invention is a PLL circuit that extracts a synchronous clock signal from a reproduction signal recorded on a recording medium.
A discriminating circuit for discriminating the presence or absence of a reproduced signal from the G signal, a switch controlled by the output signal of this discriminating circuit, and a transfer function switching circuit for the low-pass filter of the PLL circuit configured by a reference voltage generating section and a comparator are provided. When there is no reproduction signal, the voltage of the transfer function of the low pass filter is set by the output signal of the comparator which compares the VCO control voltage input via the switch with the reference voltage.

In addition, a sampling pulse generation circuit that generates a sampling pulse when a reproduction signal is not input from the FG signal, a switch that is controlled by the output signal of this sampling pulse generation circuit, and a sampling hold circuit with a built-in reference voltage generator are provided. A configuration in which when there is no signal, the VCO control voltage input via the switch is sampled and held by the sampling and holding circuit, and the output signal of this sampling and holding circuit is fed back to the input side of the low pass filter of the PLL circuit. Is.

(E) Action The switch controlled by the output signal of the discriminating circuit for discriminating the presence or absence of the reproduced signal is turned off (open circuit) when the reproduced signal is present, and operates in the conventional PLL circuit configuration. When there is no signal, that is, when there is no signal at the input terminal, the switch above
ON (closed circuit).

When the switch is turned on, the transfer function switching circuit is connected to the input side of the LPF circuit to make the control voltage of the VCO equal to the reference voltage built in the transfer function switching circuit. As a result, the free-run frequency of the PLL circuit is controlled by the reference voltage and oscillates.

By setting this reference voltage to an arbitrary value, the free-run frequency can be set to a desired frequency.

As another embodiment of the invention, instead of the discrimination circuit for discriminating the presence or absence of the reproduction signal, a sampling pulse generator is used to turn on / off the switch, and at the same time, a sample hold circuit for sampling and holding the VCO control voltage. Is provided
The output signal of this sample hold circuit is negatively fed back to the input side of the LPF circuit of the PLL circuit and operates as the bias voltage of the LPF circuit.

When there is no reproduction signal, this sample hold circuit outputs the built-in reference voltage value, and the VCO control voltage is set to this reference voltage value.

In this way, the free-run frequency of the PLL circuit can be determined with an arbitrary reference voltage value.

(F) Embodiment An embodiment of the PLL circuit according to the present invention will be described with reference to the block diagrams of FIGS. 1 and 2. FIG. 1 shows an embodiment using a transfer function switching circuit of a PLL circuit, and FIG. 2 shows another embodiment using a sample hold circuit.

The same parts as in the conventional example are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 1, 10 is a data discriminating circuit for discriminating the presence or absence of a reproduced signal from the FG signal, 11 is a switch operated by the output signal of the data discriminating circuit 10, 12 is a reference voltage generating circuit and a comparator, and controls VCO5. Voltage (or reference voltage)
An LPF transfer function switching circuit that returns to the input side of the LPF 4 to switch and set the LPF transfer function, 13 a comparator that constitutes the LPF transfer function switching circuit, and 14 a reference voltage generation circuit.

A reproduction signal is taken out from the recorded magnetic tape of a magnetic recording / reproducing apparatus (not shown), and this reproduction signal is applied to the input terminal 1 of the PLL circuit 2. The PLL circuit 2 extracts a clock signal from this reproduced signal, oscillates a synchronous clock signal synchronized with this clock signal, and outputs it from the output terminal 6.

As described above, the reproduction signal supplied to the input terminal 1 is an intermittent reproduction signal extracted by the helical scan type rotary magnetic head.

The intermittent reproduction signal is supplied to the phase comparison circuit 3 of the PLL circuit 2.

The data discriminating circuit 10 discriminates the presence or absence of a reproduction signal from the FG signal, and when it judges that there is input data, the data discriminating circuit 10
Output signal controls the switch 11 to be turned off (open circuit).

On the other hand, when it is determined that there is no input data, the data discrimination circuit
The output signal of 10 operates to turn on the switch 11 (closed circuit).

The data discriminating circuit 10 predicts an existing section of the reproduction data on the magnetic tape by the FG signal of the rotary magnetic head, that is, a section in which the rotary magnetic head comes into contact with the magnetic tape and takes in the reproduction data, and the FG signal The presence or absence of the input reproduction signal of the PLL circuit is determined.

The switch 11 is connected to the input side of the VCO 5 that controls the voltage of the VCO 5 of the PLL circuit 2 and the LPF transfer function switching circuit 12.

When the switch 11 is OFF (open circuit), that is, when it is determined that there is an input reproduction signal, the LPF transfer function switching circuit 12 becomes an oven loop, and the PLL circuit 2 is the conventional PLL circuit 2
To work as.

When there is recorded data of the reproduction signal and the reproduction signal is supplied to the phase comparison circuit 3 of the PLL circuit 2, the clock signal in the reproduction signal and the output signal of the VCO 5 are phase-compared, and the VCO 5 The output signal is phase-locked with the clock signal of the reproduction signal and oscillates a synchronous clock signal which is accurately synchronized and is output to the output terminal 6.

When the switch 11 is ON (closed circuit), the control voltage of VCO5 passes through the switch 11 and the comparator 1 of the LPF transfer function switching circuit 12
Supplied to 3.

On the other hand, a reference voltage generation circuit 14 is connected to the input of the comparator 13, the reference voltage is compared with the control voltage of the VCO5, and the output signal of the compared comparison result is the L signal of the PLL circuit 2.
It is fed back to the input side of PF4.

The output voltage of the comparator 13 fed back to the input side of LPF4 is
It becomes the bias voltage of LPF4 and is guided to the output side of LPF4.
It operates as the voltage control voltage of VCO5.

When there is no signal at the input terminal 1, the control voltage of VCO5 becomes the unique voltage of the PLL circuit 2, and VCO5 oscillates at the free-run frequency controlled by this unique voltage, but the switch 11 turns on. Therefore, the LPF transfer function switching circuit 12 operates and L
Apply bias voltage to PF4.

The output voltage of the comparator 13 of the LPF transfer function switching circuit 12 becomes a reference voltage of the reference voltage generating circuit 14 and is supplied to the input side of the LPF 4.

That is, the control voltage of VCO5 operates so as to be equal to the reference voltage of the LPF transfer function switching circuit 12, and the free-run frequency of the PLL circuit 2 becomes the oscillation frequency voltage-controlled by this reference voltage.

In this way, the PLL circuit 2 can be arbitrarily set by the reference voltage of the LPF transfer function switching circuit 12 when there is no signal input.

When there is no signal input, if the VCO5 free-run frequency set by the reference voltage is set close to the synchronous clock frequency that is phase-locked to the clock signal of the input playback signal and oscillated by the synchronous clock signal, the PLL circuit 2 The phase lock operation can be switched smoothly depending on the presence / absence, and the lockup time of VCO5 frequency control can be shortened for stable PLL operation.

Another embodiment shown in FIG. 2 will be described with reference to the block diagram of FIG.

The same parts as those of the conventional example are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 2, 20 is a sampling pulse generating circuit that generates a sampling pulse when a reproduction signal is not input, 21 is a switch controlled by the output signal of the sampling pulse generating circuit 20, 22 is a resistor, and 23 is the sampling pulse generating circuit. A sample and hold circuit that samples and holds the control voltage of VCO5 with the sampling pulse of the circuit 20.
Reference numeral 24 is a reference voltage generator built in the sample hold circuit 23.

The sampling pulse generation circuit 20 is configured to generate a sampling pulse when the reproduction signal is not input from the FG signal, that is, when the input is no signal.

The sampling pulse generation circuit 20 generates a sampling pulse when the PLL circuit 2 is not input, and outputs the sampling pulse output signal to the switch 21 and the sample hold circuit.
Supply to 23.

When the reproduction signal is supplied to the input terminal 1, the sampling pulse generating circuit 20 does not output the sampling pulse output signal. Therefore, the common terminal C of the switch 21 is connected to the b contact, and the voltage control input side of the VCO 5 is the switch 21. It is grounded by a resistor 22 via.

That is, the control voltage of VCO5 is supplied to VCO5 by shorting the output voltage of LPF4 with the resistor 22, and controls the oscillation frequency of VCO5. As described above, the oscillation frequency of the VCO 5 at this time outputs a synchronous clock signal synchronized with the clock signal of the input reproduction signal.

When there is no signal input, the sampling pulse generation circuit 20 outputs a sampling pulse, the switch 21 is controlled by this sampling pulse signal, the common terminal C is connected to the a contact, and the input control voltage of VCO5 is this switch 21. And is supplied to the sample hold circuit 23 via.

The control voltage of VCO5 is sampled and held by the sample and hold circuit 23, and the output signal of this sample and hold circuit 23 is
Negative feedback is given to the input side of LPF4 of the PLL circuit 2.

The sample-hold circuit 23 has a built-in reference voltage generator 24, which holds the level of the sample-hold value at the reference voltage value of the reference voltage generator 24. Therefore, while the sample-hold circuit 23 is performing the sampling operation, the sample-hold circuit 23 acts on the PLL circuit 2 as a kind of low-pass filter, and the LPF of the PLL circuit 2 is affected.
The transfer function of 4 is converted by this reference voltage value, and the control voltage of VCO5 is fixed to the voltage value determined by this reference voltage.

That is, since the oscillation of the free-run frequency of VCO5 is controlled by the reference voltage of the reference voltage section 24, the free-run frequency of VCO5 can be set to the optimum value by selecting this reference voltage value as the optimum value. .

In this way, the PLL circuit 2 can operate at the optimum free-run frequency even when there is no input signal.

When the input reproduction signal is applied and the PLL circuit 2 performs the phase lock operation and outputs the synchronized clock signal in synchronization with the clock signal in the input reproduction signal, the sample hold is performed by the switch 21 as described above. Circuit 23
The negative feedback loop of is in an open state, and the sample hold circuit 23 supplies the input bias voltage of LPF4 of the PLL circuit 2.

The input bias voltage of this LPF4 is the sample hold circuit 23.
As described above, since the voltage value oscillates at the optimum free-run frequency with respect to VCO5, the input bias value of the LPF4 is kept at the optimum voltage value for the PLL circuit 2 even when the PLL circuit 2 is phase locked. Has been done.

(G) Effect of the Invention According to the PLL circuit of the present invention, when the clock signal is extracted from the reproduced signal intermittently input to generate the phase-locked synchronous clock signal, the PLL circuit in the input no-signal period Since the free-run frequency of can be set to an optimum value, there is an effect that the phase lock pull-in time of the PLL circuit can be shortened and a PLL circuit without mislock can be created.

Also, the sample-hold circuit is used to set the optimum free-run frequency when there is no input signal, as described above.
Furthermore, in the PLL circuit that receives the input signal and performs the phase lock operation, since the optimum bias voltage of the LPF can be given, the phase lock range of the PLL circuit is widened,
The effect is that a PLL circuit with a good error rate can be constructed.

Moreover, it has excellent features such as easy implementation because the circuit configuration can be simplified.

[Brief description of drawings]

1 and 2 show an embodiment of a PLL circuit according to the present invention, FIG. 1 is a block diagram, and FIG. 2 is a block diagram showing another embodiment. FIG. 3 is a block diagram of a conventional PLL circuit. Explanation of main numbers 2: PLL circuit, 3: Phase comparison circuit 4: Low-pass filter (LPF) 5: Voltage controlled oscillation circuit (VCO) 10: Data discrimination circuit 11, 21: Switch, 12: LPF transfer function switching circuit 13 : Comparator, 14, 24: Reference voltage generation circuit 20: Sampling pulse generation circuit 23: Sample hold circuit

Claims (2)

[Scope of utility model registration request] 1. A PLL circuit for extracting a synchronous clock signal from a reproduction signal recorded on a recording medium, a discrimination circuit for discriminating the presence or absence of a reproduction signal from an FG signal, and a switch controlled by an output signal of this discrimination circuit. And a transfer function switching circuit of the low-pass filter of the PLL circuit configured by a reference voltage generator and a comparator, and when there is no reproduction signal, the VCO control voltage input via the switch is compared with the reference voltage. A PLL circuit configured to set a voltage of a transfer function of a low-pass filter by an output signal of the comparator. 2. A PLL circuit for extracting a synchronous clock signal from a reproduced signal recorded on a recording medium, a sampling pulse generating circuit for generating a sampling pulse when the reproduced signal is not input from an FG signal, and the sampling pulse generating circuit. A switch controlled by the output signal of the circuit and a sampling hold circuit with a built-in reference voltage generator are provided, and when there is no reproduction signal, the VCO control voltage input via the switch is sampled and held by the sampling and hold circuit. A PLL circuit configured to feed back an output signal of the sampling and holding circuit to an input side of a low-pass filter of the PLL circuit.