JPH0568021B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a reproducing device, and particularly to a reproducing device including, for example, a phase-locked circuit.

[Prior Art] This invention can be applied to many playback devices, but here we will take as an example a playback device that uses a rotating magnetic head to play back a magnetic tape that has an information track inclined with respect to the tape running direction, such as a VTR. Explain.

FIG. 1 is a diagram showing an example of a recording format of a magnetic tape, which is a recording medium. In the figure, a signal track 2 is formed on a magnetic tape 1, which is inclined with respect to the width direction of the tape 1. This signal track 2 is composed of a portion 3 where a digital information signal is recorded and a portion 4 where a pilot signal is recorded. The pilot signal may be, for example, 1/36 of the recording bit rate _CH (bits/second).
A constant frequency signal ( _CH /36) is recorded.

FIG. 2 is a diagram showing the magnetic tape running mechanism of FIG. 1. In the figure, a magnetic tape 1 is attached to a feed reel 12 driven by a drive motor 14.
to a pair of magnetic heads 11 (one of which cannot be seen in the figure because of the shadow of the drum 10) and the drum 10, which are sent from the magnetic head and rotated by the motor 22.
It is pressed against pins 16 and 17.
The magnetic tape 1 thus set is then held between the capstan 19 and the pinch roller 18, and is run by the rotation of the capstan 19. The capstan 19 is rotated by a capstan drive motor 22. Thereafter, the tape 1 is wound onto a take-up reel 13 driven by a motor 15. The rotating shaft of the magnetic head 11 is connected to a pulse generator 23 that generates pulses in synchronization with its rotation. Also, pinch roller 1
8 is connected to a pulse generator 21 which generates pulses proportional to its rotational speed.

In the playback device configured as described above, during normal playback, the magnetic head 11 traces the track 2 so that information can be read accurately.
A swing control circuit 24 controls the swing of the magnetic head 11 and the running of the magnetic tape 1 using pulses from the pulse generators 21 and 23 and other signals. In addition, in FIG. 2, for convenience, the control path of the capstan drive motor 20 by the swing control circuit 24 is omitted.

FIG. 3 is a diagram showing an example of a conventional reproduction signal processing circuit. In the figure, an information signal recorded on a magnetic tape 1 under NRZ (Non-Return-to-Zero) modulation is read out from a rotating magnetic head 11 by a rotary transformer 30. Since this read signal HF is weak, it is waveform-shaped and amplified by the waveform shaping circuit 31 to become a signal of an appropriate level (hereinafter referred to as signal NRZ), and then processed by the phase locked circuit (hereinafter referred to as PLL) 32 and signal processing. Output to the circuit. This PLL32 is a signal
A clock signal component (bit clock) included in the information signal is extracted from the NRZ, and a signal (hereinafter referred to as signal PLCK) that controls the timing of circuits that perform various signal processing in subsequent stages is output. The signal processing circuit 33 receives the signal NRZ and the signal PLCK and performs digital signal processing. Therefore,
In order for the signal processing circuit 33 to perform signal processing operations normally, the signal PLCK must always be synchronized with the signal NRZ.

FIG. 4 is a diagram showing the response of the PLL 32 to changes in the bit rate _CH of the input signal NRZ. In the figure, the horizontal direction is the bit rate _CH of the signal NRZ.
The vertical direction indicates the frequency _PLCK of the signal PLCK. Below, with reference to Figure 4, PLL32
The operation will be explained.

Now, when the bit rate _CH of signal NRZ slowly rises from a sufficiently low level, signal PLCK begins to phase synchronize with signal NRZ at _CL ( _CH = _PLCK ), and loses synchronization at _LU . Conversely, when the bit rate _CH drops slowly from a sufficiently high point, synchronization begins at _CU and goes out of synchronization at _LL . The interval [ _CH , _CU ] is called the capture range, and the interval [ _LL , _LU ] is called the lock range. Therefore,
In order for the output signal PLCK of the PLL 32 to be always phase-synchronized with the input signal NRZ, the bit rate _CH of the signal NRZ must be within the capture range of the PLL 32. In other words, it is not possible to extract the phase-synchronized signal PLCK from a signal having a bit rate outside the capture range. Therefore, if a malfunction occurs, such as when the magnetic tape 1 recorded in the double speed mode is played back at the normal mode speed, and the bit rate of the signal NRZ deviates from the predetermined capture range of the PLL 32, the conventional method shown in FIG. In the reproducing apparatus, it was not possible to extract the signal PLCK that was phase-synchronized with the signal NRZ, and the signal processing circuit 33 was unable to perform accurate signal processing.

[Summary of the Invention] The present invention eliminates the above-mentioned drawbacks and provides a system in which the output signal of the PLL is always synchronized with the input signal even when the frequency or bit rate of the input signal to the PLL is outside the capture range of the PLL. An object of the present invention is to provide a playback device configured as follows.

To summarize, this invention reproduces an information signal recorded on a recording medium and a signal of a constant period, outputs a clock signal synchronized with the reproduction signal from a phase synchronization circuit, and also outputs a signal of a constant period among the reproduction signals. By detecting the difference between the period of the constant period signal and the clock signal within the period during which the constant period signal is extracted, the deviation of the constant period signal with respect to the pull-in range of the phase synchronization circuit is detected, Based on this detection result, the pull-in range of the phase-locked circuit is controlled so that the reproduced signal always falls within the pull-in range of the phase-locked circuit.

The above objects and other objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings.

[Embodiment of the Invention] FIG. 5 is a schematic block diagram of a reproducing circuit which is an embodiment of the invention. In the figure, the signal HF is applied to a waveform shaping circuit 31 and also to a low-pass filter 34. This low-pass filter 34 is a filter that attenuates signal components other than the pilot signal. Low pass filter 34
The output signal FHF is provided to the waveform shaping circuit 35 and also to the envelope detection circuit 36. The waveform shaping circuit 35 shapes the signal FHF into a logic level signal PILOT.
Output. This signal PILOT is given to the period difference detection circuit 37. The envelope detection circuit 3
6 detects the envelope of the signal FHF and outputs a signal ENV indicating the presence of the pilot signal. The signal ENV is given to a period difference detection circuit 37. This period difference detection circuit 37 further includes a PLL.
A signal PLCK is provided from 320. The period difference detection circuit 37 detects the signal in the period in which the signal ENV is output (the period in which the pilot signal exists).
It compares the periods of PLCK and PILOT and outputs a signal FD with a pulse width corresponding to the difference in period. This signal FD is given to PLL 320.
The PLL 320 shifts the capture range based on this signal FD.

FIG. 6 is a block diagram showing an example of the period difference detection circuit 37 shown in FIG. In the figure, the signal
ENV is provided to counters 40 and 41.
The counter 40 is a counter that counts the signal PILOT from the rising edge of the signal ENV and outputs the pulse CA1 at the fourth pulse of the signal PILOT. On the other hand, the counter 41 is a counter that starts counting the signal PLCK from the rising edge of the signal ENV. The count output of the counter 41 is sent to the adder 42.
given to. This adder 42 has a counter 41
A reference value (-144 in this embodiment) is added to the count output of , and a value correlated to the frequency error between _PLCK and _PILOT is output, especially at the rising edge of pulse CA1. The most significant bit of the output of adder 42 is applied to flip-flop 43. Flip-flop 43 stores the most significant bit of adder 42 in synchronization with pulse CA1. The Q output MSB of the flip-flop 43 is applied to an up-down counter 44. The up-down counter 44 is loaded with the output of the adder 42 at the rising edge of the pulse CA1, and is driven by the signal PLCK. In addition, the up-down counter 44
performs up counting or down counting depending on the polarity (1 or 0) of the output MSB of flip-flop 43 (ie, the most significant bit of the output of adder 42). Furthermore, the up-down counter 44
outputs pulse CA2 when its count value becomes 0. This pulse CA2 is applied to flip-flop 45. The flip-flop 45 is a pulse
It is set by the rise of CA1, and pulse CA
It is reset by 2. flipflop 4
The output EN of No. 5 is applied to the buffer 46. This buffer 46 is the output of the flip-flop 45.
When EN is at a low level, it is in a high impedance state, and when it is at a high level, the output MSB of the flip-flop 43 is output.
The output of the buffer 46 is sent to the PLL320 as a signal FD.
given to.

FIG. 7 is a diagram showing signal waveforms at various parts of the circuit of FIG. 6. The operation of the above embodiment will be explained below with reference to FIG.

The signal FHF passed through the low-pass filter 34 is
An envelope detector 36 provides a signal ENV indicating the presence of the pilot signal. That is, this signal ENV is a signal that becomes high level only in the portion where the pilot signal is present. The signal FHF is also input to the waveform shaping circuit 35, and a signal PILOT is obtained in which the pilot signal portion is converted to a logic level. The counter 40 receives the signal ENV in response to the rising edge of the signal ENV.
Start counting PILOT and output pulse CA1 at the fourth pulse of signal PILOT. i.e. the signal
The time _t1 from the rise of ENV to the rise of pulse CA1 corresponds to four cycles of the pilot signal. That is, t ₁ =4/ _PILOT .

The counter 41 counts how many pulses of the signal PLCK the time _t1 corresponds to.
Start counting the signal PLCK from the rising edge of ENV. FIG. 7 shows the count value of the counter 41 as a linear graph. The number of pulses of the signal PLCK at time _t1 is given as the count value of the counter 41 at the rising edge of the pulse CA1. As mentioned above, _PILOT = _CH /36.
Also, if the signal PLCK is synchronized with the signal NRZ
_PLCK = _CH . Therefore, in the normal reproduction state, the count value N ₁ of the counter 41 at the rising edge of the pulse CA1 is N ₁ =36×4=144. When -144 is given as a reference value to the adder 42, the value Na outputted from the adder 42 becomes 0 at the rising edge of the pulse CA1 during normal reproduction.

Here, if the signal PLCK is not synchronized with the signal NRZ, N ₁ = t ₁ × _PLCK = (4 × _PLCK ) / _PILOT Na = {(4 × _PLCK ) / _PILOT }−144 = 144 {( _PLCK / _CH )−1}.

If _PLCK < _CH , Na is negative, and _PLCK >
In the case of _CH , Na is positive. Also, if the playback speed is constant ( _CH = constant), the absolute value of Na is _PLCK
is proportional to the difference between and _CH . Note that the most significant bit of the adder 42 indicates the polarity (negative or positive) of the addition result.
It has come to represent That is, the above Na
When Na is negative, its most significant bit is 1; when Na is positive, its most significant bit is 0.

The most significant bit of Na is held in flip-flop 43, and if it is 1, it is stored in up-down counter 44.
If it is 0, it will count up, and if it is 0, it will count down. FIG. 7 shows the case where Na>0.
In the case of Fig. 7, since Na > 0, the most significant bit of Na (signal MSB in Fig. 6) is 1,
The up-down counter 44 is set to Na as a count value in synchronization with the rising edge of pulse CA1.
Perform descending counting. Updown counter 44
When the count value becomes 0, the flip-flop 45 which outputs the pulse Ca2 is set by the rising edge of the pulse CA1 and reset by CA2, so that the output EN is at a high level during the period _t2.
is _t2 =|Na|/ _PLCK =144×|(1× _CH )−(1/ _PLCK )|. That is, t ₂ is the playback bit cell length (=
1/ _CH ) and the signal PLCK.

During the period _t2 , the buffer 46 outputs a signal MSB indicating the polarity of Na. Therefore, the signal FD
becomes low level when _PLCK > _CH , and becomes low level when _PLCK <
In the case of _CH , the level is high, and its pulse width is proportional to the absolute value of the difference between the reproduced bit cell length and the period of the signal PLCK.

As mentioned above, the signal FD is a signal related to the frequency error between _PLCK and _CH (that is, proportional to the period difference), and this signal is used to match the capture range of the PLL 320 with the playback bit rate.
Even if _{the CH} has changed from normal, the signal
PLCK can be synchronized to signal NRZ.

Next, how the signal FD is processed in the PLL 320 will be explained.

FIG. 8 is a block diagram showing an example of the PLL 320. In the figure, the phase comparator 50 includes a signal
NRZ and signal PLCK are provided. The phase comparator 50 detects the phase difference between the signal NRZ and the signal PLCK, and provides the detection result to the + side input terminal of the differential amplifier 51. A signal FD passed through a low-pass filter 53, that is, a signal FDL, is applied to the negative input terminal of the differential amplifier 51. The output of the differential amplifier 51 is a voltage controlled oscillator (hereinafter referred to as VCO) 5.
given to 2. This VCO 52 outputs a signal PLCK with a frequency proportional to the output of the differential amplifier 51.

Now, assuming that the voltage of the signal FDL is constant, the differential amplifier 51 does not perform any action, and the circuit in FIG. It is the same as the conventional method.

When Na < 0 ( _PLCK < _CH ), the signal FD becomes a low-level pulse, and its average voltage is (V _H +
V _L )/2 (average voltage of high level and low level)
becomes lower, raising the output voltage of the differential amplifier 51 and increasing _PLCK . As the frequency increases,
The difference between _PLCK and _CH decreases, and the pulse width of signal FD becomes shorter. By repeating this operation every time a pilot signal is input, _PLCH ≈f _CH as shown in FIG. Therefore, the signal PLCK can be synchronized with the signal NRZ.

Note that in the above embodiment, the signal FD is
Although the signal FD is applied to the PLL, the signal FD may be applied to the rotation control circuit 24 of the magnetic head 11 to match the reproduction bit rate with the capture range of the PLL 320.

Furthermore, instead of the signal PLCK, a clock generated from a crystal oscillator or the like may be used to match the reproduction bit rate with the operating speed of the signal processing section 33.

Furthermore, in the above embodiments, a recording medium having inclined tracks on the magnetic tape was used as an example, but many other recording media such as a recording medium having tracks parallel to the longitudinal direction of the tape, or a disc-shaped recording medium, etc. This invention can be applied to.

[Effects of the Invention] As described above, according to the present invention, even if the reproduction bit rate is outside the capture range of the PLL, it is possible to easily match the capture range of the PLL with the reproduction bit rate.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a recording format of a magnetic tape. FIG. 2 is a diagram showing the magnetic tape running mechanism of FIG. 1. FIG. 3 is a schematic block diagram of a conventional reproduced signal processing circuit. Figure 4 is
FIG. 3 is a diagram showing a response of a PLL to an input signal.
FIG. 5 is a schematic block diagram of a reproducing circuit according to an embodiment of the present invention. FIG. 6 is a block diagram showing details of the period difference detection circuit 37 shown in FIG. 5. 7th
This figure shows waveforms of signals at various parts of the circuit of FIG. 6. Figure 8 shows a PLL suitable for the embodiment of Figure 5.
FIG. 2 is a block diagram showing an example. FIG. 9 is a waveform diagram showing the operation of the PLL shown in FIG. 8. In the figure, 1 is a magnetic tape, 11 is a magnetic head, 30 is a rotary transformer, 31 and 35 are waveform shaping circuits, 320 is a PLL, 33 is a signal processing circuit, 34 is a low-pass filter, 36 is an envelope detection circuit, and 37 is a cycle Difference detection circuit, 40 and 41 are counters, 42 is an adder, 43 and 4
5 is a flip-flop, 44 is an up-down counter, 46 is a buffer, 50 is a phase comparator, 51
52 represents a differential amplifier, 52 represents a voltage controlled oscillator, and 53 represents a low-pass filter.

Claims (1)

[Claims] 1. Information signals are recorded in columns, and
A device for reproducing a recording medium in which a signal with a constant period is multiplexed with an information signal, comprising: a reading means for reading out the information signal recorded on the recording medium and the signal with a constant period; a phase synchronization circuit that takes as an input signal a recorded signal read out by the reading means and generates a clock signal synchronized with the recorded signal; means, period detection means for detecting a period during which a signal with a constant period is extracted by the extraction means, and a period between the clock signal and the signal with a constant period in the period detected by the period detection means. a deviation detection means for detecting a relative deviation between the pull-in range of the phase-locked circuit and the constant period signal by detecting a difference between the two; A playback device comprising a deviation correction means for correcting a relative deviation between the pull-in range and the signal of the constant period. 2. The reproducing device according to claim 1, wherein the constant period signal is a pilot signal. 3. The reproducing device according to claim 1, wherein the information signal is a video signal, and the constant periodic signal is a synchronization signal included in the video signal. 4. The reproducing apparatus according to any one of claims 1 to 3, wherein the deviation correction means includes means for controlling the reproduction speed of the recording medium. 5. The playback device according to any one of claims 1 to 3, wherein the deviation correction means includes means for controlling a change in the pull-in range of the phase synchronization circuit.